阅读说明：本技术 篡改指示封章 (Tamper indicating seal ) 是由 P·A·诺罗尼亚 D·D·甘地 D·N·卡马特 M·纳塔尼 于 2019-12-30 设计创作，主要内容包括：本公开涉及安全系统领域并且公开了篡改指示封章(100),所述篡改指示封章(100)包括篡改环路和篡改检测芯片(106)。所述篡改环路包括第一部分和第二部分。当在所述第一部分和所述第二部分之间建立电气连接时所述篡改环路闭合。所述第一部分嵌入螺栓构件(110)内并且所述第二部分嵌入外壳(116)内,使得所述螺栓构件(110)与所述外壳(116)的锁定引起所述篡改环路闭合,并且所述螺栓构件(110)的解锁引起所述篡改环路打开。所述篡改检测芯片(106)检测篡改环路闭合事件的计数,或篡改环路打开和闭合事件的计数,以有利于所述封章(100)的篡改检测。因此,即使所述封章(100)在不存在RF场的情况下被打开,也能识别篡改。(The present disclosure relates to the field of security systems and discloses a tamper-indicating seal (100), the tamper-indicating seal (100) comprising a tamper loop and a tamper detection chip (106). The tamper loop includes a first portion and a second portion. The tamper loop is closed when an electrical connection is established between the first portion and the second portion. The first portion is embedded within a bolt member (110) and the second portion is embedded within a housing (116) such that locking of the bolt member (110) with the housing (116) causes the tamper loop to close and unlocking of the bolt member (110) causes the tamper loop to open. The tamper detection chip (106) detects a count of tamper loop closing events, or a count of tamper loop opening and closing events, to facilitate tamper detection of the seal (100). Thus, tampering can be identified even if the seal (100) is opened in the absence of an RF field.)

1. A tamper-indicating seal (100), comprising:

a tamper loop having a first portion and a second portion, the tamper loop configured to close when an electrical connection is established between the first portion and the second portion; and

a tamper detection chip (106), the tamper detection chip (106) being disposed in the first portion, the tamper detection chip (106) being configured to detect events corresponding to the opening and closing of the tamper loop, and further configured to facilitate tamper detection of the seal (100) based on the detected closing events or the count of the detected opening and closing events.

2. The tamper-indicating seal (100) of claim 1, the tamper-indicating seal (100) being in the form of a bolt seal comprising a bolt member (110) and a housing (116), wherein the housing (116) is configured to receive the bolt member (110) and is further configured to facilitate a snap-lock of the bolt member (110) therein.

3. The tamper-indicating seal (100) of claim 2, wherein the first portion is embedded within the bolt member (110) and the second portion is embedded within the housing (116), wherein locking of the bolt member (110) with the housing (116) causes the tamper loop to close and unlocking of the bolt member (110) from the housing (116) causes the tamper loop to open.

4. The tamper-indicating seal (100) of claim 1, wherein the tamper detection chip (106) comprises:

a control unit (118), the control unit (118) being configured to detect events corresponding to the opening and closing of the tamper loop, and further configured to generate a close event signal upon detecting the closing of the tamper loop, and to generate an open event signal upon detecting the opening of the tamper loop;

a memory (122), the memory (122) comprising an identification register, a tamper flag register and a predetermined threshold tamper value, the identification register being configured to store a unique identification code associated with the tamper indicating seal (100);

a tamper switch (120), the tamper switch (120) configured to cooperate with the control unit (118) to receive the close event signal and the open event signal, and further configured to switch between an open state position and a closed state position based on the received close event signal and the received open event signal;

a counter (124), the counter (124) configured to store a tamper count value and further configured to cooperate with the tamper switch (120) to increment the tamper count value by one based on detection of a change in position of the tamper switch (120); and

a comparator (126), the comparator (126) being configured to cooperate with the memory (122) and the counter (124) to receive the predetermined threshold tamper value and the tamper count value, respectively, and further being configured to change the state of the tamper flag register when the tamper count value is equal to the predetermined threshold tamper value, thereby indicating tampering of the seal (100),

wherein the control unit (118), the counter (124) and the comparator (126) are implemented by one or more processors.

5. Tamper-indicating seal (100) according to claim 4, wherein the comparator (126) is configured to change at least one status bit of the identification code stored in the memory (122) when the tamper count value is equal to the predetermined threshold tamper value, thereby indicating tampering of the seal (100).

6. The tamper-indicating seal (100) of claim 4, wherein the counter (124) is a 3-bit memory and is capable of counting up to 7.

7. The tamper-indicating seal (100) of claim 4, wherein the counter (124) is configured to increment a tamper count value by one each time the tamper switch (120) switches between the open state position and the closed state position.

8. The tamper-indicating seal (100) of claim 4, wherein the counter (124) is configured to increment a tamper count value by one each time the tamper switch (120) switches to the closed state position.

9. Tamper-indicating seal (100) according to claim 4, wherein a default value of the tamper count value stored in the counter (124) is zero.

10. The tamper-indicating seal (100) of claim 4, wherein the tamper loop comprises:

at least one antenna (102), the at least one antenna (102) electrically connected to the tamper detection chip (106), the antenna (102) configured to cooperate with the memory (122) to communicate the identification code, the status of the tamper loop, the count value, and the status of the tamper flag register upon receiving a radio frequency signal from a reader (304);

a battery (108), the battery (108) configured to supply power to the control unit (118) to facilitate generation of the close event signal and the open event signal; and

a capacitor (104), the capacitor (104) configured to supply power to the control unit (118) to facilitate generation of the close event signal and the open event signal in the absence of a power source of the battery (108).

11. The tamper-indicating seal (100) of claim 10, wherein the antenna (102) is selected from the group consisting of: high frequency antennas, ultra high frequency antennas, and low frequency antennas.

12. The tamper-indicating seal (100) of claim 10, wherein the identification code, the state of the tamper loop, the count value, and the state of the tamper flag register are communicated to the reader (304) using a communication protocol selected from the group consisting of: radio Frequency Identification (RFID), long-range wide area network (LoRaWAN), Global Positioning System (GPS), and wireless fidelity (Wi-Fi).

13. The tamper-indicating seal (100) of claim 10, wherein the identification code facilitates automatic identification of a container or transport carrier (302) attached to the seal (100).

14. Tamper-indicating seal (100) according to claim 10, the tamper-indicating seal (100) being assumed to have been tampered with in case the reader (304) is not able to correctly read the unique identification code.

15. Tamper-indicating seal (100) according to claim 4, wherein the state of the tamper flag register facilitates determining whether the seal (100) has been tampered with.

16. Tamper-indicating seal (100) according to claim 5, wherein the status bit of the identification code facilitates determining whether the seal (100) is tampered with.

17. The tamper-indicating seal (100) according to claim 10, wherein the control unit (118) is configured to generate the open event signal when the battery (108) is removed without opening the tamper loop.

Technical Field

The present disclosure relates generally to the field of electronic security seals (seals). More particularly, the present disclosure relates to tamper indicating bolt-type seals.

Background

The background information that follows relates to the present disclosure, but is not necessarily prior art.

Conventional (near field communication) NFC, (radio frequency identification) RFID or dual frequency NFC + RFID security tags utilize inductive coupling technology, a process of transferring energy between an RFID tag and an RFID reader by sharing a magnetic field. The RFID reader utilizes magnetic induction to generate a radio wave field that is detected by the RFID tag. Thus, when a tag is placed in the vicinity of the reader, the magnetic field from the reader's antenna coil couples with the tag's antenna coil and induces a voltage in the tag, which is then rectified and used to power the tag's internal circuitry.

Existing passive RFID security tags/seals are only able to check and record the status of a tamper loop in the presence of the Radio Frequency (RF) field of the RFID reader. Such chips derive power from the RF field to send pulses around the tamper loop. If the pulse is successfully sent and received, the tamper check flag is set to not tampered and the seal is declared untampered. In the absence of such RF fields, a skilled counterfeiter can open and close the label/seal without changing the state of the tamper check mark. Thus, in such cases, when the tamper check mark is read by the RFID reader, it will show no tampering even if the seal/label has been tampered with.

Accordingly, there is a need for developing tamper-indicating seals that can count the number of tamper status changes of a tamper loop in real time.

Target

Some of the objectives of the present disclosure achieved by at least one embodiment herein are as follows:

it is an object of the present disclosure to ameliorate one or more problems of the prior art or at least provide a useful alternative;

it is an object of the present disclosure to provide a tamper-indicating seal.

It is another object of the present disclosure to provide a tamper-indicating seal that can record the number of times it is opened and closed.

It is yet another object of the present disclosure to provide a tamper-indicating seal that can identify tampering (even if the seal is not damaged/broken).

It is yet another object of the present disclosure to provide a tamper-indicating seal that identifies tampering, even if the seal is opened in the absence of a Radio Frequency (RF) field.

Other objects and advantages of the present disclosure will become more apparent from the following description, which is not intended to limit the scope of the present disclosure.

Disclosure of Invention

The present disclosure contemplates a tamper-indicating seal. The tamper-indicating seal includes a tamper loop and a tamper detection chip. The tamper loop includes a first portion and a second portion. The tamper loop is configured to close when an electrical connection is established between the first portion and the second portion. The tamper detection chip is disposed in the first portion. The tamper detection chip is configured to detect events corresponding to the opening and closing of the tamper loop, and is further configured to facilitate tamper detection of the seal based on the detected closing events or the count of the detected opening and closing events.

In one embodiment, the tamper-indicating seal is in the form of a bolt seal that includes a bolt member and a housing. The housing is configured to receive the bolt member and is further configured to facilitate a snap lock of the bolt member therein. A first portion of the tamper loop is embedded within the bolt member and a second portion is embedded within the housing, wherein locking of the bolt member with the housing causes the tamper loop to close and unlocking of the bolt member from the housing causes the tamper loop to open.

In one embodiment, the tamper detection chip includes a control unit, a memory, a tamper switch, a counter, and a comparator. The control unit is configured to detect events corresponding to the opening and closing of the tamperproof loop, and is further configured to generate a close event signal when the closing of the tamperproof loop is detected, and to generate an open event signal when the opening of the tamperproof loop is detected. The memory comprises an identification register, a tamper flag register and a predetermined threshold tamper value. The identification register stores a unique identification code associated with the tamper-indicating seal. The tamper switch is configured to cooperate with the control unit to receive the close event signal and the open event signal, and is further configured to switch between the open state position and the closed state position based on the received close event and open event signals. The counter is configured to store a tamper count value and is further configured to cooperate with the tamper switch to increment the tamper count value by one based on detection of a change in position of the tamper switch. The default value of the tamper count value stored in the counter is zero. In one embodiment, the counter is a 3-bit memory and can count up to 7. In one embodiment, the counter is configured to increment the tamper count value by one each time the tamper switch switches between the open state position and the closed state position. In another embodiment, the counter is configured to increment the tamper count value by one each time the tamper switch is switched to the closed state position.

The comparator is configured to cooperate with the memory and the counter to receive a predetermined threshold tamper value and a tamper count value, respectively, and is further configured to change the state of the tamper flag register when the tamper count value is equal to the predetermined threshold tamper value, thereby indicating tampering of the seal.

In an alternative embodiment, the comparator is configured to change at least one status bit of the identification code stored in the memory when the tamper count value equals a predetermined threshold tamper value, thereby indicating tampering of the seal. In one embodiment, the control unit, the counter and the comparator are implemented by one or more processors.

In one embodiment, the tamper loop includes at least one antenna, a battery, and a capacitor. The antenna is electrically connected to the tamper detection chip and is configured to cooperate with the memory to communicate the identification code, the status of the tamper loop, the count value, and the status of the tamper flag register upon receiving a radio frequency signal from the reader. The antenna is selected from the group consisting of: high frequency antennas, ultra high frequency antennas, and low frequency antennas. The identification code, the status of the tamper loop, the count value, and the status of the tamper flag register are communicated to the reader using a communication protocol selected from the group consisting of Radio Frequency Identification (RFID), long range wide area network (LoRaWAN), Global Positioning System (GPS), and wireless fidelity (Wi-Fi). The battery is configured to supply power to the control unit to facilitate generation of the closing event signal and the opening event signal. The capacitor is configured to supply power to the control unit to facilitate generation of the close event signal and the open event signal in the absence of a power source from the battery.

In one embodiment, the tamper-indicating seal is assumed to have been tampered with in the event that the reader is unable to correctly read the unique identification code. In another embodiment, the identification code facilitates automatic identification of the container or transport carrier attached to the seal.

In one embodiment, the state of the tamper flag register facilitates determining whether the seal is tampered with. Alternatively, a status bit of the identification code facilitates determining whether the seal is tampered with.

Advantageously, the control unit is configured to generate an open event signal when the battery is removed without opening the tamper loop.

Drawings

The tamper-indicating seal of the present disclosure will now be described with the aid of the accompanying drawings, in which:

FIG. 1 shows a cross-sectional view of a tamper-indicating seal of the present disclosure; and

fig. 2 shows a block diagram of a tamper detection chip of the tamper-indicating seal of fig. 1.

List of reference numerals

100-tamper indicating seal

102-antenna

104-capacitor

106-tamper detection chip

108-battery

110-bolt component

112-terminals of tamper detection chip

114-terminal for a tampered Loop in a housing

116-outer cover

118-control Unit

120-tamper switch

122-memory

124-counter

126-comparator

302-transport container/Carrier

304-reader

306-Server

Detailed Description

Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

The embodiments are provided to fully and completely convey the scope of the disclosure to those skilled in the art. Numerous details are set forth with respect to specific components and methods to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that the details provided by the examples should not be taken as limiting the scope of the disclosure. In some embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

In the present disclosure, the terminology used is for the purpose of describing particular embodiments only, and such terminology should not be taken as limiting the scope of the present disclosure. As used in this disclosure, the forms "a", "an" and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having," are open-ended transition phrases and thus specify the presence of stated features, integers, steps, operations, elements, modules, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The particular order of the steps disclosed in the methods and processes of the present disclosure should not be construed as necessarily requiring such order. It should also be understood that additional or alternative steps may be employed.

When an element is referred to as being "mounted to," "engaged to," "connected to" or "coupled to" another element, it can be directly mounted to, engaged with, connected to or coupled to the other element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed elements.

Existing passive RFID security seals can only check and record the status of a tamper loop in the presence of the Radio Frequency (RF) field of the RFID reader. In the absence of an RF field, a skilled counterfeiter can open and close the seal without changing the state of the tamper check mark. In this case, when the tamper check mark is read by the RFID reader, it will show an untampered state even if the seal has been tampered. To avoid this, a tamper-indicating seal (hereinafter referred to as "seal 100") of the present disclosure is now described with reference to fig. 1 to 3. Tamper indicating seal 100 records the number of tamper status changes to identify tampering.

Referring to fig. 1, tamper indicating seal 100 includes a tamper loop and a tamper detection chip 106. The tamper loop includes a first portion and a second portion. The tamper loop is configured to close when an electrical connection is established between the first portion and the second portion. The tamper detection chip 106 is disposed in the first portion. The tamper detection chip 106 is configured to detect events corresponding to the opening and closing of a tamper loop, and is further configured to facilitate tamper detection of the seal 100 based on the detected closing events or a count of the detected opening and closing events.

In one embodiment, tamper-indicating seal 100 is in the form of a bolt seal that includes bolt member 110 and housing 116. The housing 116 is configured to receive the bolt member 110 and is also configured to facilitate a snap lock of the bolt member 110 therein. A first portion of the tamper loop is embedded within bolt member 110 and a second portion of the tamper loop is embedded within housing 116 such that locking bolt member 110 with housing 116 causes the tamper loop to close and unlocking bolt member 110 from housing 116 causes the tamper loop to open. The tamper loop includes a tamper detection chip 106. The tamper detection chip 106 is configured to detect the number of times the tamper loop is opened and closed to facilitate tamper detection of the seal 100.

In one embodiment, the housing 116 comprises a wire having two terminals 114. The terminals 114 of the wire are configured to connect the terminals 112 of the tamper detection chip 106 located in the bolt member 110 to form a continuous tamper loop when the seal 100 is in the locked state.

Referring to fig. 2, the tamper detection chip 106 includes a control unit 118, a memory 122, a tamper switch 120, a counter 124, and a comparator 126. The control unit 118 is configured to detect events corresponding to the opening and closing of the tamperproof loop, and is further configured to generate a close event signal when the closing of the tamperproof loop is detected, and to generate an open event signal when the opening of the tamperproof loop is detected. The memory 122 comprises an identification register, a tamper flag register and a predetermined threshold tamper value. The identification register stores a unique identification code associated with the tamper-indicating seal 100. Tamper switch 120 is configured to cooperate with control unit 118 to receive the close event signal and the open event signal, and is further configured to switch between the open state position and the closed state position based on the received close event and open event signals. The counter 124 is configured to store a tamper count value and is further configured to cooperate with the tamper switch 120 to increment the tamper count value by one based on detection of a change in position of the tamper switch 120. The default value of the tamper count value stored in the counter 124 is zero. In one embodiment, counter 124 is a 3-bit memory and may count only up to 7. In an alternative embodiment, counter 124 is a 4-bit or higher memory. Once the maximum count is reached, the counter 124 is not reset to zero. In one embodiment, counter 124 is configured to increment the tamper count value by one each time tamper switch 120 switches between an open state position and a closed state position. In another embodiment, counter 124 is configured to increment the tamper count value by one each time tamper switch 120 is switched to the closed state position. The comparator 126 is configured to cooperate with the memory 122 and the counter 124 to receive a predetermined threshold tamper value and a tamper count value, respectively, and is further configured to change the state of the tamper flag register when the tamper count value is equal to the predetermined threshold tamper value, thereby indicating a tampered seal. For example, the tamper flag register may be configured to store a single bit that indicates whether the seal 100 has been tampered with. A bit value of "0" may indicate "untampered state" and a bit value of "1" may indicate "tampered state".

In an alternative embodiment, the comparator 126 is configured to change at least one status bit of the identification code stored in the memory 122 when the tamper count value equals a predetermined threshold tamper value, thereby indicating a tampered seal.

In one embodiment, the control unit 118, the counter 124, and the comparator 126 are implemented by one or more processors. The processor may be a general purpose processor, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), and/or the like. The processor may be configured to retrieve data from and/or write data to the memory. For example, the memory may be Random Access Memory (RAM), memory buffers, hard drives, databases, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), read-only memory (ROM), flash memory, hard disks, floppy disks, cloud storage, and/or the like.

The tamper loop also includes at least one antenna 102, a battery 108, and a capacitor 104. The antenna 102 is electrically connected to the tamper detection chip 106. The antenna 102 is configured to cooperate with the memory 122 to communicate the identification code, the status of the tamper loop, the count value, and the status of the tamper flag register upon receiving a radio frequency signal from the reader 304. The antenna 102 is selected from the group consisting of: high frequency antennas, ultra high frequency antennas, and low frequency antennas. In one embodiment, antenna 102 is a dual-band RFID/NFC antenna. The identification code, the status of the tamper loop, the count value, and the status of the tamper flag register may be communicated to the reader 304 using a communication protocol selected from the group consisting of Radio Frequency Identification (RFID), long range wide area network (LoRaWAN), Global Positioning System (GPS), and wireless fidelity (Wi-Fi). The battery 108 is configured to supply power to the control unit 118 to facilitate generation of the close event signal and the open event signal. The capacitor 104 is configured to supply power to the control unit 118 to facilitate generation of the close event signal and the open event signal in the absence of power from the battery 108.

In one exemplary embodiment, when the tamper loop is closed, i.e., when the bolt member 110 is locked with the housing 116, the battery 108 drives current through the tamper loop and supplies power to the control unit 118 of the tamper detection chip 106. Upon receiving power, the control unit 118 detects the closed state of the tamper loop and generates a close event signal. The control unit 118 transmits the generated close event signal to the tamper switch 120. Tamper switch 120 changes state upon receiving a close event signal. The change in state of tamper switch 120 drives counter 124 to increment the count value by one.

In another exemplary embodiment, there will be no current in the tamper loop when it is open, i.e., when bolt member 110 is removed/unlocked from housing 116. However, the battery 108 is still connected to the control unit 118 and supplies power to the control unit 118. Upon receiving power from the battery 108, the control unit 118 detects the open state of the tamper loop (i.e., no current in the tamper loop) and generates an open event signal. The control unit 118 transmits the generated open event signal to the tamper switch 120. Upon receiving the open event signal, the tamper switch 120 returns to its original state. The change in state of tamper switch 120 drives counter 124 to increment the count value by one.

In one embodiment, counter 124 increments the tamper count value by one each time tamper switch 120 switches to the closed state position. In other words, the counter 124 increments the tamper count value only during a locking event (i.e., when the tamper loop is closed and the bolt member 110 is locked with the housing 116), and ignores the unlocking event because it will be between the two locking events and can be detected at the time of scanning. Thus, with the same amount of counter memory, the number of lock/unlock events that can be counted by the counter 124 is doubled. Referring to the embodiment of fig. 3, the reader 304 is communicatively coupled to a server 306. Each reader 304 is associated with a unique account Identifier (ID). The reader 304 is configured to transmit the identification code, the status of the tamper loop at the time of scanning, the count value, and the unique account ID to the server 306 when the tamper seal 100 is scanned. In this configuration, the seal 100 may be used as a reusable seal, where each event is stored on a block chain or server 306. For example, a first user locks the seal 100. This increases the count value by 1. He then scans the seal 100 with the secure access account (account ID) to verify the transaction. At this stage, the identification code, the status of the tamper loop at the time of scanning, the count value, and the unique account ID are transmitted to the server 306. At the reader end, the expected count value is 1. Upon receipt, the receiver scans the seal 100 and checks the count value. If the checked count value matches the count value stored in server 306, then the seal 100 is declared untampered. The scan records his account ID, identification code, status of the tamper loop, and count value on the server 306. For the next use, he simply locks the seal 100 again, increasing the count to 2. Upon receipt, the seal 100 is declared tampered with if the next user sees an open label status or if the count is 3.

In one exemplary embodiment, referring to table 1 below, by default, the tamper loop is open and the count value of counter 124 is set to 0. The manufacturer tests the seal 100 by closing the tamper loop. At this stage, the count value is increased to 1. After a successful test, the loop is opened here and the count is increased to 2. In this case, the tamper seal 100 is supplied to the end user.

For the end user, only one lock attempt is allowed. Once locked, the tamper loop is closed again and the count becomes 3. This is the only condition that the seal 100 returned to the reader 304 is declared non-tampered.

TABLE 1

In the event of any prior or subsequent tampering attempt, it is not possible to bypass the counter 124. If the seal 100 is tampered with by opening the tamper loop, the counter 124 immediately becomes 4. If the tamper loop is successfully reattached, the counter 124 is incremented to 5. When this is detected by the reader 304 at the customer, the seal 100 is declared tampered with.

In one embodiment, the identification code facilitates automatic identification of the container or transport carrier (302) to which the seal 100 is attached. The reader 304 is configured to read the unique identification code and cooperate with the server 306 to allow automatic identification of any container or transport carrier (302) to which the seal 100 is attached.

In the event that the reader 304 is unable to correctly read the unique identification code, the seal 100 is assumed to have been tampered with.

In one embodiment, the state of the tamper flag register facilitates determining whether the seal 100 has been tampered with. In another embodiment, the status bit of the identification code facilitates determining whether the seal 100 has been tampered with.

Advantageously, the control unit 118 is configured to generate an open event signal when the battery 108 is removed without opening the tamper loop (i.e., without unlocking the bolt member 110 from the housing 116). For example, if an attempt is made to remove the battery 108 without opening the tamper loop (i.e., without removing the bolt member 110 from the housing 116), there will be a loss of power to the tamper loop, and subsequently a loss of power to the control unit 118. In this case, the capacitor 104 provides sufficient power to the control unit 118 to facilitate generation of the opening event signal. At the moment the battery 108 is disconnected, the tamper switch 120 changes its state upon receiving an open event signal, thereby incrementing the count value of the counter 124 and changing the state of the tamper flag register or the status bit of the identification code.

Tamper indicating seal 100 facilitates identification of a tamper event even when seal 100 is opened without damaging it or when seal 100 is opened in the absence of a Radio Frequency (RF) field. Thus, even if the seal 100 is tampered with by a skilled counterfeiter, tamper detection is ensured.

The foregoing description of the embodiments has been provided for the purpose of illustration and is not intended to limit the scope of the present disclosure. Individual components of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Technical progress

The present disclosure described above has some technical advantages, including but not limited to, implementing a tamper-indicating seal that:

the number of times it opens and closes can be counted;

tamper-evident, even if the seal is not damaged/broken;

tamper-identification, even if the seal is opened in the absence of a Radio Frequency (RF) field;

identify a case where the seal has not been locked; and

a seal that can be deployed to be reusable.

The embodiments herein and the various features and advantageous details thereof are explained with reference to non-limiting embodiments in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, these examples should not be construed as limiting the scope of the embodiments herein.

The foregoing description of the specific embodiments so fully reveals the general nature of the embodiments herein: various applications of such specific embodiments may be readily modified and/or adapted by others through the application of current knowledge without departing from the general concept; and therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Thus, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments described herein.

The use of the expression "at least" or "at least one" indicates the use of one or more elements or components or quantities, which may be used in embodiments of the present disclosure to achieve one or more of the desired goals or outcomes.

The numerical values set forth for various physical parameters, dimensions, or quantities are only approximations, and it is contemplated that values higher/lower than the numerical values assigned to the parameters, dimensions, or quantities fall within the scope of the disclosure unless specifically stated to the contrary in the specification.

While considerable emphasis has been placed herein on the components and parts of the preferred embodiments, it will be appreciated that many embodiments can be made and that many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other variations of the preferred and other embodiments of the present disclosure will be apparent to those skilled in the art based upon the disclosure herein, from which it is to be clearly understood that the foregoing descriptive matter is to be interpreted merely as illustrative of the present disclosure and not as a limitation.