阅读说明：本技术 测量接收机的rc/cr相位误差校准方法及装置 (RC/CR phase error calibration method and device of measuring receiver ) 是由 程振国 秋旭亚 于 2019-07-18 设计创作，主要内容包括：提供一种电路,所述电路包括RC-CR电路和第二电路。所述RC-CR电路通过RC路径在第一输出节点处输出第一信号,通过CR路径在第二输出节点处输出第二信号。所述第二电路通过所述RC路径在所述第一输出节点处与所述RC-CR电路耦合。所述第二电路包括并联耦合的电容器阵列以及多个开关,所述电容器阵列中的每一个电容器与所述多个开关中的对应开关串联连接。所述电容器阵列中的每一个电容器及其对应的开关耦合在所述第一输出节点与接地之间。所述多个开关被接通或断开,使得所述第一信号与所述第二信号的相位差处于预定相位范围内。(A circuit is provided that includes an RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node through an RC path and a second signal at a second output node through a CR path. The second circuit is coupled to the RC-CR circuit at the first output node through the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, each capacitor in the array of capacitors connected in series with a corresponding switch in the plurality of switches. Each capacitor of the capacitor array and its corresponding switch are coupled between the first output node and ground. The plurality of switches are turned on or off so that a phase difference of the first signal and the second signal is within a predetermined phase range.)

1. A circuit, comprising:

an RC-CR circuit to phase shift an input signal received at an input node of the RC-CR circuit, wherein the RC-CR circuit has a first output node that outputs a first output signal through a first output path, and a second output node that outputs a second output signal through a second output path;

a first circuit coupled with the RC-CR circuit at the first output node through the first output path, wherein the first circuit includes an array of capacitors coupled in parallel and a plurality of switches, a first terminal of each capacitor in the array of capacitors coupled with the first output node of the RC-CR circuit, a second terminal of each capacitor in the array of capacitors coupled with a ground of the circuit through a corresponding switch in the plurality of switches, wherein each switch in the plurality of switches is controllably turned on or off such that a phase difference of the first output signal and the second output signal of the RC-CR circuit is within a predetermined phase range.

2. The circuit of claim 1, wherein the capacitance of each capacitor in the capacitor array is equal to the same capacitance value weighted by a predetermined weighting factor.

3. The circuit of any of claims 1-2, wherein the RC-CR circuit further comprises:

a first resistor having a first terminal coupled in series with the ground of the circuit through a first capacitor and a second terminal coupled with the input node of the RC-CR circuit, wherein a common node of the first resistor and the first capacitor is coupled with the first output node of the RC-CR circuit;

a second capacitor having a first terminal coupled in series with the ground of the circuit through a second resistor, and a second terminal coupled with the input node of the RC-CR circuit, wherein a common node of the second resistor and the second capacitor is coupled with the second output node of the RC-CR circuit;

wherein each of the first and second resistors has a fixed resistance and each of the first and second capacitors has a fixed capacitance.

4. The circuit of any of claims 1-3, wherein the first capacitor and the second capacitor in the RC-CR circuit have the same capacitance.

5. The circuit of any of claims 1-4, wherein the first capacitor and the second capacitor in the RC-CR circuit have different capacitances.

6. The circuit of any of claims 1-5, wherein a capacitance of one capacitor of the capacitor array is a predetermined fraction of a capacitance of the first capacitor or the second capacitor in the RC-CR circuit.

7. The circuit of any of claims 1-6, wherein the predetermined fraction is 5%, 10%, or 20%.

8. The circuit of any of claims 1-7, wherein the capacitance of the first capacitor is a fraction of the capacitance of the second capacitor.

9. The circuit of any one of claims 1 to 8, wherein the capacitance of one capacitor in the capacitor array is the same as the capacitance of the first capacitor in the RC-CR circuit.

10. The circuit of any of claims 1-9, wherein the capacitor array comprises n capacitors, and wherein the capacitance of the ith capacitor of the n capacitors is (2)^i–1Cs), where i is 1, 2, … …, n is a capacitance value, and n and i are each integers greater than 0.

11. The circuit of any one of claims 1 to 10, further comprising:

a first buffer coupled with the first output node of the RC-CR circuit, the first buffer receiving the first output signal;

a second buffer coupled with the second output node of the RC-CR circuit, the second buffer receiving the second output signal;

a mixer to receive output signals from the first buffer and the second buffer.

12. The circuit of any of claims 1-11, wherein the plurality of switches comprise n-channel metal-oxide-semiconductor (NMOS) field effect transistor switches.

13. The circuit of any of claims 1-12, wherein the frequency of the input signal to the RC-CR circuit is in the range of 660MHz to 6 GHz.

14. A mobile device, comprising:

a first circuit to phase shift an input signal received at an input node of the first circuit, wherein the first circuit has a first output node that outputs a first output signal through a first output path and a second output node that outputs a second output signal through a second output path;

a second circuit coupled with the first circuit at the first output node through the first output path, wherein the second circuit comprises an array of capacitors coupled in parallel and a plurality of switches, each capacitor in the array of capacitors connected in series with a corresponding switch in the plurality of switches, and each capacitor in the array of capacitors and its corresponding switch coupled between the first output node of the first circuit and ground, wherein each switch in the plurality of switches is controllably turned on or off such that a phase difference of the first output signal and the second output signal of the first circuit is within a predetermined phase range.

15. The mobile device of claim 14, wherein the first circuit further comprises:

a first resistor connected in series with a first capacitor, the first resistor and the first capacitor coupled between the input node of the first circuit and the ground, wherein a common node of the first resistor and the first capacitor is coupled with the first output node of the first circuit;

a second capacitor connected in series with a second resistor, the second capacitor and the second resistor coupled between the input node of the first circuit and the ground, wherein a common node of the second resistor and the second capacitor is coupled with the second output node of the first circuit;

wherein each of the first and second resistors has a fixed resistance and each of the first and second capacitors has a fixed capacitance.

16. The mobile device of any of claims 14 to 15, wherein a capacitance of one capacitor of the capacitor array is a predetermined fraction of a capacitance of the first capacitor or the second capacitor in the first circuit.

17. The mobile device according to any of claims 14 to 16, wherein the predetermined fraction is 5%, 10% or 20%.

18. The mobile device of any of claims 14 to 17, wherein the capacitor array comprises n capacitors, and wherein the capacitance of the ith capacitor of the n capacitors is (2)^i–1Cs), where i is 1, 2, … …, n is a capacitance value, and n and i are each integers greater than 0.

19. The mobile device according to any of claims 14 to 18, wherein the capacitance of each capacitor of the capacitor array is equal to the same capacitance value weighted by a predetermined weighting factor.

20. A method, comprising:

determining a phase difference between a first signal and a second signal output by an RC-CR circuit, wherein the RC-CR circuit is configured to: phase shifting an input signal of the RC-CR circuit; outputting the first signal at a first output node of the RC-CR circuit; outputting the second signal at a second output node of the RC-CR circuit;

turning on or off one or more switches of a plurality of switches in a circuit connected with the RC-CR circuit such that the phase difference is within a predetermined phase range, the circuit connected with the RC-CR circuit at the first output node of the RC-CR circuit and including a plurality of capacitors and a plurality of switches, wherein the plurality of capacitors are coupled in parallel, each capacitor of the plurality of capacitors is coupled in series with a corresponding switch of the plurality of switches, and each capacitor of the plurality of capacitors and its corresponding switch are coupled between the first output node of the RC-CR circuit and ground.

Technical Field

The present disclosure relates generally to wireless communications, and in particular embodiments to techniques and mechanisms for RC/CR phase error calibration for measurement receivers.

Background

Measurement receivers have been widely used to measure characteristics of radio signals, and the measured characteristics can be used in calibration and processing methods of radio signals in wireless communication systems.

Disclosure of Invention

Technical advantages are generally achieved by embodiments of the present invention, which describe methods and apparatus for RC/CR phase error calibration for a measurement receiver.

According to an aspect of the invention, there is provided a circuit comprising: an RC-CR circuit to phase shift an input signal received at an input node of the RC-CR circuit, wherein the RC-CR circuit has a first output node that outputs a first output signal through a first output path, and a second output node that outputs a second output signal through a second output path; a first circuit coupled with the RC-CR circuit at the first output node through the first output path, wherein the first circuit includes an array of capacitors coupled in parallel and a plurality of switches, a first terminal of each capacitor in the array of capacitors coupled with the first output node of the RC-CR circuit, a second terminal of each capacitor in the array of capacitors coupled with a ground of the circuit through a corresponding switch in the plurality of switches, wherein each switch in the plurality of switches is controllably turned on or off such that a phase difference of the first output signal and the second output signal of the RC-CR circuit is within a predetermined phase range.

Optionally, in any one of the above aspects, the capacitance of each capacitor in the capacitor array is equal to the same capacitance value weighted by a predetermined weighting factor.

Optionally, in any one of the above aspects, the RC-CR circuit further comprises: a first resistor having a first terminal coupled in series with the ground of the circuit through a first capacitor and a second terminal coupled with the input node of the RC-CR circuit, wherein a common node of the first resistor and the first capacitor is coupled with the first output node of the RC-CR circuit; a second capacitor having a first terminal coupled in series with the ground of the circuit through a second resistor, and a second terminal coupled with the input node of the RC-CR circuit, wherein a common node of the second resistor and the second capacitor is coupled with the second output node of the RC-CR circuit; wherein each of the first and second resistors has a fixed resistance and each of the first and second capacitors has a fixed capacitance.

Optionally, in any one of the above aspects, the first capacitor and the second capacitor in the RC-CR circuit have the same capacitance.

Optionally, in any of the above aspects, the first capacitor and the second capacitor in the RC-CR circuit have different capacitances.

Optionally, in any of the above aspects, a capacitance of one capacitor of the capacitor array is a predetermined fraction of a capacitance of the first capacitor or the second capacitor in the RC-CR circuit.

Optionally, in any of the above aspects, the predetermined fraction is 5%, 10%, or 20%.

Optionally, in any of the above aspects, the capacitance of the first capacitor is a fraction of the capacitance of the second capacitor.

Optionally, in any of the above aspects, a capacitance of one capacitor in the capacitor array is the same as a capacitance of the first capacitor in the RC-CR circuit.

Optionally, in any one of the above aspects, the capacitor array includes n capacitors, and a capacitance of an i-th capacitor of the n capacitors is (2 i-1 × Cs), where i ═ 1, 2, … …, n, Cs are capacitance values, and n and i are integers greater than 0, respectively.

Optionally, in any one of the above aspects, the circuit further comprises: a first buffer coupled with the first output node of the RC-CR circuit, the first buffer receiving the first output signal; a second buffer coupled with the second output node of the RC-CR circuit, the second buffer receiving the second output signal; a mixer to receive output signals from the first buffer and the second buffer.

Optionally, in any of the above aspects, the plurality of switches comprises n-channel metal-oxide-semiconductor (NMOS) field effect transistor switches.

Optionally, in any of the above aspects, the input signal of the RC-CR circuit has a frequency in a range of 660MHz to 6 GHz.

According to another aspect of the present invention, there is provided a mobile device including: a first circuit to phase shift an input signal received at an input node of the first circuit, wherein the first circuit has a first output node that outputs a first output signal through a first output path and a second output node that outputs a second output signal through a second output path; a second circuit coupled with the first circuit at the first output node through the first output path, wherein the second circuit comprises an array of capacitors coupled in parallel and a plurality of switches, each capacitor in the array of capacitors connected in series with a corresponding switch in the plurality of switches, and each capacitor in the array of capacitors and its corresponding switch coupled between the first output node of the first circuit and ground, wherein each switch in the plurality of switches is controllably turned on or off such that a phase difference of the first output signal and the second output signal of the first circuit is within a predetermined phase range.

Optionally, in any one of the above aspects, the first circuit further comprises: a first resistor connected in series with a first capacitor, the first resistor and the first capacitor coupled between the input node of the first circuit and the ground, wherein a common node of the first resistor and the first capacitor is coupled with the first output node of the first circuit; a second capacitor connected in series with a second resistor, the second capacitor and the second resistor coupled between the input node of the first circuit and the ground, wherein a common node of the second resistor and the second capacitor is coupled with the second output node of the first circuit; wherein each of the first and second resistors has a fixed resistance and each of the first and second capacitors has a fixed capacitance.

Optionally, in any of the above aspects, a capacitance of one capacitor of the capacitor array is a predetermined fraction of a capacitance of the first capacitor or the second capacitor in the first circuit.

Optionally, in any of the above aspects, the predetermined fraction is 5%, 10%, or 20%.

Optionally, in any one of the above aspects, the capacitor array includes n capacitors, and a capacitance of an i-th capacitor of the n capacitors is (2 i-1 × Cs), where i ═ 1, 2, … …, n, Cs are capacitance values, and n and i are integers greater than 0, respectively.

Optionally, in any one of the above aspects, the capacitance of each capacitor in the capacitor array is equal to the same capacitance value weighted by a predetermined weighting factor.

According to another aspect of the present invention, there is provided a method comprising: determining a phase difference between a first signal and a second signal output by an RC-CR circuit, wherein the RC-CR circuit is configured to: phase shifting an input signal of the RC-CR circuit, the first signal being output at a first output node of the RC-CR circuit, the second signal being output at a second output node of the RC-CR circuit; turning on or off one or more switches of a plurality of switches in a circuit connected with the RC-CR circuit such that the phase difference is within a predetermined phase range, the circuit connected with the RC-CR circuit at the first output node of the RC-CR circuit and including a plurality of capacitors and a plurality of switches, wherein the plurality of capacitors are coupled in parallel, each capacitor of the plurality of capacitors is coupled in series with a corresponding switch of the plurality of switches, and each capacitor of the plurality of capacitors and its corresponding switch are coupled between the first output node of the RC-CR circuit and ground.

Drawings

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 shows a diagram of an embodiment wireless communication system;

FIG. 2 shows a diagram of an embodiment measurement receiver;

FIG. 3 shows a diagram of an RC-CR circuit;

fig. 4 shows a diagram of an RC-CR circuit;

FIG. 5 shows a diagram of an embodiment circuit including an RC-CR circuit;

FIG. 6 shows a diagram of another embodiment circuit including an RC-CR circuit;

FIG. 7 shows a diagram of yet another embodiment circuit including an RC-CR circuit;

FIG. 8 shows a diagram of a further embodiment circuit including an RC-CR circuit;

FIG. 9 shows a flow diagram of an embodiment method for RC/CR phase error calibration;

FIG. 10 shows a diagram of an embodiment wireless communication network;

FIG. 11 shows a diagram of an embodiment processing system;

FIG. 12 is a diagram of an embodiment transceiver;

corresponding numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

Detailed Description

The making and using of embodiments of the present invention are described in detail below. It should be understood, however, that the concepts disclosed herein may be embodied in a wide variety of specific contexts, and that the specific embodiments described herein are merely illustrative and do not limit the scope of the claims. In addition, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

The RC-CR circuit outputs a first signal at a first output node and a second signal at a second output node. The phase difference of the first signal and the second signal is equal to a predetermined phase, e.g. 90 °, or within a predetermined phase range. However, in many cases, the phase difference may deviate from the predetermined phase or exceed the predetermined phase range, for example, due to load impedance mismatch, layout, and the like.

Embodiments of the present invention provide a circuit for adjusting or calibrating a phase difference so that the phase difference has a desired value. According to one embodiment, the circuit includes an RC-CR circuit and a calibration circuit. The RC-CR circuit outputs a first signal at a first output node through an RC path and a second signal at a second output node through a CR path. The calibration circuit is coupled to the RC-CR circuit at a first output node through an RC path. The calibration circuit includes an array of capacitors and a plurality of switches, each capacitor in the array of capacitors connected in series with a corresponding switch in the plurality of switches. Each capacitor of the capacitor array and its corresponding switch are coupled between the first output node and ground. Each of the plurality of switches is turned on or off such that a phase difference of the first signal and the second signal is within a predetermined phase range. The circuit may be used in a measurement receiver to make signal measurements.

Measurement receivers are known for measuring characteristics of radio signals, such as signal strength and quality, including leakage, image and linearity. Typically, the characteristic measurements may be used to perform a calibration, for example, a calibration in a factory, a laboratory calibration, or a real-time calibration of the wireless signal of the wireless communication system or the processing method employed by the wireless communication system. For example, the measurement receiver may be used to perform factory transmitter automatic power control (Tx APC) calibration, factory transmitter/measurement receiver (Tx/MRx) local oscillator leakage and Frequency Dependent (FD) I/Q image calibration, factory Tx counter 3 order intermodulation product (Tx 8 phase CIM3) calibration, real-time mode transmit power detection for highest output power (e.g., power delivered from the power amplifier to the antenna), real-time digital pre-distortion (DPD) for highest output power, real-time mode antenna tuning for highest output power, and real-time FD I/Q image calibration.

In one example, the measurement receiver may be used for factory or real-time mode FD I/Q image calibration of signals sent through the in-phase (I) and quadrature (Q) paths of the transmitter. I/Q transmitters typically suffer from image distortion due to gain and phase imbalance between the I and Q paths. The imbalance may be measured using a measurement receiver and the image distortion may then be corrected based on the measurement.

Fig. 1 shows a diagram of an embodiment communication system 100. Communication system 100 includes a transmitter (Tx)102, a first correction unit 104, a measurement receiver (MRx)106, a second correction unit 108, a frequency dependent I/Q mismatch estimation (FD-IQME) unit 110, a coupler 112, an antenna 114 and a Power Amplifier (PA) 116. The transmitter 102 may be a linear I/Q transmitter. The first correction unit 104 receives the baseband signal through I/Q paths, i.e., I1 and Q1, and receives the correction signal from the FD-IQME unit 110. For example, the first correction unit 104 may remove frequency-dependent image distortion of a signal output from the transmitter 102 or the PA 116. Then, the first correction unit 104 outputs corrected I/Q path signals, i.e., I2, Q2. The first correction unit 104 may include a baseband digital processor, for example, an Application Specific Integrated Circuit (ASIC) or a field-programmable gate array (FPGA), which may digitally implement the Tx frequency-dependent image correction. The transmitter 102 receives and processes the I2 and Q2 and generates a transmit signal S0 suitable for transmission. The PA 116 receives the signal S0 and outputs a signal S1 transmitted through the antenna 114. The transmit signal S1 is also fed into MRx 106 through coupler 112. The signal S0 may also be fed directly into MRx 106 (not shown) for measurement. MRx 106 measures the transmit signal S0/S1 and outputs signals I3 and Q3 through the I/Q path. The second correction unit 108 receives I3 and Q3, and performs distortion correction on I3 and Q3 according to a control signal from the FD-IQME 110. Signal distortion of I3 and Q3 may be caused by the transmitter 102. The second correction unit 108 outputs I4 and Q4 and feeds them into the FD-IQME 110. The second correction unit 108 may comprise a baseband digital processor (e.g., ASIC or FPGA) that may digitally implement MRx frequency dependent image correction. The FD-IQME 110 receives I1, Q1, and I4, Q4, estimates signal distortion of signals output from the transmitter 102 and/or PA 116 according to I4, Q4, and outputs control signals for the first correction unit 104 and the second correction unit 108 to perform distortion correction accordingly. The FD-IQME 110 may comprise a baseband digital processor (e.g., ASIC or FPGA, or even firmware) that may implement frequency-dependent I/Q mismatch estimation to generate Tx and MRx frequency-dependent correction signals.

FIG. 2 shows a diagram of an embodiment circuit 200 of MRx. The circuit 200 may be used in the MRx 106 of the communication system 100 shown in fig. 1. The circuit 200 includes a Radio Frequency (RF) attenuator 202, a Low Noise Amplifier (LNA) 204, an RC-CR circuit 206, RF buffers 208, 210, a mixer 212, an Intermediate Frequency (IF) Variable Gain Amplifier (VGA) 214, and an IF filter 216. The RF attenuator 202 attenuates the received RF signal and feeds an output signal to the LNA 204. The LNA 204 receives and amplifies the output signal from the RF attenuator 202, thereby generating an amplified signal. In one example, where the received RF signal is of a high strength, the received RF signal may be attenuated by RF attenuator 202 and fed into RC-CR circuit 206, thereby bypassing LNA 204. In another example, where the received RF signal is of a lesser strength, the received RF signal may be fed to the LNA 204 for amplification, thereby bypassing the RF attenuator 202. The RC-CR circuit 206 receives and phase shifts the amplified signal and outputs a first signal on the RC path and a second signal on the CR path. The two signals (i.e., the first signal and the second signal) have a phase shift of a predefined value. The two signals are passed to RF buffers 208, 210, respectively, and then to mixer 212. The mixer 212 may output a signal having an intermediate frequency for subsequent processing. For example, as shown, the signal output by mixer 212 may be amplified by an IF VGA 214 and filtered by an IF filter 216 to produce a filtered IF signal.

The RC-CR circuit 206 may also be referred to as a phase shift circuit or RC-CR network. The RC-CR circuit is used to phase shift an input signal and to generate two output signals that are out of phase by a designed phase value. In this example, the RC-CR circuit 206 is configured such that the phase difference of the two output signals is equal to 90 degrees. However, due to process variations, load impedance (e.g., caused by load and parasitic effects), the phase difference may not be exactly equal to the predefined phase. For example, the phase difference may be within a phase range of the predefined phase, i.e., { P- Δ, P + Δ }, where P represents the predefined phase, e.g., 90 °, and Δ represents the maximum phase error of the allowed phase difference. For example, the phase difference may be in the phase range of {90 ° -0.5 °,90 ° -0.5 ° } or {90 ° -0.03 °,90 ° +0.03 ° }. Generally, the closer the phase difference is to the predefined phase, the higher the RC-CR phase accuracy of the RC-CR circuit. In one example, an RC-CR circuit may be considered to produce an acceptable or accurate RC-CR phase shift when its phase difference is within a predefined phase range. However, when the phase difference of the RC-CR circuit exceeds a predefined phase range, an RC-CR phase error may occur. The RC/CR phase accuracy of MRx can affect the performance of MRx in factory or real-time mode FD I/Q image calibration of cellular transmitters, etc.

Fig. 3 shows a diagram of an RC-CR circuit 300. The RC-CR circuit 300 is a conventional RC-CR circuit that phase shifts an input signal to produce two output signals that are 90 ° out of phase. The RC-CR circuit 300 includes an RC circuit 310 and a CR circuit 320. RC circuit 310 includes a resistor 312 and a capacitor 314. Resistor 312 and capacitor 314 are connected in series and coupled between an input node 332 of RC-CR circuit 330 and ground 334. The CR circuit 320 includes a resistor 322 and a capacitor 324. Resistor 322 is connected in series with capacitor 324 and is coupled between input node 332 and ground 334. The common node of the resistor 312 and the capacitor 314 is coupled to a first output node 336 of the RC-CR circuit 300. The first output node 336 may be referred to as an output node on the RC path of the RC-CR circuit 300. The common node of the resistor 322 and the capacitor 324 is coupled to a second output node 338 of the RC-CR circuit 300. The second output node 338 may also be referred to as an output node on the CR path of the RC-CR circuit 300. The resistor 312 and the capacitor 314 in the RC circuit 310 may be referred to as an RC path resistor and an RC path capacitor, respectively, and the resistor 322 and the capacitor 324 in the CR circuit 320 may be referred to as a CR path resistor and a CR path capacitor, respectively. The RC-CR circuit 300 receives an input signal at an input node 332, outputs a first signal at a first output node 336, and outputs a second signal at a second output node 338. The resistors 312, 322 and the capacitors 314, 324 are designed to have values such that the phase difference of the two signals (i.e., the first signal and the second signal) is equal to 90 degrees.

Fig. 4 shows a diagram of an RC-CR circuit 400. Fig. 4 shows an equivalent RC-CR circuit taking into account circuit loading and parasitic effects. As shown, the RC-CR circuit 400 includes a circuit 401 similar to the RC-CR circuit 300. Circuit 401 includes resistors 402, 406 and capacitors 404, 408. A resistor 402 (i.e., an RC path resistor) and a capacitor 404 (i.e., an RC path capacitor) are connected in series and coupled between an input node 410 of the RC-CR circuit 400 and a ground 412. A resistor 406 (i.e., a CR path resistor) and a capacitor 408 (i.e., a CR path capacitor) are connected in series and coupled between an input node 410 of the RC-CR circuit 400 and a ground 412. The common node of resistor 402 and capacitor 404 is connected on an RC path to a first output node 414, and the common node of resistor 406 and capacitor 408 is connected on a CR path to a second output node 416. The RC-CR circuit 400 generates two output signals at a first output node 414 and a second output node 416, respectively, that are out of phase by a predefined phase.

The RC-CR circuit 400 also includes resistors 418, 422 and capacitors 420, 424. Resistor 418 and capacitor 420 are connected in parallel and coupled between first output node 414 and ground 412. Resistor 422 and capacitor 424 are connected in parallel and coupled between second output node 416 and ground 412. Resistors 418, 422 and capacitors 420, 424 represent the load and parasitic impedance on the RC and CR paths, respectively.

In one example, resistors 402, 406 may have the same resistance, e.g., represented by R, capacitors 404, 408 may have the same capacitance, e.g., represented by C, and circuit 401 is designed to produce two output signals that are 90 ° out of phase. In this case, when the resistors 418, 422 have the same resistance Rp and the capacitors 420, 424 have the same capacitance Cp, the two output signals at the first output node 414 and the second output node 416 may have the phase θ_RCAnd theta_CRRespectively expressed as:

that is, the phase difference of the two output signals is equal to 90 °. This means that when the load impedances on the RC and CR paths are matched (i.e., the same), the RC-CR circuit 400 receives an input signal at the input node 410 and outputs two signals that are 90 ° out of phase. The phase of the output signal at the first output node 414 may be referred to as the RC phase and the phase of the output signal at the second output node 416 may be referred to as the CR phase. Therefore, the RC-CR phase difference is 90 deg..

However, in practice, the load impedances on the RC and CR networks and the RC and CR paths typically do not match each other, which results in the RC-CR phase difference of the output signal deviating from the predefined 90 ° (thereby resulting in an RC-CR phase error or deviation), the RC-CR phase accuracy being reduced. Therefore, the low RC-CR phase accuracy results in reduced MRx measurement and calibration performance. The RC-CR network and the mismatch in load impedance between the RC path and the CR path of the RC-CR network may be caused by various factors, such as process variations of the circuit (e.g., the circuit to which the RC-CR circuit is connected for signal processing), and/or circuit placement involving uncontrolled placement behavior, such as routing, coupling, spacing, positioning, and the like. Designing a near constant phase difference over a wide frequency range covering multiple frequency bands (e.g., 600MHz to 6GHz), especially for high frequencies (e.g., 6GHz), is a challenging task.

Various methods and mechanisms have been proposed and utilized to improve the RC-CR phase accuracy of RC-CR circuits, for example, by reducing impedance and/or capacitance mismatch between the RC path and the CR path. Fig. 5 shows a diagram of a circuit 500. Circuit 500 includes LNA 502, RC-CR circuit 504, RF buffers 506, 508, and mixer 510. The LNA amplifies the receive signal and feeds into the RC-CR circuit 504. The RC-CR circuit 504 generates two output signals that are out of phase by a predefined value. The two output signals are then passed to RF buffers 506, 508, respectively, and to a mixer 510. The RC-CR circuit 504 is used to reduce the RC-CR phase error by adjusting the RC path and CR path capacitors. The RC-CR circuit 504 includes resistors 512, 514 and capacitors 516, 518. The resistor 512 and the capacitor 516 are connected in series and coupled between an input node 520 of the RC-CR circuit 504 and ground 522. Resistor 514 and capacitor 518 are connected in series and coupled between input node 520 and ground 522. The RC-path capacitor 516 and the CR-path capacitor 518 may each be adjusted to have different capacitances in order to reduce layout parasitic mismatch, thereby reducing capacitance mismatch between the RC-path and the CR-path.

Fig. 6 shows a diagram of a circuit 600. As shown, the circuit 600 includes an RC-CR circuit 601. RC-CR circuit 601 is used to reduce by adjusting RC path and CR path capacitancesSmall RC-CR phase error. As shown, RC-CR circuit 601 includes resistors 602, 606, a first capacitor array 604, and a second capacitor array 608. Resistor 602 and first capacitor array 604 are connected in series and coupled to receive input signal V_inBetween input node 610 and ground 612. The first capacitor array 604 is equivalent to the RC-path capacitor of the RC-CR circuit 601. Resistor 606 and second capacitor array 608 are connected in series and coupled between input node 610 and ground 612. The second capacitor array 608 is equivalent to the CR path capacitor of the RC-CR circuit 601. The first capacitor array 604 includes a plurality of capacitors connected in parallel. Each of the plurality of capacitors is coupled to ground 612 through a switch. The first capacitor array 604 may have different capacitances by turning the switches on or off. The second capacitor array 608 includes a plurality of branches connected in parallel. Each branch comprises two capacitors connected in series by a switch. The second capacitor array 608 may also have a different capacitance by turning these switches on or off. The common node of the resistor 602 and the first capacitor array 604 is connected on an RC path to an output node 614, and a first output signal is output from the output node 614. A common node of the resistor 606 and the second capacitor array 608 is connected to an output node 616 on the CR path, and a second output signal is output from the output node 616. The first and second signals are then fed into RF buffers 618, 620, respectively, and subsequently passed to an output signal V_outThe mixer 624. In this example, both the RC path capacitor (represented by first capacitor array 604) and the CR path capacitor (represented by second capacitor array 608) may be adjusted by switches in the first capacitor array 604 and the second capacitor array 608 to reduce parasitic mismatch between the RC path and the CR path.

Circuits 500 and 600 as shown in fig. 5 and 6 modify a conventional RC-CR circuit (as shown in fig. 3) by utilizing adjustable (rather than fixed) RC-path and CR-path capacitors and attempting to adjust the RC-path and CR-path capacitances to reduce processing and parasitic mismatch. This makes the capacitive matching between the RC path and the CR path relatively complex. Additionally, as described above, the second capacitor array 608 in the circuit 600 includes branches connected in parallel, each branch including two capacitors connected in series by a switch. Matching the CR path capacitance to the RC path capacitance is also complicated by the use of two capacitors connected in series through switches in each branch. Further, the drain and source of the switch in the first capacitor array 604 (i.e., on the RC path) are at different potentials than the drain and source of the switch in the second capacitor array 608 (i.e., on the CR path), and the potential difference between the switches on the RC path and the CR path may cause additional RC-CR phase error.

FIG. 7 shows a diagram of an embodiment circuit 700. The circuit 700 may be included in an MRx, such as MRx 106 shown in fig. 1. As shown, circuit 700 includes LNA 702, RC-CR circuit 704, RC-CR phase error calibration circuit 706, RF buffers 708, 710, and mixer 712. The LNA 702 amplifies the received signal and feeds the output signal into the RC-CR circuit 704. The RC-CR circuit 704 receives an input signal at the input node 730, phase shifts an output signal, and outputs a first signal on an RC path of the RC-CR circuit 704 and a second signal on a CR path of the RC-CR circuit 704. The two signals, i.e. the first signal and the second signal, have a predefined phase difference, e.g. 90 °. An RC-CR phase error calibration circuit 706 is coupled to the RC-CR circuit 704 along an RC path of the RC-CR circuit 704 for calibrating the RC-CR phase error of the RC-CR circuit 704. The two signals output by the RC-CR circuit 704 are passed to RF buffers 708 and 710 and fed into a mixer 712.

The RC-CR circuit 704 is similar to the RC-CR circuit 300 shown in FIG. 3. As shown, the RC-CR circuit 704 includes an RC circuit having a resistor 722 and a capacitor 724. The resistor 722 and the capacitor 724 are connected in series and are coupled between an input node 730 of the circuit 700 and ground 732. The RC-CR circuit 704 also includes a CR circuit having a resistor 726 and a capacitor 728. Resistor 726 is connected in series with capacitor 728 and is coupled between input node 730 and ground 732. The common node of the resistor 722 and the capacitor 724 is coupled to a first output node 734 of the RC-CR circuit 704. The common node of the resistor 726 and the capacitor 728 is coupled to a second output node 736 of the RC-CR circuit 704. Each of the resistors 722, 726 has a fixed resistance and each of the capacitors 724, 728 has a fixed capacitance. The RC-CR circuit 704 may be configured such that a phase difference of the first signal output at the first output node 734 and the second signal output at the second output node 736 is a predefined phase value. The resistors 722, 726 may have the same resistance. The capacitors 724, 728 may have the same or different capacitances. The circuit 700 or the RC-CR circuit 704 may be fabricated using a Fin-Effect Transistor (FinFET) fabrication technique (hereinafter referred to as "TSMC 16nm FinFET fabrication technique") of taiwan semiconductor manufacturing, ltd. The TSMC 16nm FinFET fabrication technology is one technique used by TSMC to produce chips.

The RC-CR phase error calibration circuit 706 is connected to the RC-CR circuit 704 at a first output node 734 on the RC path. The RC-CR phase error calibration circuit 706 includes a plurality of capacitors coupled in parallel, namely capacitors 742, 744, 746, 748. RC-CR phase error calibration circuit 706 also includes a plurality of switches, switches 752, 754, 756, 758. Capacitors 742, 744, 746, 748 are coupled to ground 732 through switches 752, 754, 756, 758, respectively. Each of the capacitors 742, 744, 746, 748 corresponds to a switch 752, 754, 756, or 758. A first terminal of each of the capacitors 742, 744, 746, 748 is connected to the first output node 734 of the RC-CR circuit 704 and a second terminal of each of the capacitors 742, 744, 746, 748 is connected to its corresponding switch, 752, 754, 756, 758. That is, each of the capacitors 742, 744, 746, 748 and its corresponding switch 752, 754, 756, 758 are coupled between the first output node 734 and the ground 732, respectively. The switches 752, 754, 756, 758 may be n-channel metal-oxide-semiconductor (NMOS) field effect transistor switches. By turning on or off the switches 752, 754, 756, 758, the RC-CR phase error calibration circuit 706 may load a different capacitance on the RC path of the RC-CR circuit 704, thus changing the capacitance on the RC path of the RC-CR circuit 704. Accordingly, the phase difference between the first and second signals output at the first output node 734 and the second output 736 may be adjusted. In this example, the RC path capacitance of the RC-CR circuit 704 is adjusted using the RC-CR phase error calibration circuit 706. The RC-CR phase error calibration circuit 706 calibrates the phase difference between the two signals output by the RC-CR circuit 704 such that the phase difference is equal to 90 ° or within a predefined phase range.

Although fig. 7 illustrates four capacitors included in the RC-CR phase error calibration circuit 706, one of ordinary skill in the art will recognize that any number of suitable capacitors may be included in the RC-CR phase error calibration circuit 706. For example, the RC-CR phase error calibration circuit 706 may include 3, 6, or 8 capacitors connected in parallel. In another example, the number of capacitors included in the RC-CR phase error calibration circuit 706 may be equal to 2ⁿWherein n is an integer greater than 1. For example, the RC-CR phase error calibration circuit 706 may include 2, 4, 8, 16, or 32 capacitors. Each capacitor corresponds to one switch and each capacitor is connected to ground through its corresponding switch. The number of capacitors included in the RC-CR phase error calibration circuit 706 may be determined according to RC-CR phase accuracy requirements.

Some or all of the capacitors 742, 744, 746, 748 may have the same capacitance or different capacitances. For example, capacitors 742, 744, 746 may have the same capacitance, which is different from the capacitance of capacitor 748. In another example, the capacitance of one of the capacitors 742, 744, 746, 748 may be equal to the capacitance of the capacitor 724. In yet another example, the capacitance of one of the capacitors 742, 744, 746, 748 may be equal to a fraction of the capacitance of the capacitor 724 or the capacitor 728. In one embodiment, the capacitances of capacitors 742, 744, 746, 748 may all be equal to a predefined value weighted by a weighting factor. For example, the capacitances of capacitors 742, 744, 746, 748 may be a, respectively₁*x、a₂*x、a₃X and a₄X, where x is a predefined capacitance value, a₁、a₂、a₃And a₄Is a weighting factor. In one example, the weighting factor a₁、a₂、a₃And a₄The values of (a) may be 1, 2, 3 and 4, respectively. In RC-CR phase error correctionIn case the quasi circuit 706 comprises n capacitors C1, … …, Ci, … …, Cn connected in parallel, the capacitance of the n capacitors may all be a_iX, where i ═ 1, 2, … …, n, x are predefined capacitance values. In one example, a_iMay have a value of 2^i–1. In another example, a_iMay have a value of 2^–(i–1). The n capacitors in the RC-CR phase error calibration circuit 706 each have a capacitance of 2^i–1Or 2^–(i–1)Where i is 1, 2, … …, n, the n capacitors may be referred to as a binary weighted capacitor array or a binary capacitor array.

The number of capacitors and/or the capacitance of the capacitors included in the RC-CR phase error calibration circuit 706 may be determined such that the capacitance on the RC path of the RC-CR circuit 704 may be adjusted, and thus, the phase difference between the first and second signals output at the first output node 734 and the second output 736 may be adjusted to be equal to a predefined phase value, such as 90 °, or within a predefined phase range, such as { P- Δ, P + Δ }, where P represents a predefined phase, such as 90 °, Δ represents a maximum phase error that allows for the phase difference. For example, the value of Δ may be 0.1 °, 0.05 °, 0.5 °,1 °, and the like. In one example, the minimum capacitance of the capacitors 742, 744, 746, 748 may be equal to a fraction of the capacitance of the capacitor 724 (i.e., the RC path capacitor of the RC-CR circuit 704). The score may be a predetermined value, such as 1/10, 1/20, 1/5, 1/30, and the like. The fraction, i.e. the minimum capacitance in the capacitor array, can thus be determined according to the resolution required for the phase error correction of the RC-CR circuit. The resolution of the phase error correction determines the minimum phase error that needs to be adjusted. The higher the resolution of the phase error correction, the smaller the fraction required may be.

The circuit 700 may also include a control circuit 760, the control circuit 760 outputting control signals to turn on and off one or more of the switches 752, 754, 756, 758. In one example, the control circuit 760 may output a four-bit control signal, each bit corresponding to one of the plurality of switches, thereby indicating whether to turn the corresponding switch on or off. For example, control circuit 760 may output 1001, which 1001 instructs switches 752 and 758 to be turned on and switches 754 and 756 to be turned off. In this case, bit 1 indicates on and bit 0 indicates off. N bits may be used to control N switches. Those of ordinary skill in the art will recognize many variations and alternatives for turning the switch on/off. The control circuit 760 may determine the control signal based on an input signal from a phase error estimation unit, such as FD-IQME 110 shown in fig. 1. The phase error estimation unit may be configured to receive the phases of the two output signals of the RC-CR circuit 704, determine a phase difference between the two output signals, and estimate a phase difference error. The phase error estimation unit may also be used to determine the phase difference needs and the extent to which it can be corrected and to generate a signal for switching the switch accordingly and send this signal to the control circuit 760. In one example, the signal may indicate a switch to be opened or closed.

FIG. 8 shows a diagram of another embodiment circuit 800. The circuit 800 may also be included in MRx. The circuit 800 includes an RC-CR circuit 802, an RC-CR phase error calibration circuit 804, RF buffers 806, 808, and a mixer 810. The RC-CR circuit 802 receives an input signal at an input node 812, phase shifts an output signal, and outputs a first signal on an RC path of the RC-CR circuit 802 and a second signal on a CR path of the RC-CR circuit 802. The RC-CR circuit 802 is designed such that the two signals (i.e., the first signal and the second signal) have a predefined phase difference, such as 90 °. An RC-CR phase error calibration circuit 804 is connected to the RC-CR circuit 802 on an RC path of the RC-CR circuit 802 for calibrating the RC-CR phase error of the RC-CR circuit 802 such that the phase difference between the two signals output by the RC-CR circuit 802 is equal to a predefined value or within a predefined phase range. The two signals output by the RC-CR circuit 802 are passed to RF buffers 806 and 808 and fed into a mixer 810.

The RC-CR circuit 802 is similar to the RC-CR circuit 300 shown in FIG. 3. As shown, the RC-CR circuit 802 includes a resistor 814 and a capacitor 816 connected in series and coupled between an input node 812 and a ground 822. The RC-CR circuit 802 also includes a resistor 818 and a capacitor 820 connected in series and coupled between the input node 812 and ground 822. The common node of the resistor 814 and the capacitor 816 is coupled to a first output node 824 of the RC-CR circuit 802. A common node of the resistor 818 and the capacitor 820 is coupled to a second output node 826 of the RC-CR circuit 802. Resistors 814, 818 each have a fixed resistance and capacitors 816, 820 each have a fixed capacitance. The circuit 800 and/or the RC-CR circuit 802 may be fabricated using TSMC 16nm FinFET fabrication techniques.

The RC-CR phase error calibration circuit 804 is connected to the RC-CR circuit 802 at a first output node 824 along an RC path. The RC-CR phase error calibration circuit 804 is used to adjust the capacitance on the RC path of the RC-CR circuit 802, thereby adjusting or calibrating the phase difference between the two signals output by the RC-CR circuit 802. The RC-CR phase error calibration circuit 804 includes a plurality of capacitors C0, C1, C2, C3, C4, and C5 coupled in parallel. Each of the capacitors C0, C1, C2, C3, C4, and C5 is coupled to ground 822 through a corresponding switch, i.e., switches D0, D1, D2, D3, D4, and D5. A first terminal of each of the capacitors C0, C1, C2, C3, C4, and C5 is connected to the first output node 824, and a second terminal of each of the capacitors C0, C1, C2, C3, C4, and C5 is connected to its corresponding switch, i.e., D0, D1, D2, D3, D4, and D5. The switches D0, D1, D2, D3, D4, and D5 may be n-channel metal-oxide-semiconductor (NMOS) field effect transistor switches. By turning on or off each of the switches D0, D1, D2, D3, D4, and D5, the RC-CR phase error calibration circuit 804 loads a different capacitance on the RC path, thus changing the capacitance on the RC path of the RC-CR circuit 802.

In one embodiment, the RC path resistance (resistor 814) may be matched in layout matching to the CR path resistance (resistor 818). For example, resistors 814 and 818 may have the same resistance, and the layout on the RC path and CR path also match each other. The capacitance of the capacitor 820 may be 4x, the capacitance of the capacitor 816 may be 3x, and the capacitance of the capacitor D0 may be x, where x represents a capacitance value. That is, the capacitances of capacitors 816 and 820 are both multiples of the capacitance of capacitor D0. The CR path capacitance (4 x for capacitor 820) may match the RC path capacitance (3 x for capacitor 816 + 1x for capacitor D0). The capacitance of each capacitor Ci (i ═ 0, 1, … …, 4) is 2^–ix. In one embodiment, switch D0 may be initially turned on to match the RC path capacitance to the CR path capacitance. When it is desired to correct for the RC-CR phase error, for example, where it is desired to adjust the phase difference between the two signals output at output nodes 824 and 826 by adding an RC path capacitance, one or more of switches D1-D4 may be turned on. E.g., turn on D4. In another example, D4 and D3 are turned on. In the event that it is desired to adjust the phase difference between the two signals being output by reducing the RC path capacitance, switch D0 may be turned off and one or more of switches D1-D4 may be turned on. In this example, when switch D0 is initially turned on to match the RC path capacitance to the CR path capacitance, switch D0 being "turned on" may load the RC-CR circuit 802 with resistance and parasitic capacitance, which may initially affect the RC-CR phase accuracy of the RC-CR circuit 802. The effects of load resistance and parasitic capacitance caused by the "on" switch D0 may be reduced using TSMC 16nm FinFET processing techniques.

As shown in fig. 7-8, embodiments of the present invention use an RC-CR phase error calibration circuit connected in the RC path of the RC-CR circuit to correct or calibrate the RC-CR phase error of the RC-CR circuit. The RC-CR phase error calibration circuit adjusts an RC-path capacitance of the RC-CR circuit to adjust a phase difference of signals output by the RC-CR circuit on the RC path and the CR path, respectively. These embodiments avoid adjusting the capacitors of the conventional RC-CR circuits, such as RC-CR circuits 704, 802, thereby keeping the conventional RC-CR circuits unchanged. The RC-CR phase error calibration circuit includes a switch having a source coupled to ground. Thus, smaller and simpler NMOS switches can be used, thereby simplifying the calibration circuit. Additionally, the calibration resolution may be configured by configuring the minimum capacitance in the capacitor in the RC-CR phase error calibration circuit. This allows for more accurate calibration of the RC-CR phase error. These embodiments may operate on signals having various frequencies, such as frequencies in the range of 660MHz to 6 GHz. The embodiments may be applied to various communication systems, such as 4G or 5G technology compatible communication systems.

Fig. 9 shows a flow diagram of an embodiment method 900. As shown, in step 902, the method 900 determines a phase difference between a first signal and a second signal output by an RC-CR circuit. The RC-CR circuit is to phase shift an input signal of the RC-CR circuit, output a first signal at a first output node of the RC-CR circuit, and output a second signal at a second output node of the RC-CR circuit. In step 904, the method 900 turns on or off one or more of a plurality of switches in a circuit connected to the RC-CR circuit according to the determined phase difference such that the phase difference is within a predetermined phase range. The circuit is connected to the RC-CR circuit at a first output node of the RC-CR circuit and includes a plurality of capacitors and a plurality of switches. A plurality of capacitors are coupled in parallel, each of the plurality of capacitors is coupled in series with a corresponding switch of the plurality of switches, and each of the plurality of capacitors and its corresponding switch are coupled between the first output node of the RC-CR circuit and ground.

Fig. 10 shows a network 1000 for transmitting data. The network 1000 includes a base station 1010 having a coverage area 1010, a plurality of mobile devices 1020, and a backhaul network 1030. As shown, base station 1010 establishes uplink (dashed lines) and/or downlink (dotted lines) connections with mobile device 1020, which are used to carry data from mobile device 1020 to base station 1010, and vice versa. The data carried over the uplink/downlink connections may include data communicated between the mobile devices 1020 as well as data communicated to and from remote locations (not shown) over the backhaul network 1030. As used herein, the term "base station" refers to any component (or collection of components) used to provide wireless access to a network, such as an enhanced base station (eNB), macrocell, femtocell, Wi-Fi Access Point (AP), or other wireless enabled device. The base station may provide wireless Access according to one or more wireless communication protocols, such as Long Term Evolution (LTE), LTE advanced (LTE-a), High Speed Packet Access (HSPA), Wi-Fi 802.11a/b/g/n/ac, and so on. As used herein, the term "mobile device" refers to any component (or collection of components) capable of establishing a wireless connection with a base station, such as a User Equipment (UE), a mobile Station (STA), and other wireless enabled devices. In some embodiments, network 1000 may include various other wireless devices, such as repeaters, low power nodes, and so forth. Embodiments of the present invention may be applied to mobile devices in communication with network 1000.

Fig. 11 illustrates a block diagram of an embodiment processing system 1100 for performing embodiments described herein, wherein the embodiment processing system 1100 may be installed in a host device. As shown, processing system 1100 includes a processor 1104, a memory 1106, and an interface 1110 and 1114, which may or may not be arranged as shown in FIG. 11. Processor 1104 may be any component or collection of components for performing computations and/or other processing related tasks, and memory 1106 may be any component or collection of components for storing programming and/or instructions for execution by processor 1104. In one embodiment, memory 1106 includes non-transitory computer-readable media. Interfaces 1110, 1112, 1114 may be any component or collection of components that enable processing system 1100 to communicate with other devices/components and/or a user. For example, one or more of interfaces 1110, 1112, 1114 may be used to transfer data, control, or management messages from processor 1104 to applications installed in the host device and/or remote devices. Also for example, one or more of interfaces 1110, 1112, 1114 may be used to enable a user or user device (e.g., a Personal Computer (PC), etc.) to interact/communicate with processing system 1100. Processing system 1100 may include additional components not shown in fig. 11, such as long-term memory (e.g., non-volatile memory, etc.).

In some embodiments, the processing system 1100 is included in a network device that accesses or otherwise forms part of a telecommunications network. In one example, the processing system 1100 is located in a network-side device in a wireless or wireline telecommunications network, such as a base station, relay station, scheduler, controller, gateway, router, application server, or any other device in a telecommunications network. In other embodiments, the processing system 1100 is located in a user-side device accessing a wireless or wired telecommunications network, such as a mobile station, a User Equipment (UE), a Personal Computer (PC), a tablet, a wearable communication device (e.g., a smart watch, etc.), or any other device for accessing a telecommunications network.

In some embodiments, one or more of the interfaces 1110, 1112, 1114 connect the processing system 1100 to a transceiver for sending and receiving signaling over a telecommunications network. Fig. 12 shows a block diagram of a transceiver 1200 for sending and receiving signaling over a telecommunications network. The transceiver 1200 may be installed in a host device. As shown, the transceiver 1200 includes a network-side interface 1202, a coupler 1204, a transmitter 1206, a receiver 1208, a signal processor 1210, and a device-side interface 1212. The network-side interface 1202 may include any component or collection of components for sending or receiving signaling over a wireless or wireline telecommunications network. The coupler 1204 may include any component or collection of components for facilitating bi-directional communication over the network-side interface 1202. The transmitter 1206 may include any component or collection of components (e.g., an upconverter, power amplifier, etc.) for converting a baseband signal to a modulated carrier signal suitable for transmission over the network-side interface 1202. Receiver 1208 may include any component or collection of components (e.g., a downconverter, a low noise amplifier, etc.) for converting a carrier signal received over network-side interface 1202 to a baseband signal. The signal processor 1210 may include any component or collection of components for converting baseband signals to or from data signals suitable for communication over the one or more device-side interfaces 1212. One or more device-side interfaces 1212 may include any component or collection of components for communicating data signals between signal processor 1210 and components within a host device (e.g., processing system 1100, a Local Area Network (LAN) port, etc.).

The transceiver 1200 may send and receive signaling over any type of communication medium. In some embodiments, transceiver 1200 sends and receives signaling over a wireless medium. For example, transceiver 1200 may be a wireless transceiver for communicating according to a wireless telecommunication protocol, such as a cellular protocol (e.g., long-term evolution (LTE), etc.), a Wireless Local Area Network (WLAN) protocol (e.g., Wi-Fi, etc.), or any other type of wireless protocol (e.g., bluetooth, Near Field Communication (NFC), etc.). In these embodiments, the network-side interface 1202 includes one or more antenna/radiating elements. For example, the network-side interface 1202 may include a single antenna, a plurality of independent antennas, or a multi-antenna array for multi-layer communication, such as Single Input Multi Output (SIMO), Multiple Input Single Output (MISO), Multiple Input Multi Output (MIMO), and so on. In other embodiments, transceiver 1200 sends and receives signaling over a wired medium (e.g., twisted pair cable, coaxial cable, optical fiber, etc.). A particular processing system and/or transceiver may utilize all of the components shown, or only a subset of these components, and the level of integration may vary from device to device.

It should be understood that one or more steps of the embodiment methods provided herein may be performed by corresponding units or modules. For example, the signal may be transmitted by a transmitting unit or a transmitting module. The signal may be received by a receiving unit or a receiving module. The signals may be processed by a processing unit or processing module. The control unit/module, the adjustment unit/module, the determination unit/module, the switching unit/module, the RC-CR phase error calibration unit/module, the image distortion correction unit/module, and/or the FD-IQME unit/module may perform other steps. The respective units/modules may be hardware, software or a combination thereof. For example, one or more units/modules may be an integrated circuit, such as a Field Programmable Gate Array (FPGA) or an application-specific integrated circuit (ASIC).

Although the detailed description has been described, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented. Moreover, the scope of the invention is not intended to be limited to the particular embodiments described herein. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.