阅读说明：本技术 一种mos栅控晶闸管及其制造方法 (MOS grid-controlled thyristor and manufacturing method thereof ) 是由 刘超 杨超 汪淳朋 陈万军 张波 于 2021-08-24 设计创作，主要内容包括：本发明属于功率半导体技术领域,特别涉及一种MOS栅控晶闸管及其制造方法。本发明中的一种MOS栅控晶闸管,主要是通过缩短传统MCT结构栅极面积,并引入第二阴极及P型掺杂区,减小器件栅极通过栅氧化层与衬底接触的面积,从而减小器件栅极-阳极之间的寄生电容,增强MCT器件的dv/dt抗性；本发明中的一种MOS栅控晶闸管的制造方法,能够与现有MOS栅控晶闸管工艺相兼容。本发明的有益效果为,不牺牲器件阻断特性的基础上,极大提升了MCT器件都dv/dt抗性,有效的解决了常规MOS栅控晶闸管在脉冲功率应用时储能电容充电过程中的误开启问题,提升了器件和脉冲电路的稳定性。(The invention belongs to the technical field of power semiconductors, and particularly relates to an MOS (metal oxide semiconductor) grid-controlled thyristor and a manufacturing method thereof. According to the MOS gate-controlled thyristor, the area of a grid electrode of a traditional MCT structure is shortened, a second cathode and a P-type doped region are introduced, and the contact area of the grid electrode of a device and a substrate through a grid oxide layer is reduced, so that the parasitic capacitance between the grid electrode and an anode of the device is reduced, and the dv/dt resistance of the MCT device is enhanced; the manufacturing method of the MOS grid-controlled thyristor can be compatible with the existing MOS grid-controlled thyristor process. The invention has the advantages that the dv/dt resistance of the MCT device is greatly improved on the basis of not sacrificing the blocking characteristic of the device, the problem of false start of the conventional MOS grid-controlled thyristor in the charging process of the energy storage capacitor when the pulse power is applied is effectively solved, and the stability of the device and the pulse circuit is improved.)

1. A MOS grid-controlled thyristor comprises a cellular structure which comprises an anode metal (10), a P-type anode region (9) and an N-type drift region (8) which are sequentially stacked from bottom to top; the upper layer of the N-type drift region (8) is provided with a P-type well region (7), the upper layer of the P-type well region (7) is provided with 2N-type well regions (6) which are symmetrically distributed along the vertical central line of the unit cell, the upper layer of the N-type well region (6) is provided with a P-type cathode region (4), the P-type cathode region (4) is positioned on one side of the N-type well region (6) far away from the vertical central line of the unit cell, and two P-type doped regions (5) are arranged at two ends of the upper layer of the N-type drift region (8) close to the edge of the unit cell; two gate oxide layers (2) which are symmetrically distributed by using a vertical centerline of the cell are arranged at two ends of the upper surface of the cell P-type well region (7), and a polycrystalline silicon gate region (1) is arranged on the upper layer of each gate oxide layer (2); the upper surface of the P-type well region (7) is provided with a cathode metal region (3), and the upper surface of the P-type doped region (5) is provided with a second cathode metal region (11); the upper surfaces of two ends of the P-type well region (7) and the N-type well region (6) are positioned below the polysilicon gate region (1), one part of the P-type cathode region (4) is positioned below the polysilicon gate region (1), and the other part of the P-type cathode region is in contact with the upper surface of the cathode metal region (3).

2. A MOS-gated thyristor according to claim 1, wherein the second cathode metal region (11) is spaced apart from the polysilicon gate (1), the P-type doped region (5) is spaced apart from the P-type well region (7), and the spacing between the second cathode metal region (11) and the polysilicon gate (1) is greater than the spacing between the P-type doped region (5) and the P-type well region (7).

3. A manufacturing method of a MOS grid-controlled thyristor is characterized by comprising the following steps:

the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type drift region (8);

the second step is that: forming a P-type anode region (9) at the bottom of the N-type drift region 8 by adopting an ion implantation and high-temperature diffusion junction pushing process;

the third step: growing silicon dioxide on the upper surface of the N-type drift region (8) to form a gate oxide layer (2), and depositing N-type conductive polycrystalline silicon on the upper surface of the gate oxide layer (2) to form a polycrystalline silicon gate region (1);

the fourth step: forming a P-type well region (7) on the N-type substrate by adopting an ion implantation and high-temperature diffusion junction pushing process;

the fifth step: forming P-type doped regions (5) at two ends of the upper layer of the N-type substrate by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type doped regions (5) and the P-type well regions (7) cannot have overlapping parts;

and a sixth step: adopting ion implantation and high-temperature diffusion knot pushing processes; forming an N-type well region (6) on the upper layer of the P-type well region (7), wherein the N-type well regions (6) are symmetrically distributed around the vertical central line of the unit cell, and the middles of the two N-type well regions (6) are not overlapped;

the seventh step: forming a P-type cathode region (4) on the upper layers of the two N-type well regions (6) by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type cathode region (4) is positioned on one side of the N-type well region (6) far away from the vertical central line of the unit cell and is symmetrically distributed around the vertical central line of the unit cell;

eighth step: depositing a metal layer on the upper surface of the N-type drift region (8) to form a cathode metal region (3) and a second cathode metal region (11), wherein the cathode metal region (3) is positioned in the middle of the cell, and two ends of the cathode metal region are respectively contacted with the upper surface part of the P-type cathode region (4); the second cathode metal regions (11) are positioned at two ends of the unit cell and are arranged on the upper layer of the P-type doped region (5), and the width of the second cathode metal regions along the transverse direction of the device cannot exceed the width of the P-type doped region (5) along the transverse direction of the device.

The ninth step: and depositing a metal layer on the lower surface of the P-type anode region (9) to form an anode metal layer (10).

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to an MOS (metal oxide semiconductor) grid-controlled thyristor and a manufacturing method thereof.

Background

The power semiconductor device is used as a switching device and can be applied to two aspects of the power electronic field and the pulse power field. When applied in the field of pulsed power, semiconductor switching devices are often combined with capacitive or inductive energy storage circuits to produce transient voltage or current pulses. In order to meet the application of pulse power, the switching device needs to have extremely high peak current capability and current rise rate (di/dt), and simultaneously has high voltage rise rate (dv/dt) resistance to ensure the working stability.

The MOS field-Controlled Thyristor (MOS Controlled Thyristor, abbreviated as MCT) has the advantages of both MOS devices and Thyristor devices, has high current density, low conduction power consumption and high turn-on speed, and is very suitable for being applied to the field of pulse power. But also faces problems in practical applications. When the pulse current is generated by using a capacitive energy storage mode, the charging speed of the energy storage capacitor is high, and the rising rate (dv/dt) of the anode voltage of the device is high. Due to the existence of parasitic capacitance between the anode and the grid of the device, instantaneous displacement current can be generated between the grid and the anode at a high voltage change rate and flows through the grid of the device to be released through the grounding of the cathode, when the parasitic resistance between the grid and the cathode is not negligible, the displacement current can generate voltage drop between the grid and the cathode, if the voltage drop exceeds the threshold voltage of the device, the device is started under the condition of no external grid voltage, the device is triggered by mistake, and the stability of the device in the practical application process is further influenced.

Disclosure of Invention

The invention aims to solve the problems, and provides a high dv/dt resistance MOS gate-controlled thyristor and a manufacturing method thereof to solve the problem of false start in the process of charging an energy storage capacitor of a conventional MCT device, so as to improve the reliability of the device and a pulse system.

In order to achieve the purpose, the invention adopts the following technical scheme:

a MOS grid-controlled thyristor is disclosed, as shown in FIG. 2, the cellular structure of which comprises an anode metal 10, a P-type anode region 9 and an N-type drift region 8 which are sequentially stacked from bottom to top; the upper layer of the N-type drift region 8 is provided with P-type well regions 7 which are symmetrically distributed by using a cell vertical central line, the upper layer of the P-type well regions 7 is provided with 2N-type well regions 6 which are symmetrically distributed by using a cell vertical central line, the upper layer of the N-type well regions 6 is provided with a P-type cathode region 4, the P-type cathode region 4 is positioned on one side of the N-type well regions 6 far away from the cell vertical central line, and two P-type doped regions 5 are also arranged at two ends of the upper layer of the N-type drift region 8, close to the edges of the cells; two ends of the upper surface of the cell P-type well region 7 are provided with two gate oxide layers 2 which are symmetrically distributed by using a cell vertical central line, and the upper layer of each gate oxide layer 2 is provided with a polycrystalline silicon gate region 1; the upper surface of the P-type well region 7 is provided with a cathode metal region 3, and the upper surface of the P-type doped region 5 is provided with a second cathode metal region 11. The upper surfaces of two ends of the P-type well region 7 and the N-type well region 6 are positioned below the polycrystalline silicon gate region 1, one part of the P-type cathode region 4 is positioned below the polycrystalline silicon gate region 1, and the other part of the P-type cathode region is in contact with the upper surface of the cathode metal region 3.

Specifically, a gap is reserved between the second cathode metal region 11 and the polysilicon gate 1, a gap is reserved between the P-type doped region 5 and the P-type well region 7, and the gap between the second cathode metal region 11 and the polysilicon gate 1 is slightly larger than the gap between the P-type doped region 5 and the P-type well region 7.

The technical scheme of the invention mainly shortens the traditional grid structure, thereby reducing the contact area of the grid of the device and the substrate through the grid oxide layer and obviously reducing the parasitic capacitance between the grid anode; the invention relieves the electric field concentration phenomenon of the edge of the grid under the blocking state by introducing the second cathode metal region 11, and simultaneously does not sacrifice the blocking characteristic of the device while improving the dv/dt resistance of the device by arranging the P-type doped region 5 below the second cathode metal region 11.

Also provided is a method for manufacturing the MOS gate-controlled thyristor, which comprises the following steps:

the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type drift region 8;

the second step is that: forming a P-type anode region 9 at the bottom of the N-type drift region 8 by adopting an ion implantation and high-temperature diffusion junction pushing process;

the third step: growing silicon dioxide on the upper surface of the N-type drift region 8 to form a gate oxide layer 2, and depositing N-type conductive polycrystalline silicon on the upper surface of the gate oxide layer 2 to form a polycrystalline silicon gate region 1;

the fourth step: forming a P-type well region 7 on an N-type substrate by adopting ion implantation and high-temperature diffusion junction-pushing processes;

the fifth step: forming P-type doped regions 5 at two ends of the upper layer of the N-type substrate by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type doped regions 5 and the P-type well region 7 cannot have overlapping parts;

and a sixth step: adopting ion implantation and high-temperature diffusion knot pushing processes; forming an N-type well region 6 on the upper layer of the P-type well region 7, wherein the N-type well regions 6 are symmetrically distributed about the vertical central line of the unit cell, and the middle parts of the two N-type well regions 6 are not overlapped;

the seventh step: forming a P-type cathode region 4 on the upper layers of the two N-type well regions 6 by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type cathode region 4 is positioned on one side of the N-type well regions 6 far away from the vertical central line of the unit cell and is symmetrically distributed around the vertical central line of the unit cell;

eighth step: depositing a metal layer on the upper surface of the N-type drift region 8 to form a cathode metal region 3 and a second cathode metal region 11, wherein the cathode metal region 3 is positioned in the middle of the cell, and two ends of the cathode metal region are respectively contacted with the upper surface part of the P-type cathode region 4; the second cathode metal regions 11 are located at two ends of the cell and on the upper layer of the P-type doped region 5, and the width along the lateral direction of the device cannot exceed the width along the lateral direction of the device of the P-type doped region 5.

The ninth step: and depositing a metal layer on the lower surface of the P-type anode region 9 to form an anode metal layer 10.

The MOS grid-controlled thyristor with the low grid capacitance and the high dv/dt resistance and the manufacturing method thereof have the advantages that the problem of false start of the conventional MOS grid-controlled thyristor in the charging process of the energy storage capacitor during the application of pulse power is solved, and meanwhile, the manufacturing method provided by the invention is compatible with the traditional MCT process.

Drawings

FIG. 1 is a schematic structural diagram of a conventional MOS-gated thyristor;

FIG. 2 is a schematic structural diagram of a MOS-gated thyristor according to an embodiment;

FIG. 3 is a schematic flow chart of a manufacturing method provided by the present invention;

FIG. 4 is a graph comparing the breakdown characteristics of the example and conventional MCT devices;

FIG. 5 is a graph showing the simulated anode capacitance of the gate of the MCT device

FIG. 6 is a schematic diagram of a dV/dt resistance simulation circuit of the MCT device;

FIG. 7 is a graph showing the dv/dt resistance simulation results of an example and a conventional MCT device when the dv/dt is 37 kv/us;

FIG. 8 is a graph showing the dv/dt resistance simulation results of the example and conventional MCT devices when the dv/dt is 56 kv/us.

Detailed Description

The technical scheme of the invention is described in detail in the following with the accompanying drawings:

fig. 1 is a schematic structural diagram of a conventional MOS-gated thyristor, and fig. 2 is a schematic structural diagram of an MOS-gated thyristor according to an embodiment of the present invention, where both use conduction of a thyristor inside a device to obtain a high current rise rate di/dt and a peak current, so as to satisfy a condition of pulse power application. In practical application, however, due to the parasitic resistance between the gate and the cathode, the gate voltage of the device rises under the coupling of high dv/dt and gate anode capacitance, and exceeds the threshold voltage of the device, so that the device is turned on by mistake, and finally, the pulse system fails. Theoretical analysis shows that when the gate anode capacitance is reduced, the gate voltage induced by the device through dv/dt is reduced, thereby reducing the probability of the device being turned on by mistake.

Compared with the conventional MOS grid-controlled thyristor, the area of the contact between the grid electrode of the device and the substrate through the grid oxide layer is reduced due to the introduction of the second cathode and the P-type doped region below the second cathode, so that the parasitic capacitance of the grid anode is obviously reduced. When the pulse power is applied, the grid current generated under the action of dv/dt is reduced in the charging process of the energy storage capacitor, so that the voltage drop generated on the grid cathode series resistor is reduced, and the possibility of false opening caused by the fact that the grid voltage of the device exceeds the threshold voltage is reduced. Therefore, the invention can effectively improve the dv/dt resistance of the MCT device under the condition of not sacrificing the withstand voltage of the device.

Fig. 3 is a schematic flow chart of a method for manufacturing a MOS-gated thyristor according to the present invention, and fig. 4 is a schematic diagram illustrating a comparison of breakdown characteristics of a conventional MCT device according to the present invention. It can be seen from the figure that the voltage resistance of the device of the present invention is not only not degraded but also slightly increased compared with the conventional MCT device, which also illustrates the structural change of the device of the present invention without sacrificing the MCT blocking capability.

Fig. 5 is a graph showing the gate anode capacitance of the example and a conventional MCT device. The cell width of the MCT device is 100um compared with the cell width of the conventional MCT device, and the area of the MCT device is 1CM 2. As can be seen from the graph, when a voltage of 20V is applied to the anode, the gate anode capacitance of the conventional MCT device is 32pF, while the gate anode capacitance of the present invention is only 4pF, and the gate anode parasitic capacitance Cga of the MCT device in the present invention is significantly smaller than that of the conventional MCT device by 87.5%, which is sufficient to illustrate that the gate anode parasitic capacitance Cga of the MCT device is significantly reduced by the present invention.

FIG. 6 is a schematic diagram of a dv/dt resistance simulation circuit of an MCT device, wherein the selected gate-cathode parasitic resistance Rgk is 100 ohms, the charging circuit parasitic resistance R is 5 ohms, the charging circuit parasitic inductance is 20e-9 henries, the anode charging voltage U0 is 2000V, and the voltage is far less than the actual withstand voltage of the device, and the magnitude of external dv/dt is controlled by changing the anode charging time. FIG. 7 is a graph showing the dv/dt resistance simulation results of the example and the conventional MCT device when the dv/dt is 37kv/us, and FIG. 8 is a graph showing the dv/dt resistance simulation results of the example and the conventional MCT device when the dv/dt is 56 kv/us. The Dv/dt simulation result shows that the traditional MCT device generates false triggering when the Dv/dt is 37kv/us, while the MCT of the invention does not generate false triggering when the Dv/dt reaches 56kv/us, and the Dv/dt resistance of the MCT device of the invention is improved by about 51 percent compared with that of the traditional MCT device. Therefore, by shortening the area of the grid of the traditional MCT structure and introducing the second cathode and the P-type doped region, the contact area of the grid of the device and the substrate through the grid oxide layer can be reduced, so that the parasitic capacitance between the grid and the anode of the device is reduced, the dv/dt resistance of the MCT device is enhanced, the problem of mistaken starting of the conventional MOS grid-controlled thyristor in the charging process of the energy storage capacitor when pulse power is applied is effectively solved, and the stability of the device and a pulse circuit is improved.

Taking the schematic structure diagram of the device shown in fig. 2 as an example, the manufacturing method comprises the following steps:

the first step is as follows: manufacturing a junction terminal by using a substrate silicon wafer to form an N-type drift region 8;

the second step is that: forming a P-type anode region 9 at the bottom of the N-type drift region 8 by adopting an ion implantation and high-temperature diffusion junction pushing process;

the third step: growing silicon dioxide on the upper surface of the N-type drift region 8 to form a gate oxide layer 2, and depositing N-type conductive polycrystalline silicon on the upper surface of the gate oxide layer 2 to form a polycrystalline silicon gate region 1;

the fourth step: forming a P-type well region 7 on an N-type substrate by adopting ion implantation and high-temperature diffusion junction-pushing processes;

the fifth step: forming P-type doped regions 5 at two ends of the upper layer of the N-type substrate by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type doped regions 5 and the P-type well region 7 cannot have overlapping parts;

and a sixth step: adopting ion implantation and high-temperature diffusion knot pushing processes; forming an N-type well region 6 on the upper layer of the P-type well region 7, wherein the N-type well regions 6 are symmetrically distributed about the vertical central line of the unit cell, and the middle parts of the two N-type well regions 6 are not overlapped;

the seventh step: forming a P-type cathode region 4 on the upper layers of the two N-type well regions 6 by adopting an ion implantation and high-temperature diffusion junction-pushing process, wherein the P-type cathode region 4 is positioned on one side of the N-type well regions 6 far away from the vertical central line of the unit cell and is symmetrically distributed around the vertical central line of the unit cell;

eighth step: depositing a metal layer on the upper surface of the N-type drift region 8 to form a cathode metal region 3 and a second cathode metal region 11, wherein the cathode metal region 3 is positioned in the middle of the cell, and two ends of the cathode metal region are respectively contacted with the upper surface part of the P-type cathode region 4; the second cathode metal regions 11 are located at two ends of the cell and on the upper layer of the P-type doped region 5, and the width along the lateral direction of the device cannot exceed the width along the lateral direction of the device of the P-type doped region 5.

The ninth step: and depositing a metal layer on the lower surface of the P-type anode region 9 to form an anode metal layer 10.

It should be noted that the manufacturing method of the MOS-gated thyristor provided by the present invention is compatible with the conventional MOS-gated thyristor process, and only one additional mask needs to be added for injecting the P-type doped region, which can bring about a greater dv/dt resistance improvement compared with the conventional MOS-gated thyristor, and greatly improve the stability in the application process at a later stage, although the cost is slightly increased.