阅读说明：本技术 具有自举高侧驱动器的开关模式dc/dc转换器 (Switch mode DC/DC converter with self-elevating side driver ) 是由 E·乔达 J·贝克尔 C·施特克 于 2020-02-03 设计创作，主要内容包括：一种用于DC/DC升压转换器(100)中的高侧NMOS功率晶体管(Mhs)的栅极驱动器(103)包括在输出引脚(P1)和高侧晶体管的栅极之间串联耦合的第一开关(102)和第二开关(104)。第三开关(106)耦合在栅极与高侧晶体管(Mhs)和低侧晶体管(Mls)之间的开关节点(SW)之间,开关节点还耦合到输入引脚(P3)。第四开关(108)和第五开关(110)串联耦合在输出引脚和钳位引脚(P4)之间。第六开关(112)和第七开关(114)串联耦合在输出引脚和接地引脚(P2)之间。第一自举电容器(C1)和第二自举电容器(C2)具有耦合到第一开关和第二开关之间的第一节点(105)的各自的第一端子。第一电容器具有耦合到第四开关与第五开关之间的节点(107)的第二端子；第二电容器具有耦合到第六开关和第七开关之间的节点(109)的第二端子。(A gate driver (103) for a high-side NMOS power transistor (Mhs) in a DC/DC boost converter (100) includes a first switch (102) and a second switch (104) coupled in series between an output pin (P1) and the gate of the high-side transistor. A third switch (106) is coupled between the gate and a switch node (SW) between the high-side transistor (Mhs) and the low-side transistor (Mls), the switch node also being coupled to the input pin (P3). A fourth switch (108) and a fifth switch (110) are coupled in series between the output pin and the clamp pin (P4). The sixth switch (112) and the seventh switch (114) are coupled in series between the output pin and the ground pin (P2). The first bootstrap capacitor (C1) and the second bootstrap capacitor (C2) have respective first terminals coupled to a first node (105) between the first switch and the second switch. The first capacitor has a second terminal coupled to a node (107) between the fourth switch and the fifth switch; the second capacitor has a second terminal coupled to a node (109) between the sixth switch and the seventh switch.)

1. A gate driver for a high-side N-type metal oxide silicon (NMOS) power transistor in a DC/DC boost converter implemented in an Integrated Circuit (IC) chip, the gate driver comprising:

a first switch coupled in series with a second switch between an output pin for coupling to an output voltage and a gate of the high-side NMOS power transistor;

a third switch coupled between the gate of the high-side NMOS power transistor and a switch node between the high-side NMOS power transistor and a low-side NMOS power transistor, the switch node further coupled to an input pin;

a fourth switch coupled in series with a fifth switch between the output pin and a clamping pin for coupling to a clamping voltage;

a sixth switch coupled in series with a seventh switch between the output pin and a ground pin for coupling to a lower rail;

a first bootstrap capacitor having a first terminal coupled to a first node between the first switch and the second switch and a second terminal coupled to a second node between the fourth switch and the fifth switch; and

a second bootstrap capacitor having a first terminal coupled to the first node and a second terminal coupled to a third node between the sixth switch and the seventh switch.

2. The gate driver of claim 1, wherein the first bootstrap capacitor is coupled to provide a first bootstrap voltage across the respective first and second terminals, and the second bootstrap capacitor is coupled to provide a second bootstrap voltage across the respective first and second terminals, the second bootstrap voltage being greater than the first bootstrap voltage.

3. The gate driver of claim 2, wherein the second terminal of the first bootstrap capacitor is formed in a substrate of the IC chip.

4. The gate driver of claim 3, wherein the second bootstrap capacitor overlies the first bootstrap capacitor and has the same area as the first bootstrap capacitor.

5. The gate driver of claim 1, wherein the first switch, the third switch, the fifth switch, and the seventh switch are coupled to be closed during a first phase, and the second switch, the fourth switch, and the sixth switch are coupled to be closed during a second phase.

6. A DC/DC boost converter implemented in an Integrated Circuit (IC) chip, the DC/DC boost converter comprising:

a high-side NMOS power transistor coupled in series with the low-side NMOS power transistor between an output pin for coupling to an output voltage and a ground pin for coupling to a lower rail;

a switch node between the high-side NMOS power transistor and the low-side NMOS power transistor, the switch node coupled to an input pin for coupling to an input voltage through an inductor;

a first bootstrap capacitor having a first terminal coupled to selectively connect to one of an output voltage and a gate of the high-side NMOS power transistor and a second terminal coupled to selectively connect to one of the output pin and a clamp pin for coupling to a clamp voltage; and

a second bootstrap capacitor having a first terminal coupled to be selectively connected to one of the output pin and the gate of the high-side NMOS power transistor and a second terminal coupled to be selectively connected to one of the ground pin and the output pin.

7. The DC/DC boost converter of claim 6, wherein the second terminal of the first bootstrap capacitor is formed in a substrate of the IC chip.

8. A DC/DC boost converter according to claim 7, wherein the second bootstrap capacitor overlies the first bootstrap capacitor.

9. The DC/DC boost converter of claim 7, wherein the area of the second bootstrap capacitor is the same as the area of the first bootstrap capacitor.

10. The DC/DC boost converter of claim 6, wherein the gate of the high-side NMOS power transistor is coupled to connect to the switch node during a first phase of operation of the DC/DC boost converter and to connect to respective first terminals of the first and second bootstrap capacitors during a second phase of operation.

11. The DC/DC boost converter of claim 10, wherein the respective first terminals of the first and second bootstrap capacitors are further coupled to connect to the output pin during a first phase of the operation.

12. The DC/DC boost converter of claim 11, wherein the second terminal of the first bootstrap capacitor is further coupled to connect to the clamp pin during a first phase of the operation.

13. The DC/DC boost converter of claim 12, wherein the second terminal of the second bootstrap capacitor is further coupled to be connected to the lower rail during a first phase of the operation.

14. The DC/DC boost converter of claim 13, wherein respective second terminals of the first and second bootstrap capacitors are coupled to connect to the output pin during a second phase of the operation.

15. A method of operating a DC/DC boost converter, comprising:

providing the DC/DC boost converter on an Integrated Circuit (IC) chip, the DC/DC boost converter including a stacked bootstrap capacitor; and

an output pin of the IC chip is coupled to provide an output voltage, wherein the output pin is coupled to a respective first terminal of the stacked bootstrap capacitor during a first phase and to a respective second terminal of the stacked bootstrap capacitor during a second phase.

16. The method of claim 15, further comprising:

coupling a ground pin of the IC chip to a ground plane; and

an input pin of the IC chip is coupled to an inductor and an input voltage.

17. The method of claim 16, further comprising coupling a clamp pin of the IC chip to a clamp voltage.

Technical Field

The described embodiments relate generally to the field of voltage conversion circuits. More specifically, and not by way of any limitation, the present description is directed to a switch mode DC/DC converter with a self-elevating side driver.

Background

In the power stage of the DC/DC boost converter, two N-type metal oxide silicon (NMOS) transistors may be employed as the low-side and high-side switches. This arrangement may utilize a bootstrapped gate driver for the high-side switch. To generate a stable bootstrap voltage, a large capacitor may be required. The use of large capacitors may occupy a large area and introduce additional switching losses, thereby reducing converter efficiency. Improvements are desirable.

Disclosure of Invention

The described embodiments provide a switched mode DC/DC boost converter using stacked bootstrap capacitors that can be charged to different bootstrap voltages. Stacking the bootstrap capacitor reduces the area required and may provide additional advantages to be described.

In one aspect, embodiments are disclosed for a gate driver for a high-side NMOS power transistor in a DC/DC boost converter implemented in an IC chip. The gate driver includes: a first switch coupled in series with a second switch between an output pin for coupling to an output voltage and a gate of a high-side NMOS power transistor; a third switch coupled between the gate of the high-side NMOS power transistor and a switch node, the switch node being located between the high-side NMOS power transistor and the low-side NMOS power transistor and further coupled to the input pin; a fourth switch coupled in series with the fifth switch between the output pin and a clamp pin for coupling to a clamp voltage; a sixth switch coupled in series with the seventh switch between the output pin and a ground pin for coupling to the lower rail; a first bootstrap capacitor having a first terminal coupled to a first node between the first switch and the second switch and a second terminal coupled to a second node between the fourth switch and the fifth switch; and a second bootstrap capacitor having a first terminal coupled to the first node and a second terminal coupled to a third node between the sixth switch and the seventh switch.

In another aspect, embodiments of a DC/DC boost converter implemented in an IC chip are described. The DC/DC boost converter includes: a high-side N-type metal oxide silicon (NMOS) power transistor coupled in series with the low-side NMOS power transistor between an output pin for coupling to an output voltage and a ground pin for coupling to a lower rail; a switch node between the high side NMOS power transistor and the low side NMOS power transistor, the switch node coupled to an input pin, the input pin coupled to an input voltage through an inductance; a first bootstrap capacitor having a first terminal coupled to be selectively connected to one of the output voltage and a gate of the high-side NMOS power transistor and one of a clamp pin for coupling to the clamp voltage and an output pin; and a second bootstrap capacitor having a first terminal coupled to be selectively connected to one of the output pin and the gate of the high-side NMOS power transistor and a second terminal coupled to be selectively connected to one of the ground pin and the output pin.

In yet another aspect, embodiments of a method of operating a DC/DC boost converter are described. The method includes providing a DC/DC boost converter on an Integrated Circuit (IC) chip, the DC/DC boost converter including a stacked bootstrap capacitor; and an output pin of the IC chip is coupled to provide an output voltage, wherein the output pin is coupled to a respective first terminal of the stacked bootstrap capacitor during the first phase and to a respective second terminal of the stacked bootstrap capacitor during the second phase.

Drawings

Embodiments of the specification are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. It should be noted that different references to "an" or "one" embodiment in this specification are not necessarily to the same embodiment, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. As used herein, the term "couple" or "couples" is intended to mean an indirect or direct electrical connection, unless defined as a "communicative coupling" which may include a wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

FIG. 1 depicts an example of a switch-mode DC/DC boost converter implemented in an integrated circuit chip;

FIGS. 2A and 2B depict the position of the switch of FIG. 1 during two phases of operation;

FIG. 3A depicts the voltage across the first and second bootstrap capacitors as the output voltage increases;

FIG. 3B depicts a graph of Rds-on, hs as the output voltage increases;

FIG. 4A depicts the relative area consumed in implementing the high-side NMOS power transistor, the high-side gate drive switch, and the bootstrap capacitor C1 in accordance with an embodiment of the circuit of FIG. 9;

FIG. 4B depicts the relative area consumed in implementing the high-side NMOS power transistor, the high-side gate drive switch, and the bootstrap capacitor C1/C2;

FIG. 5 depicts a cross-section along line A-A' of FIG. 4B;

FIG. 6 depicts a plot of the capacitance ratio of the bootstrap capacitor C2 to the bootstrap capacitor C1 versus how many times smaller the stacked capacitor implementation is than the single capacitor implementation;

FIG. 7 depicts the overall boost converter efficiency of a single bootstrap capacitor implementation versus a stacked bootstrap capacitor implementation;

FIG. 8 depicts a flow chart of a method of operating a DC/DC boost converter; and

fig. 9 depicts an example of a switched mode DC/DC boost converter according to the prior art.

Detailed Description

Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

A prior art DC/DC boost converter 900 with an output voltage Vout of up to 10V is shown in fig. 9. The DC/DC boost converter 900 is implemented on an Integrated Circuit (IC) chip 901, which chip 901 may be coupled to a first terminal of an inductor L, with an input voltage Vin coupled to a second terminal of the inductor L. The DC/DC boost converter 900 is also coupled to the output voltage Vout and the lower rail, which may be a ground plane. The bootstrap capacitor C1 is provided on the chip, and in the illustrated embodiment, the technology used to fabricate the IC chip 901 can only handle voltages across the bootstrap capacitor C1 of 5V. Because the first terminal of the bootstrap capacitor C1 is coupled to the output voltage Vout, which may have a value up to 10V, the clamping voltage Vclamp may be coupled to the second terminal of the bootstrap capacitor C1 to limit the voltage across the bootstrap capacitor C1. Therefore, when the output voltage Vout is 10V, the clamp voltage Vclamp is 5V.

The DC/DC boost converter 900 includes a high side NMOS power transistor Mhs coupled in series with a low side NMOS power transistor Mls between the output voltage Vout and the lower rail. The switch node SW is located between the high-side NMOS power transistor Mhs and the low-side NMOS power transistor Mls, and may be coupled to the inductor L to receive the input voltage Vin. Control of the low-side NMOS power transistor Mls is generally easier than control of the high-side NMOS power transistor Mhs, and is shown simply as a driver circuit 920 that is coupled to the voltage Vdd and the lower rail and receives the activate signal ACTls.

The driver circuit for the high-side NMOS power transistor Mhs includes a bootstrap capacitor Cl and 5 switches 902-910. These switches are shown in their most general form, as the exact implementation of the switches is not relevant to the present description. A first terminal of the bootstrap capacitor C1 is coupled to a switch 902 that operates to couple that terminal to the output voltage Vout. The first terminal is also coupled to a switch 904 operative to couple the first terminal to a gate of a high-side NMOS power transistor Mhs. The gate of the high-side NMOS power transistor Mhs is also coupled to a switch 906, which operates to couple the gate to the switch node SW. The second terminal of the bootstrap capacitor C1 is coupled to a switch 908, which operates to couple the second terminal to the output voltage Vout, and is also coupled to a switch 910, which operates to couple the second terminal to the clamping voltage Vclamp.

The switches 902-910 operate in two phases, where the switches are coupled in the phases to be closed as shown in fig. 9. In a first phase Φ 1, which occurs when the low side NMOS power transistor Mls is on, switches 902, 906, and 910 are closed and switches 904 and 908 are open. The bootstrap capacitor C1 is charged to a bootstrap voltage Vboot1, which is Vboot1 equal to the output voltage Vout minus the clamp voltage Vclamp, which in one embodiment is 5V. Meanwhile, the gate of the high-side NMOS power transistor Mhs is coupled to the switch node SW through a switch 906. Since the gate and source terminals of the power transistors are at the same potential, the high-side NMOS power transistor Mhs remains in an off state.

In the second phase Φ 2, the low-side power transistor Mls is turned off, switches 902, 906, and 910 are open and switches 904 and 908 are closed. The second terminal of the bootstrap capacitor C1 now receives the output voltage Vout. The charge accumulated during the first phase Φ 1 is shared with the gate capacitor of the high-side NMOS power transistor Mhs, generating a gate-source voltage and turning on the high-side NMOS power transistor Mhs. As previously described, the integrated bootstrap capacitor C1 may occupy a large area on the IC chip 901 and introduce additional switching losses that reduce the converter efficiency.

Fig. 1 depicts a DC/DC boost converter 100 implemented on an IC chip 101 and having an output voltage of up to 10V. The DC/DC boost converter 100 includes a high side NMOS power transistor Mhs and a low side NMOS power transistor Mls, and has a switching node SW between the high side NMOS power transistor Mhs and the low side NMOS power transistor Mls, the high side NMOS power transistor Mhs and the low side NMOS power transistor Mls being coupled in series between an output pin P1 for coupling to the output voltage Vout and a ground pin P2 for coupling to the lower rail. The switch node SW is coupled to an input pin P3, which is coupled to the inductor L and through the inductor L to the input voltage Vin during operation of the DC/DC boost converter 100.

The high side NMOS power transistor Mhs is controlled by a gate driver 103, the gate driver 103 includes a first bootstrap capacitor C1, a second bootstrap capacitor C2, and 7 switches 102-114; the low-side gate driver 120 is coupled between the voltage Vdd and the lower rail and receives the activate low-side signal ACTls. As shown in FIG. 9, FIG. 1 illustrates a stage in which each of the switches 102 and 114 is coupled closed. Although their structures are on different levels of the chip, the first bootstrap capacitor C1 and the second bootstrap capacitor C2 are both on-chip capacitors, as explained below. The first bootstrap capacitor C1 is again limited in the voltage it can handle and may be coupled to the clamp voltage Vclamp via clamp pin P4, while the second bootstrap capacitor C2 may handle the full output voltage Vout across the plates and be coupled to the lower rail through ground pin P2. It may be noted that 3 ground pins P2 are shown in fig. 1. In power supply circuits, the actual number of pins coupled to the high current pins may vary depending on the needs and design of the circuit, and these descriptions should not be considered limiting. In one embodiment, the clamp voltage Vclamp is 5V. A first terminal of each of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 is coupled to the first node 105.

With respect to the switching circuit of the gate driver 103, the first switch 102 and the second switch 104 are coupled in series between the output pin Pl and the gate of the high-side NMOS power transistor Mhs, with the first node 105 located between the first switch 102 and the second switch 104. The third switch 106 is coupled between the gate of the high-side NMOS power transistor Mhs and the switch node SW. The fourth switch 108 is coupled in series with the fifth switch 110 between the output pin P1 and the clamping voltage Vclamp, with the second terminal of the first bootstrap capacitor C1 coupled to the second node 107 between the fourth switch 108 and the fifth switch 110. The sixth switch 112 and the seventh switch 114 are coupled in series between the output pin P1 and a lower rail, which in one embodiment is a ground plane, with a second terminal of the second bootstrap capacitor C2 coupled to a third node 109 between the sixth switch 112 and the seventh switch 114.

The operation of the switches 102 and 114 again occurs in two different phases, which are described with reference to fig. 2A and 2B. Inactive transistors, switches and paths are shown as dashed lines, while active transistors, switches and paths are shown as solid lines. During the first phase Φ 1 shown in fig. 2A, the first switch 102, the third switch 106, the fifth switch 110, and the seventh switch 114 are closed, while the second switch 104, the fourth switch 108, and the sixth switch 112 are open. During the first phase Φ 1, a first bootstrap capacitor C1 is coupled between the output pin P1 and the clamp pin P4 to charge the first bootstrap capacitor C1 to a first bootstrap voltage Vboot1 equal to (Vout-Vclamp), and a second bootstrap capacitor C2 is coupled between the output pin P1 and the lower rail to charge the second bootstrap capacitor C2 to a second bootstrap voltage Vboot2 equal to the output voltage Vout. The third switch 106 couples the gate of the high-side NMOS power transistor Mhs to the switch node SW when the first and second bootstrap capacitors C1 and C2 are charging. Closing the third switch 106 ensures that the gate and source terminals of the high-side NMOS power transistor Mhs are at the same potential and that the high-side NMOS power transistor Mhs is in an off state.

Then in the second phase Φ 2 shown in fig. 2B, the second switch 104, the fourth switch 108, and the sixth switch 112 are closed, while the first switch 102, the third switch 106, the fifth switch 110, and the seventh switch 114 are open. During the second phase Φ 2, the low side NMOS power transistor Mls turns off. Current continues to flow through the inductor L and begins to charge the switch node SW, which is now decoupled from the gate of the high-side NMOS power transistor Mhs. At the same time, coupling the bottom plate of the first bootstrap capacitor C1 and the bottom plate of the second bootstrap capacitor C2 (i.e., the plate with the lower voltage) to the output pin P1 and the output voltage Vout through the fourth switch 108 and the sixth switch 112, respectively, results in a corresponding increase in the voltage on the top plate of the capacitor. The total charge accumulated during the first phase Φ 1 is shared with the gate capacitor of the high-side NMOS power transistor Mhs, generating a gate/source voltage and turning on the high-side NMOS power transistor Mhs.

Fig. 3A depicts the bootstrap voltages Vboot1 and Vboot2 as the value of the output voltage Vout increases. As the output voltage Vout increases, the clamping voltage Vclamp applied to the second terminal of the bootstrap capacitor C1 is adjusted to ensure that the first bootstrap voltage Vboot1 remains the same across all values of the output voltage Vout. The second bootstrap capacitor C2 is powered by the output voltage Vout and the lower rail (e.g., ground plane), such that the second startup voltage Vboot2 rises in direct proportion to the output voltage Vout. Meanwhile, as shown in fig. 3B, the high side drain/source on-resistances Rds-on, hs are inversely proportional to the output voltage Vout and decrease as the output voltage increases. Thus, for lower output voltage Vout values, the operation of high-side NMOS power transistor Mhs reduces switching losses due to lower gate/source voltage Vgs, while at higher output voltage Vout values, the operation of high-side NMOS power transistor Mhs reduces conduction losses due to higher overdrive reducing drain/source on-resistance Rds-on, hs.

As shown, the DC/DC boost converter 100 includes two independent bootstrap capacitors chargeable to different voltages, where the first bootstrap voltage Vboot contributed by the first bootstrap capacitor C1 remains constant, while the second bootstrap voltage Vboot2 increases in proportion to the output voltage Vout. The charge shared between the first bootstrap capacitor C1 and the second bootstrap capacitor C2 can reduce the capacitance required by the individual capacitors. Further, the DC/DC boost converter efficiency is improved by making one of the voltages (e.g., the second bootstrap voltage Vboot2) dependent on the operating point of the output voltage Vout. When the DC/DC boost converter 100 is implemented in the IC chip 101, the second bootstrap capacitor C2 may be stacked in the layout to achieve a significant area reduction.

Fig. 4A depicts the relative footprint on an IC chip for the components of the high-side circuit 400A of the DC/DC boost converter 900. The high-side NMOS power transistor area HS-NMOS 402A consumes about half of the chip portion dedicated to the high-side circuit 400A. In the remaining half of the high-side circuit 400A, the C1 capacitor area 404A consumes approximately two-thirds, and the gate drive switch area HS _ GDRV 406A consumes the remaining one-third.

Fig. 4B depicts the relative footprints of the components of the high-side circuit 400B for the DC/DC boost converter 100. In the embodiment shown, the high-side NMOS power transistor area HS-NMOS 402B has been reduced by approximately 10%. This reduction in area depends on the capacitance ratio between the first bootstrap capacitor C1 and the second bootstrap capacitor C2, which affects the extent to which the gate/source voltage of the high-side switch varies within the voltage range of Vout, and can vary. The reduction in on-chip capacitor area is even more significant. The C1/C2 capacitor area 404B is less than half the size of the C1 capacitor area 404A. By stacking two capacitors having the same capacitance, the area consumed by the capacitors can be halved. More area may be reduced when a high voltage capacitor (e.g., the second bootstrap capacitor C2) is stacked on an existing capacitor with a limited voltage. Also, the actual reduction in space used by the capacitor depends on the capacitance ratio, as described below. The size of the high-side gate-driven switch area HS-GDRV406B is substantially the same as in the prior art because the increased area for the new switches 112, 114 is commensurate with the possible reduction in switch size of the first bootstrap capacitor C1 due to current sharing with the second bootstrap capacitor C2.

Fig. 5 depicts a portion of an IC chip 500 on which stacked bootstrap capacitors C1 and C2 are implemented and corresponds to a cross-section taken at line a-a' of fig. 4B. As shown, the second bootstrap capacitor C2 overlies the first bootstrap capacitor C1 and has the same area as the first bootstrap capacitor C1. Although not required to have the same area in the described embodiments, fabricating the first and second bootstrap capacitors C1 and C2 to have the same area provides for minimal area usage. The epitaxial layer 502 of the IC chip 500 comprises a thick oxide layer 504, a doped well forming the bottom plate 506 of the first capacitor C1 in the substrate of the IC chip 500, and a contact region 508 for the bottom plate 506. The oxide layer covers the bottom plate 506 and forms a capacitor dielectric 510 for the first capacitor C1. In one embodiment, capacitor dielectric 510 is formed at the same time that the gate oxide for the logic transistors on IC chip 500 is formed. The polysilicon layer forms the upper plate 512 of the first capacitor C1.

Dielectric layer 514 separates upper plate 512 from lower metal wiring stack 518, and vias 516 form connections between lower metal wiring stack 518 and both contact region 508 and upper plate 512. Dielectric layer 520 separates lower metal routing stack 518 from second capacitor C2, which second capacitor C2 is comprised of lower plate 522 and upper plate 524 separated by C2 dielectric layer 526. Upper metal routing stack 530 is coupled to both upper plate 524 and lower plate 522 through respective vias 532. The overlap region between the first capacitor C1 and the second capacitor C2 is shown by arrow 534. The arrow 534 also depicts the overlap between the upper plate 524 and the lower plate 522 of the second capacitor C2, and the overlap between the upper plate 512 and the lower plate 506 of the first capacitor C1.

The mathematical operation of area reduction will now be shown. An implementation of the bootstrap capacitor C1 of fig. 9 is fabricated in a similar manner to the first capacitor C1 of fig. 5, in fig. 5 the first plate is a heavily doped polysilicon layer, separated from the second plate formed in the substrate of the wafer by a gate oxide layer. For such a single 5V bootstrap capacitor implementation, the total charge in the 5V gate oxide capacitor C1 is expressed as:

Q1-5V · C1 equation 1

Where Q is the charge and C is the capacitance.

The gate-source voltage Vgs resulting from the charge redistribution between the bootstrap capacitor C1 and the gate of the high-side NMOS power transistor Mhs is represented by:

where Cgg is the effective gate capacitance of the high-side NMOS power transistor Mhs. Rearranging the equation to determine the bootstrap capacitance can be:

turning next to the stacked bootstrap capacitor embodiment described, the total charge in the 5V gate oxide capacitor and the high voltage capacitor charged to 10V is expressed as:

q1, 2 ═ 5V · C1+10V · C2 equation 4

The gate-to-source voltage Vgs of the high-side NMOS power transistor resulting from the charge redistribution between the gates of the first bootstrap capacitor C1, the second bootstrap capacitor C2, and the high-side NMOS power transistor Mhs is:

assuming that the capacitance of the high voltage capacitor is 1/r of the capacitance of the 5V gate oxide capacitor, the following results are obtained:

solving the equation for bootstrap capacitance yields:

comparing the 5V gate oxide bootstrap capacitance value with the proposed stacked capacitor implementation using a single capacitor yields:

since the second bootstrap capacitor C2 is stacked on top of the first bootstrap capacitor C1, the reduction of the 5V gate oxide capacitor C1 directly translates to an area reduction.

Fig. 6 depicts a graph 600 in which the Y-axis provides the ratio of the capacitor area when a single bootstrap capacitor is used to the capacitor area when stacked bootstrap capacitors are used, and the X-axis depicts the capacitance ratio r. It can be seen that as the capacitance ratio becomes larger, the area reduction becomes smaller. The embodiment of fig. 1 is implemented along a curve at point 602 where the capacitance ratio plotted on the X-axis is 3 and the area reduction plotted on the Y-axis is 2.444 times.

Fig. 7 depicts a graph 700 comparing the overall boost converter efficiency of a single capacitor embodiment, illustrated by curve 702, and the overall boost converter efficiency of the stacked capacitor embodiment of fig. 1, illustrated by curve 704. The efficiency loss of the bootstrap capacitor includes the high side gate charge that needs to be replenished at each switching cycle, and the capacitor isolation well associated with the dynamically moving high voltage node. The proposed capacitor stack implementation reduces the capacitor isolation well. The estimated efficiency curves show an improvement of about 4% in the light load region where switching losses dominate.

Fig. 8 depicts a flow diagram of a method 800 of operating a DC/DC boost converter in accordance with an embodiment of the specification. Method 800 begins by providing (805) a DC/DC boost converter on an IC chip, where the DC/DC boost converter has a stacked bootstrap capacitor. The method continues with coupling (810) an output pin of the IC chip to provide an output voltage such that the output voltage is coupled to a respective first terminal of the stacked bootstrap capacitor during a first phase and to a respective second terminal of the stacked bootstrap capacitor during a second phase. Further elements include coupling (815) a ground pin of the IC chip to a ground plane; coupling (820) an input pin of the IC chip to an inductor and an input voltage; and coupling (825) a clamp pin of the IC chip to a clamp voltage.

Applicants have described a DC/DC boost converter with a high-side NMOS power transistor and stacked bootstrap capacitor implementation that may exhibit one or more of the following advantages: the chip area of the high-side switch is reduced, the chip area of the stacked capacitor is reduced, less switching losses and dynamic on-resistance, the latter two of the advantages being attributed to the dynamic bootstrap voltage of the second bootstrap capacitor. Applicants have also described a method of operating a DC/DC boost converter.

Although various embodiments have been illustrated and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed description should be read as implying that any particular component, element, step, action, or function is essential such that it must be included in the claims scope. The singular forms "a", "an", and "the" are not intended to mean "one and only one" unless specifically stated otherwise. All structural and functional equivalents to the elements of the above-described embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with modification and alteration within the spirit and scope of the appended claims.