阅读说明：本技术 一种逆导型mos栅控晶闸管及其制造方法 (Reverse conducting MOS grid-controlled thyristor and manufacturing method thereof ) 是由 刘超 汪淳朋 杨超 陈万军 张波 于 2021-09-01 设计创作，主要内容包括：本发明属于功率半导体技术领域,具体的说是涉及一种逆导型MOS栅控晶闸管及其制造方法。本发明中的一种逆导型MOS栅控晶闸管,主要是通过缩短常规RC-MCT器件的FS层宽度,增大P型阳极区上方的电阻,从而减小器件正向导通过程中的回跳电压,改善器件正向导通过程中的snapback效应；本发明中的一种逆导型MOS栅控晶闸管的制造方法,能够与现有MOS栅控晶闸管工艺相兼容。本发明的有益效果为：在不牺牲器件正向阻断能力的基础上,改善了器件正向导通过程中的snapback效应,提升了器件在正向导通过程中的稳定性。(The invention belongs to the technical field of power semiconductors, and particularly relates to a reverse conducting MOS (metal oxide semiconductor) grid-controlled thyristor and a manufacturing method thereof. The reverse conducting MOS grid-controlled thyristor is mainly characterized in that the resistance above a P-type anode region is increased by shortening the width of an FS layer of a conventional RC-MCT device, so that the rebound voltage of the device in the forward conducting process is reduced, and the snapback effect of the device in the forward conducting process is improved; the manufacturing method of the reverse conducting MOS grid-controlled thyristor can be compatible with the existing MOS grid-controlled thyristor process. The invention has the beneficial effects that: on the basis of not sacrificing the forward blocking capability of the device, the snapback effect of the device in the forward conduction process is improved, and the stability of the device in the forward conduction process is improved.)

1. A cell junction of a reverse conducting MOS grid-controlled thyristor comprises an anode structure, a drift region structure positioned on the upper surface of the anode structure, a grid structure positioned on the upper surface of the drift region and a cathode structure; the drift region structure comprises an N-drift region (7) and an FS layer (8), wherein the N-drift region (7) is positioned on the upper layer of the FS layer (8), and the upper surface of the FS layer (8) is in contact with the N-drift region (7); the gate structure comprises a gate oxide layer (3) and a gate electrode (1), wherein the gate oxide layer (3) is positioned at one end of the upper surface of the N-drift region (7); the cathode structure comprises cathode metal (2), a P-type deep well region (4), an N well region (5) and a P well region (6), wherein the cathode metal (2) is located at the other end of the upper surface of the N-drift region (7), the cathode structure is characterized in that the P well region (6) is arranged on the upper layer of the N-drift region (7), the N well region (5) is arranged on the upper layer of the P well region (6), the P-type deep well region (4) is arranged on the upper layer of the N well region (5), and two ends of the upper surfaces of the P-type deep well region (4), the N well region (5) and the P well region (6) are respectively in contact with the silicon dioxide insulating layer (3) and the bottom of the cathode metal (2); the positive pole structure includes positive pole metal (11), N type anode region (10), P type anode region (9), the upper surface in P type anode region (9) and the bottom contact of FS layer (8), the upper surface in N type anode region (10) and the bottom contact in N-drift region (7), the side and the P type anode region (9) contact in N type anode region (10). The lower surface of the N-type anode region (10) and the lower surface of the P-type anode region (9) are in contact with the upper surface of the anode metal (11).

2. A manufacturing method of a reverse conducting MOS grid-controlled thyristor is characterized by comprising the following steps:

the first step is as follows: selecting an N-type silicon wafer as a substrate silicon wafer, namely an N-drift region (7) in the structure, firstly injecting N-type impurities into one end of the back surface of the N-drift region (7) through photoetching ions and performing junction pushing to form an N-type FS layer (8);

the second step is that: forming a gate oxide layer (3) on one end of the upper surface of the N-drift region (7) through thermal oxidation, depositing a layer of polycrystalline silicon/metal on the gate oxide layer (3), and etching to form a gate electrode (1);

the third step: injecting P-type impurities into the other end of the upper layer of the N-drift region (7) and pushing the P-type impurities to form a P well region (6) by utilizing an ion injection and high-temperature junction pushing process, wherein the upper surface of one end of the P well region (6) is contacted with the bottom of the gate oxide layer (3);

the fourth step: injecting N-type impurities into the upper layer of the P well region (6) to form an N well region (5) by utilizing ion injection and high-temperature junction pushing processes, wherein the upper surface of one end of the N well region (5) is contacted with the bottom of the gate oxide layer (3);

the fifth step: injecting P-type impurities into the upper layer of the N-well region (5) to form a P-type deep well region (4) by utilizing ion injection and high-temperature junction pushing processes, wherein the upper surface of one end of the P-type deep well region (4) is contacted with the bottom of the gate oxide layer (8);

and a sixth step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;

the seventh step: depositing metal on the other end of the upper surface of the N-drift region (7) to form cathode metal (2); the bottom of the cathode metal (2) is contacted with the upper surfaces of the other ends of the P well region (5), the N well region (6) and the P deep well region (7);

eighth step: depositing a passivation layer on the surface of the device;

the ninth step: injecting P-type impurities into the lower layer of the back N-type FS layer (8) through photoetching ions and carrying out ion activation to form a P-type anode region (9);

the tenth step: injecting N-type impurities into one end of the lower layer of the back N-drift region (7) through photoetching ions and activating the ions to form an N-type anode region (10);

the eleventh step: and performing metal deposition on the lower surface of the device to form an anode (11).

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to a reverse conducting MOS (metal oxide semiconductor) grid-controlled thyristor and a manufacturing method thereof.

Background

With the continuous development of human society, the consumption of energy is also continuously increased, and the utilization rate of electric energy is required to be higher and higher while the output is increased. The realization of these requirements depends on the development of power electronics. The MOS gate controlled thyristor has also gained attention as a new power device.

The MOS grid Controlled Thyristor (MCT) is a semiconductor device with the advantages of power MOS and Thyristor, has the advantages of voltage control drive, no current saturation and high power density, and is very suitable for being applied to the high power field. Typical MCT devices do not have reverse turn-on capability, and in actual circuits, if normal operation is desired, a reverse diode is often connected in parallel to achieve reverse free-wheeling capability. Taking the pulse discharge circuit as an example, if the pulse discharge circuit does not have reverse conduction capability, a continuous pulse process cannot be realized, voltage stagnation is generated in the reverse direction, energy is difficult to be smoothly released, and device damage is easy to occur.

To solve this problem, RC-MCT (reverse construction MCT) has been proposed. Compared with the traditional MCT, the RC-MCT can be used in a pulse power circuit, a freewheeling diode does not need to be connected in parallel, and a reverse current leakage channel exists in the device, so that the advantages of realizing a reverse conductance function, reducing the complexity of a pulse circuit, facilitating circuit integration and reducing the cost are achieved on the basis of not increasing the unit cell width. However, the reverse conducting structure can cause the MCT to have a larger rebound voltage during the forward conducting process, which causes adverse effect on the forward conducting process, so that the rebound voltage of the RC-MCT is necessary to be reduced by improving the structure.

Disclosure of Invention

The invention aims to provide a reverse conducting MOS grid-controlled thyristor structure which improves snapback effect in the forward conducting process.

The technical scheme of the invention is as follows: a reverse conducting MOS gate-controlled thyristor is disclosed, as shown in FIG. 2, the cell junction comprises an anode structure, a drift region structure located on the upper surface of the anode structure, a planar gate structure located on the upper surface of the drift region, and a cathode structure; the drift region structure comprises an N-drift region 7 and an FS (field stop) layer 8, wherein the N-drift region 7 is positioned on the upper layer of the FS layer 8, the FS layer 8 is positioned below the gate structure, and the upper surface of the FS layer 8 is in contact with the N-drift region 7; the planar gate structure comprises a gate oxide layer 3 and a gate electrode 1, wherein the gate oxide layer 3 is positioned at one end of the upper surface of the N-drift region 7; the cathode structure comprises cathode metal 2, a P-type deep well region 4, an N well region 5 and a P well region 6, wherein the cathode metal 2 is positioned at the other end of the upper surface of the N-drift region 7, the cathode structure is characterized in that the P well region 6 is arranged on the upper layer of the N-drift region 7, the N well region 5 is arranged on the upper layer of the P well region 6, the P-type deep well region 4 is arranged on the upper layer of the N well region 5, and two ends of the upper surfaces of the P-type deep well region 4, the N well region 5 and the P well region 6 are respectively contacted with the silicon dioxide insulating layer 3 and the bottom of the cathode metal 2; the anode structure includes anode metal 11, N type anode region 10, P type anode region 9, the upper surface in P type anode region 9 contacts with the bottom of FS layer 8, the upper surface in N type anode region 10 contacts with the bottom in N-drift region 7, the side in N type anode region 10 contacts with P type anode region 9. The lower surface of the N-type anode region 10 and the lower surface of the P-type anode region 9 are in contact with the upper surface of the anode metal 11.

The grid structure of the reverse conducting MOS grid-controlled thyristor provided by the invention can be a plane grid or a groove grid.

The invention also provides a manufacturing method of the reverse conducting MOS grid-controlled thyristor, which comprises the following steps:

the first step is as follows: selecting an N-type silicon wafer as a substrate silicon wafer, namely an N-drift region 7 in the structure, firstly injecting N-type impurities into one end of the back surface of the N-drift region 7 through photoetching ions and performing junction pushing to form an N-type FS layer 8; as shown in fig. 5;

the second step is that: forming a gate oxide layer 3 on one end of the upper surface of the N-drift region 7 through thermal oxidation, depositing a layer of polycrystalline silicon/metal on the gate oxide layer 3, and etching to form a gate electrode 1; as shown in fig. 6;

the third step: injecting P-type impurities into the upper layer of the N-drift region 7 and pushing the P-type impurities to form a P well region 6 by utilizing an ion injection and high-temperature junction pushing process, wherein the upper surface of one end of the P well region 6 is in contact with the bottom of the gate oxide layer 3; as shown in fig. 7;

the fourth step: injecting N-type impurities into the upper layer of the P well region 6 by utilizing ion injection and high-temperature junction pushing processes to form an N well region 5, wherein the upper surface of one end of the N well region 5 is contacted with the bottom of the gate oxide layer 3; as shown in fig. 8;

the fifth step: injecting P-type impurities into the upper layer of the N-well region 5 by using ion injection and high-temperature junction pushing processes to form a P-type deep well region 4, wherein the upper surface of one end of the P-type deep well region 4 is in contact with the bottom of the gate oxide layer 8; as shown in fig. 9;

and a sixth step: depositing a BPSG insulating medium layer on the upper surface of the device, and etching an ohmic contact hole;

the seventh step: depositing metal on the other end of the upper surface of the N-drift region 7 to form cathode metal 2; the bottom of the cathode metal 2 is contacted with the upper surfaces of the other ends of the P well region 5, the N well region 6 and the P deep well region 7; as shown in fig. 10;

eighth step: depositing a passivation layer on the surface of the device;

the ninth step: injecting P-type impurities into the lower layer of the back N-type FS layer 8 through photoetching ions and carrying out ion activation to form a P-type anode region 9; as shown in fig. 11;

the tenth step: injecting N-type impurities into one end of the lower layer of the back N-drift region 7 through photoetching ions and activating the ions to form an N-type anode region 10; as shown in fig. 12;

the eleventh step: carrying out metal deposition on the lower surface of the device to form an anode 11;

the novel reverse conducting MOS grid-controlled thyristor has the beneficial effects that the snapback effect is inhibited by greatly improving the anode short-circuit resistance.

Drawings

FIG. 1 is a schematic diagram of a conventional planar gate type RC-MCT cell structure;

FIG. 2 is a schematic diagram of a planar grid type RC-MCT cell structure according to the present invention;

FIG. 3 is a schematic diagram of a conventional trench-gate type RC-MCT cell structure;

FIG. 4 is a schematic diagram of a cell structure of a trench-gate type RC-MCT cell according to the present invention;

FIG. 5 is a schematic structural diagram of the N-type FS layer 8 formed in the manufacturing process flow of the present invention;

FIG. 6 is a schematic structural diagram of a gate electrode formed by depositing a polysilicon/metal layer on the gate oxide layer and etching the polysilicon/metal layer after forming gate oxide in the manufacturing process flow of the present invention;

FIG. 7 is a schematic structural diagram of a P-well region formed by injecting P-type impurities into a plug-in junction in the process flow of the present invention;

FIG. 8 is a schematic structural diagram of an N-well region formed by ion implantation of N-type impurity push-junction in the process flow of the present invention;

FIG. 9 is a schematic structural diagram of a P deep well region formed by injecting P-type impurity push-knot ions in the process flow of the present invention;

FIG. 10 is a schematic view of the front side metallization of the fabrication process flow of the present invention;

FIG. 11 is a schematic structural diagram of a P-type anode region 9 formed by implanting P-type impurities to the back surface and performing ion activation in the process flow of the present invention;

fig. 12 is a schematic structural diagram of the manufacturing process flow of the present invention after injecting N-type impurities to the back surface and performing ion activation to form the N-type anode region 10;

FIG. 13 is a graph showing a comparison of forward turn-on characteristics of the present invention and conventional RC-MCT devices;

FIG. 14 is a graph showing the breakdown characteristics of the RC-MCT device of the present invention in comparison with conventional RC-MCT devices;

Detailed Description

The technical scheme of the invention is described in detail in the following with the accompanying drawings:

the invention provides a reverse conducting MOS (metal oxide semiconductor) gated thyristor, which has a structural schematic diagram shown in figure 2 and comprises a gate electrode 1, a metalized cathode 2, a gate oxide layer 3, a P deep well 4, an N well 5, a P well 6, an N drift region 7, an FS layer 8, a P anode region 9, an N anode region 10 and a metalized anode 11. The P trap 6 is positioned at the top of the drift region 7, the N trap 5 is positioned in the P trap 6, the P deep trap 4 is positioned in the N trap 5, the gate oxide layer 3 is positioned on the surfaces of the P deep trap 4, the N trap 5, the P trap 6 and the N drift region 7, the gate electrode 1 is positioned on the surface of the gate oxide layer 3, and the metalized cathode 2 covers the P deep trap 4, the N trap 5 and a part of the P trap 6. The lower surface of the N drift region 7 is provided with an FS layer 8 and an N anode region 10, the lower surface of the FS layer 8 is a P-type anode region 9, and the upper part of a metallized anode 11 is in contact with the N anode region 10 and the P-type anode region 9.

The gate structure of the reverse conducting type MOS gated thyristor provided by the invention can be a planar gate or a trench gate, the structure of the reverse conducting type MOS gated thyristor cell with the planar gate is shown in fig. 2, and the structure of the reverse conducting type MOS gated thyristor cell with the trench gate is shown in fig. 4.

When a positive voltage is applied to the gate 1 of the device, an N-type channel is generated on the surface of the P-type base region 6 below the gate 1. When the anode current is small, electrons in the N-well region 5 are injected into the N-type drift region 7 and finally flow out through the N-type anode region 10, and the path is only electron conduction. With the increase of the anode current, the voltage drop formed on the PN junction formed by the P-type anode region 9 and the N-type FS layer 8 is higher than the turn-on voltage, the PN junction is turned on, the P-type anode region 9 injects a large number of holes into the N-drift region 7, the N-drift region 7 generates a conductivity modulation effect, the on-resistance is greatly reduced, and at this time, a current-voltage relationship curve of the device has a rebound phenomenon.

Compared with the conventional RC-MCT, the invention increases the resistance above the P-type anode region by reducing the width of the FS layer, so that the rebound voltage of the device in the forward conduction process is reduced, and meanwhile, the forward withstand voltage of the device is not reduced.

Figure 13 is a graph comparing the forward turn-on characteristics of the present invention and a conventional RC-MCT device. As can be seen from the figure, the rebound voltage of the conventional RC-MCT is 74.3V, while the rebound voltage of the present invention is 57.9V, and compared with the conventional structure, the rebound voltage of the present invention is reduced by 22%, and the result fully shows that the snapback effect during the forward conduction process of the device is obviously improved by the present invention.

Figure 14 is a graph showing the breakdown characteristics of the inventive MCT device compared to a conventional MCT device. As can be seen from the figure, the two curves substantially coincide, indicating that the voltage resistance of the present invention is unchanged compared to the conventional RC-MCT device, which also indicates that the device structure of the present invention is changed without sacrificing the forward blocking capability of the device.