阅读说明：本技术 用于有源移相器中的功耗降低的方法和电路 (Method and circuit for power consumption reduction in active phase shifters ) 是由 A.吉恩 A.辛格 于晓华 孙祥源 吕思壮 T.张 于 2021-05-31 设计创作，主要内容包括：提供了一种电子电路和方法。该电子电路包括：同相(I)正交(Q)放大器,包括I共源共栅分支和Q共源共栅分支,IQ放大器配置为接收差分输入信号和控制信号、基于控制信号控制I共源共栅分支中的栅极电压和Q共源共栅分支中的栅极电压、用I共源共栅分支生成I输出信号、以及用Q共源共栅分支生成Q输出信号；以及正交耦合器,配置为执行I输出信号和Q输出信号的正交求和以及生成最终的相移输出。(An electronic circuit and method are provided. The electronic circuit includes: an in-phase (I) quadrature (Q) amplifier including an I-cascode branch and a Q-cascode branch, the IQ amplifier configured to receive a differential input signal and a control signal, control a gate voltage in the I-cascode branch and a gate voltage in the Q-cascode branch based on the control signal, generate an I output signal with the I-cascode branch, and generate a Q output signal with the Q-cascode branch; and a quadrature coupler configured to perform a quadrature summation of the I and Q output signals and generate a final phase shifted output.)

1. An electronic circuit, comprising:

an in-phase, I-quadrature, Q, amplifier comprising an I-cascode branch and a Q-cascode branch, the IQ amplifier configured to:

receiving a differential input signal and a control signal;

controlling a gate voltage in the I-cascode branch and a gate voltage in the Q-cascode branch based on a control signal;

generating an I output signal with the I cascode branch; and

generating a Q output signal with the Q cascode branch; and

a quadrature coupler configured to:

performing a quadrature summation of the I output signal and the Q output signal; and

generating a final phase shifted output.

2. The electronic circuit of claim 1, wherein the I-cascode branch comprises a first cascode arm and a second cascode arm.

3. The electronic circuit of claim 2, wherein the first cascode arm includes a first cascode transistor and a second cascode transistor, and the second cascode arm includes a third cascode transistor and a fourth cascode transistor.

4. The electronic circuit of claim 3, wherein the first, second, third, and fourth cascode transistors process an I-based control signal in the received control signal.

5. The electronic circuit of claim 3, wherein the first, second, third, and fourth cascode transistors are segmented and weighted to generate a relative I: Q ratio.

6. The electronic circuit of claim 1, wherein the Q-cascode branch comprises a first cascode arm and a second cascode arm.

7. The electronic circuit of claim 6, wherein the first cascode arm includes a first cascode transistor and a second cascode transistor, and the second cascode arm includes a third cascode transistor and a fourth cascode transistor.

8. The electronic circuit of claim 7, wherein the first, second, third, and fourth cascode transistors process a Q-based control signal in the received control signal.

9. The electronic circuit of claim 7, wherein the first, second, third, and fourth cascode transistors are segmented and weighted to generate a relative I: Q ratio.

10. The electronic circuit of claim 1, further comprising a digital logic block configured to generate the control signal based on a 4-bit digital input.

11. A method, comprising:

receiving a differential input signal and a control signal with an in-phase I-quadrature Q amplifier comprising an I-cascode branch and a Q-cascode branch;

controlling a gate voltage in the I-cascode branch and a gate voltage in the Q-cascode branch based on a control signal;

generating an I output signal with the I cascode branch;

generating a Q output signal with the Q cascode branch;

performing quadrature summation of the I output signal and the Q output signal with a quadrature coupler; and

the final phase shifted output is generated with a quadrature coupler.

12. The method of claim 11, wherein an I-cascode branch includes a first cascode arm and a second cascode arm.

13. The method of claim 12, wherein the first cascode arm includes a first cascode transistor and a second cascode transistor, and the second cascode arm includes a third cascode transistor and a fourth cascode transistor.

14. The method of claim 13, wherein processing a control signal further comprises processing an I-based control signal in the received control signal with a first cascode transistor, a second cascode transistor, a third cascode transistor, and a fourth cascode transistor.

15. The method of claim 13, wherein the first, second, third, and fourth cascode transistors are segmented and weighted to generate a relative I: Q ratio.

16. The method of claim 11, wherein the Q-cascode branch comprises a first cascode arm and a second cascode arm.

17. The method of claim 16, wherein the first cascode arm includes a first cascode transistor and a second cascode transistor, and the second cascode arm includes a third cascode transistor and a fourth cascode transistor.

18. The method of claim 17, wherein processing a control signal further comprises processing a Q-based control signal in the received control signal with a first cascode transistor, a second cascode transistor, a third cascode transistor, and a fourth cascode transistor.

19. The method of claim 17, wherein the first, second, third, and fourth cascode transistors are segmented and weighted to generate a relative I: Q ratio.

20. The method of claim 11, further comprising generating a control signal with a digital logic block based on a 4-bit digital input.

Technical Field

The present disclosure relates generally to active phase shifters with reduced power consumption.

Background

Directional communication at millimeter wave frequencies is a key impetus for deploying fifth generation (5G) cellular technology. Phased arrays are used to implement these directional links.

Antennas in a phased array may steer the direction of a radiation beam when driven with a particular combination of amplitude and phase. One of the key blocks for implementing such a system is the phase shifter. The goal of the phase shifter is to produce a digitally programmable output phase given a fixed phase input signal while ensuring that the gain variation between these different phase states is as small as possible. Phase shifter designs can be broadly categorized as active phase shifter designs and passive phase shifter designs. Active phase shifters provide area/integration and loss advantages over passive phase shifters, respectively, as the number of antenna elements increases and phase resolution becomes lower, while having the disadvantage of increased power consumption.

Disclosure of Invention

According to one embodiment, an electronic circuit comprises: an in-phase (I) quadrature (Q) amplifier including an I-cascode branch and a Q-cascode branch, the IQ amplifier configured to receive a differential input signal and a control signal, control a gate voltage in the I-cascode branch and a gate voltage in the Q-cascode branch based on the control signal, generate an I output signal with the I-cascode branch, and generate a Q output signal with the Q-cascode branch; and a quadrature coupler configured to perform a quadrature summation of the I and Q output signals and generate a final phase shifted output.

According to one embodiment, a method comprises: receiving a differential input signal and a control signal with an IQ amplifier comprising an I-cascode branch and a Q-cascode branch, controlling a gate voltage in the I-cascode branch and a gate voltage in the Q-cascode branch based on the control signal, generating an I-output signal with the I-cascode branch, generating a Q-output signal with the Q-cascode branch, performing a quadrature summation of the I-output signal and the Q-output signal with a quadrature coupler, and generating a final phase-shifted output with the quadrature coupler.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a diagram of a conventional active phase shifter;

fig. 2 shows a diagram of an active phase shifter according to an embodiment;

fig. 3 shows a diagram of a 4-bit active phase shifter according to an embodiment;

fig. 4 shows a flow diagram for a 4-bit active phase shifter according to an embodiment; and

FIG. 5 illustrates a block diagram of an electronic device in a network environment, in accordance with one embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the same elements will be denoted by the same reference numerals although they are shown in different drawings. In the following description, only specific details such as detailed configurations and components are provided to assist in an overall understanding of embodiments of the present disclosure. Thus, it should be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the disclosure. Moreover, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of functions in the present disclosure, and may be different according to a user, a user intention, or a habit. Therefore, the definition of the terms should be determined based on the contents throughout the specification.

The present disclosure may have various modifications and various embodiments, and embodiments among them are described in detail below with reference to the accompanying drawings. It should be understood, however, that the disclosure is not limited to these embodiments, but includes all modifications, equivalents, and alternatives falling within the scope of the disclosure.

Although terms including ordinal numbers such as first, second, etc., may be used to describe various elements, structural elements are not limited by the terms. The terminology is used only to distinguish one element from another. For example, a first structural element may be termed a second structural element without departing from the scope of the present disclosure. Similarly, the second structural element may also be referred to as the first structural element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated items.

The terminology used herein is for the purpose of describing various embodiments of the disclosure only and is not intended to be limiting of the disclosure. Singular forms are intended to include the plural unless the context clearly indicates otherwise. In the present disclosure, it is to be understood that the terms "comprises" or "comprising" mean the presence of the features, numbers, steps, operations, structural elements, parts, or combinations thereof, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, structural elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein have the same meaning as understood by those skilled in the art to which this disclosure belongs. Terms such as terms defined in a general dictionary will be construed to have the same meaning as the context in the related art, and will not be construed to have an idealized or overly formal meaning unless expressly so defined herein.

The electronic device according to one embodiment may be one of various types of electronic devices. The electronic device may comprise, for example, a portable communication device (e.g., a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to one embodiment of the present disclosure, the electronic apparatus is not limited to those described above.

The terminology used in the present disclosure is not intended to be limiting of the disclosure, but is intended to include various changes, equivalents, or alternatives to the corresponding embodiments. With respect to the description of the figures, like reference numerals may be used to refer to like or related elements. The singular form of a noun corresponding to an item may include one or more things unless the relevant context clearly dictates otherwise. As used herein, each of the phrases such as "a or B," "at least one of a and B," "at least one of a or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B or C" may include all possible combinations of the items listed together in the respective one of the phrases. As used herein, terms such as "1 st," "2 nd," "first," and "second" may be used to distinguish a corresponding component from another component, but are not intended to limit the components in other respects (e.g., importance or order). It is intended that if an element (e.g., a first element) is referred to as being "coupled to," "connected to," or "connected to" another element (e.g., a second element), with or without the terms "operatively" or "communicatively coupled to" the other element (e.g., the second element), it indicates that the element may be directly coupled (e.g., wired), wirelessly, or via a third element to the other element.

As used herein, the term "module" may include units implemented in hardware, software, or firmware, and may be used interchangeably with other terms (e.g., "logic," "logic block," "portion," and "circuitry"). A module may be a single integral component or a minimal unit or portion thereof adapted to perform one or more functions. For example, according to one embodiment, the modules may be implemented in the form of Application Specific Integrated Circuits (ASICs).

Fig. 1 shows a diagram of a conventional active phase shifter 100. The active phase shifter 100 includes an in-phase (I) Variable Gain Amplifier (VGA) "AI" 102, a corresponding impedance Matching Network (MN)104, a quadrature (Q) VGA "AQ" 106, a corresponding impedance MN 108, and an I/Q generator summing circuit 110 that receives the outputs of the MNs 104 and 108 and performs quadrature addition.

Based on phase range and phase stepLong, should realize different A_I:A_QThe ratio is fed to an I/Q generator 110 that performs quadrature vector summation. For A_I:A_QThere are two requirements: (1) "Arctan (A)_Q/A_I) "should be close to (i.e., the target phase value is below the difference of the phase error target) the target phase value to be generated; and (2) "(A)_I^2+A_Q2) 0.5 "should be approximately constant (i.e., much smaller than the gain error target) at all phase states. Thus, as shown in fig. 1, the I VGA102 and the Q VGA106 are identical.

The present systems, methods, and circuits may be implemented in an active phase shifter to reduce power consumption. Fig. 2 shows a diagram of an active phase shifter 200 according to an embodiment. The active phase shifter 200 includes a single combined IQ amplifier 202, MN 204 for I output, MN 206 for Q output, and I/Q generator summing circuit 208. The IQ amplifier 202 may comprise a single differential transconductor instead of two separate differential transconductors as in the conventional case of fig. 1 to generate the currents routed to the separate digitally programmable cascode branches to produce the required a_I:A_QAnd (4) the ratio.

The active phase shifter 200 provides various advantages. The active phase shifter 200 utilizes a single differential transconductor to generate signal currents that are routed to separate digital programmable cascode branches whose outputs are used as inputs to an I/Q generator summing circuit. Because conventional active phase shifters use separate amplifiers with two differential transconductors, this topology has lower current consumption while producing the same output amplitude. The cascode devices are segmented and then weighted to achieve a 4-bit phase shift in the active phase shifter 200. Conventional active phase shifters are non-segmented, and as a result only 3-bit phase shifts can be achieved.

The active phase shifter 200 provides reduced power consumption compared to conventional phase shifters. The active phase shifter 200 also has reduced input gate loading/capacitance due to the use of a single differential transconductor, compared to an architecture in which both the I and Q paths are implemented by separate amplifiers. The reduced load results in higher gain/lower power consumption of the driver stage. This advantage is significant at millimeter wave frequencies, where gate capacitance can have significant resistive losses due to lossy lower level metal/polysilicon gate wiring, especially for larger width devices. The area required to implement the active phase shifter 200 core is at least 30% less than conventional active phase shifters, resulting in a more compact layout and thus improved ease of integration.

The active phase shifter is implemented as a 4-bit 360 degree phase shifter (i.e., 360/2^4 ^ 22.5 degree phase steps). Regardless of the architecture choice of the phase shifter, the I/Q amplitude ratios required by the I/Q generator for a 4-bit phase shift are 1:0(0 degrees), 1:0.4(22.5 degrees), 0.7:0.7(45 degrees), 0.4:1(67.5 degrees), and 0:1(90 degrees).

To make the most efficient use of DC current, power consumption may be limited by equation (1) across all different phase states, i.e., pairs of (I, Q) where Imax and Qmax are the maximum magnitudes required in the I and Q paths across all phase states.

max(abs(I/Imax)+abs(Q/Qmax))(1)

For the case of 4-bit phase shift, if the I and Q amplitudes are summed for 0/22.5/45/67.5/90, as shown in Table 1, it can be seen that equation (1) is 1.4.

TABLE 1

Thus, if the I and Q currents are generated by a single differential transconductor and then rerouted to two separate I/Q transformers based on the required relative ratio, a power reduction is achieved. The current consumption of active phase shifter 200 can be limited to 1.4 compared to 2X in the case of the conventional design approach that uses two separate amplifiers without sacrificing any gain and still produce the required phase step.

Fig. 3 shows a diagram of a 4-bit active phase shifter 300 according to an embodiment. The active phase shifter 300 includes a digital logic block 302 that generates four sets of control signals: i <3:0>, Ibar <3:0>, Q <3:0> and Qbar <3:0 >. I <3:0> and Ibar <3:0> are control signals (e.g., I-based control signals) for the cascode devices in the I signal path, and Q <3:0> and Qbar <3:0> are control signals (e.g., Q-based control signals) for the cascode devices in the Q signal path. The active phase shifter 300 includes a single differential transconductor receiving a differential voltage input 303. The I-cascode branch 304 produces an I signal output 332 and the Q-cascode branch 306 produces a Q signal output 334. The I-cascode branch 304 includes a first cascode arm 308 and a second cascode arm 310. The first cascode leg 308 includes a first segmented and weighted cascode transistor 316 and a second segmented and weighted cascode transistor 318. The second cascode arm 320 includes a third segmented and weighted cascode transistor 320 and a fourth segmented and weighted cascode transistor 322. The Q-cascode branch 306 includes a first cascode arm 312 and a second cascode arm 314. The first cascode leg 312 includes a first segmented and weighted cascode transistor 324 and a second segmented and weighted cascode transistor 326. The second cascode arm 314 includes a third segmented and weighted cascode transistor 328 and a fourth segmented and weighted cascode transistor 330. Further, the drain outputs of the segmented and weighted cascode transistor 318 and the segmented and weighted cascode transistor 320 are connected to the differential side of the io output balun with inverted polarity with respect to 316 and 322. Likewise, the drain outputs of segmented and weighted cascode transistor 326 and segmented and weighted cascode transistor 328 are connected to the differential side of the Q output balun with inverted polarities with respect to 324 and 330. The I-cascode branch 304 produces a differential output that is converted to a single-ended I output 332 with a balun, and the Q-cascode branch 306 produces a differential output that is converted to a single-ended Q output 334 with a balun. The I and Q outputs 332, 334 are processed by a tuned quadrature coupler 336, which quadrature coupler 336 quadrature vector sums to produce a final phase shifted output.

As shown in fig. 3, the active phase shifter 300 receives a differential input signal 303 and a single 4-bit digital control signal PS <3:0> that selects 1 out of 16 possible phase shifted states. Digital logic block 302 is used to generate four sets of 4-bit control signals to control the gates of the I and Q cascode transistors according to the desired resulting phase shift state. Digital logic block 302 may include a lookup table containing the on/off settings of each cascode transistor for each phase state.

In each I/Q differential cascode arm (arms 308 and 310 of I-cascode branch 304 and arms 312 and 314 of Q-cascode branch 306), there are two sets of segmented and weighted cascode transistors controlled by I <3:0>/Q <3:0> and Ibar/Qbar <3:0>, respectively. For example, cascode transistor 316 is controlled by I <3:0>, cascode transistor 318 is controlled by Ibar <3:0>, cascode transistor 320 is controlled by Ibar <3:0>, and cascode transistor 322 is controlled by I <3:0 >. Likewise, cascode transistor 324 is controlled by Q <3:0>, cascode transistor 326 is controlled by Qbar <3:0>, cascode transistor 328 is controlled by Qbar <3:0>, and cascode transistor 330 is controlled by Q <3:0 >. The two sets of control signals (i.e., I/Ibar and Q/Qbar) are used because it is necessary to generate I/Q outputs of opposite polarity to achieve full 360 degree phase shift capability.

Each cascode transistor may be segmented and weighted (4:3:2:1) to produce the desired relative I: Q ratio. If the same number of two sets of cascode devices, controlled by I/Q and Ibar/Qbar, are turned on at the same time, there is no net output signal because the signal currents are cancelled in the primary winding of the transformer connected at the drain of the cascode transistors. This cancellation of a portion of the signal current is used in the 0/90/180/270 degree phase state, where only the I or Q (or I or Q of inverted polarity) signal is needed at the output.

Fig. 4 shows a flow diagram 400 for a 4-bit active phase shifter according to an embodiment. At 402, an active phase shifter receives a differential input and four control signals. The active phase shifter may receive a differential input as a differential voltage input (which is converted to a current through a differential transconductor) and a 4-bit control signal. The differential voltage input may be converted to a current through the differential transconductor, and the 4-bit control signal may be converted (e.g., by the digital block 302) to a derivative set of four 4-bit control signals I <3:0>, Ibar <3:0>, Q <3:0>, and Qbar <3:0> as described above.

At 404, the active phase shifter sets a control signal to control the cascode transistors in the cascode arm. The control signal may control the gates of the cascode transistors in the I/Q differential cascode arm. These gates are controlled according to the desired phase shift setting given by the 4-bit control input. Each I/Q cascode branch has two arms, each arm may include two cascode transistors that may be further segmented and weighted. In the first cascode arm of the I-cascode branch, the gates of the first segmented and weighted cascode transistors may be set by I <3:0> and the gates of the second segmented and weighted cascode transistors may be set by Ibar <3:0 >. In the second cascode arm of the I-cascode branch, the gates of the third segmented and weighted cascode transistor may be set by Ibar <3:0> and the gates of the fourth segmented and weighted cascode transistor may be set by I <3:0 >. The drain outputs of the second and third segmented and weighted cascode transistors may be connected to the differential side of the io output balun with an inverted polarity relative to the drain outputs of the first and fourth segmented and weighted cascode transistors. In the first cascode arm of the Q-cascode branch, the gates of the first segmented and weighted cascode transistors may be set by Q <3:0>, and the gates of the second segmented and weighted cascode transistors may be set by Qbar <3:0 >. In the second cascode arm of the Q-cascode branch, the gates of the third segmented and weighted cascode transistor may be set by Qbar <3:0>, and the gates of the fourth segmented and weighted cascode transistor may be set by Q <3:0 >. The drain outputs of the second and third segmented and weighted cascode transistors may be connected to the differential side of the Q output balun with an inverted polarity relative to the drain outputs of the first and fourth segmented and weighted cascode transistors. .

At 406, the active phase shifter generates an I output signal with the I-cascode branch and a Q output signal with the Q-cascode branch based on the output from the cascode transistors. At 408, the active phase shifter performs quadrature vector summation of the I and Q output signals (with the I/Q generator/summation circuit) to generate the final desired phase shifted output signal. At 410, the active phase shifter along with the quadrature coupler generates a final phase shifted output.

As an additional or alternative embodiment, different relative weights of the cascode transistors are possible given the phase shifter step size, resulting in slightly different systematic phase errors between the phase states.

Another additional or alternative embodiment includes different segmentation and weighting for the cascode transistors based on different target I: Q weighting ratios needed to achieve higher or lower phase shift step sizes. The concept of using a single combined I/Q amplifier core is possible, but the power saving advantage may be different from that of a 4-bit active phase shifter.

Fig. 5 illustrates a block diagram of an electronic device 501 in a network environment 500, in accordance with one embodiment. Referring to fig. 5, an electronic device 501 in a network environment 500 may communicate with another electronic device 502 via a first network 598 (e.g., a short-range wireless communication network) or may communicate with another electronic device 504 or a server 508 via a second network 599 (e.g., a long-range wireless communication network). Electronic device 501 may also communicate with electronic device 504 via server 508. The electronic device 501 may include a processor 520, a memory 530, an input device 550, a sound output device 555, a display device 560, an audio module 570, a sensor module 576, an interface 577, a haptic module 579, a camera module 580, a power management module 588, a battery 589, a communication module 590, a Subscriber Identity Module (SIM)596, or an antenna module 597. In one embodiment, at least one of these components (e.g., the display device 560 or the camera module 580) may be omitted from the electronic device 501, or one or more other components may be added to the electronic device 501. In one embodiment, some of the components may be implemented as a single Integrated Circuit (IC). For example, a sensor module 576 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 560 (e.g., a display).

Processor 520 may run, for example, software (e.g., program 540) to control at least one other component (e.g., a hardware or software component) of electronic device 501 coupled to processor 520, and may perform various data processing or calculations. As at least part of the data processing or computation, the processor 520 may load commands or data received from another component (e.g., the sensor module 576 or the communication module 590) into the volatile memory 532, process the commands or data stored in the volatile memory 532, and store the resulting data in the non-volatile memory 534. Processor 520 may include a main processor 521 (e.g., a Central Processing Unit (CPU) or an Application Processor (AP)) and an auxiliary processor 523 (e.g., a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a sensor hub processor, or a Communications Processor (CP)) that may operate independently of main processor 521 or may operate in conjunction with main processor 521.

The auxiliary processor 523 may control at least some of the functions or states associated with at least one of the components of the electronic device 501 (e.g., the display device 560, the sensor module 576, or the communication module 590) in place of the main processor 521 when the main processor 521 is in an inactive (e.g., sleep) state, or control at least some of the functions or states associated with at least one of the components of the electronic device 501 (e.g., the display device 560, the sensor module 576, or the communication module 590) with the main processor 521 when the main processor 521 is in an active (e.g., running an application). According to one embodiment, the auxiliary processor 523 (e.g., ISP or CP) may be implemented as part of another component (e.g., camera module 580 or communication module 590) that is functionally related to the auxiliary processor 523.

The memory 530 may store various data used by at least one component of the electronic device 501 (e.g., the processor 520 or the sensor module 576). The various data may include, for example, software (e.g., program 540) and input data or output data for commands associated therewith. Memory 530 may include volatile memory 532 or nonvolatile memory 534.

Program 540 may be stored in memory 530 as software and may include, for example, an Operating System (OS)542, middleware 544, or applications 546.

Input device 550 may receive commands or data from outside of electronic device 501 (e.g., a user) to be used by other components of electronic device 501 (e.g., processor 520). The input device 550 may include, for example, a microphone, a mouse, or a keyboard.

The sound output device 555 may output a sound signal to the outside of the electronic device 501. The sound output device 555 may include, for example, a speaker or a receiver. The speaker may be used for general purposes such as playing multimedia or recording, and the receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented as a separate or part of the speaker.

The display device 560 may visually provide information to an exterior (e.g., user) of the electronic device 501. The display device 560 may include, for example, a display, a holographic device, or a projector, and control circuitry for controlling a respective one of the display, holographic device, and projector. According to one embodiment, the display device 560 may include touch circuitry adapted to detect a touch or sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of a force caused by a touch.

The audio module 570 may convert sound into electrical signals and vice versa. According to one embodiment, the audio module 570 may obtain sound via the input device 550 or output sound via the sound output device 555 or headphones of the external electronic device 502 coupled directly (e.g., wired) or wirelessly with the electronic device 501.

The sensor module 576 can detect an operational state (e.g., power or temperature) of the electronic device 501 or an environmental state (e.g., state of a user) external to the electronic device 501 and then generate an electrical signal or data value corresponding to the detected state. The sensor module 576 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an Infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface 577 may support one or more specified protocols for coupling the electronic device 501 with the external electronic device 502 directly (e.g., wired) or wirelessly. According to one embodiment, the interface 577 may include, for example, a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface.

The connection end 578 may include a connector via which the electronic device 501 may be physically connected with the external electronic device 502. According to one embodiment, the connection end 578 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

The haptic module 579 may convert an electrical signal into a mechanical stimulus (e.g., vibration or motion) or an electrical stimulus recognizable by a user via a sense of touch or kinesthesia. According to one embodiment, the haptic module 579 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

The camera module 580 may capture still images or moving images. According to one embodiment, the camera module 580 may include one or more lenses, image sensors, ISPs, or flash lights.

The power management module 588 may manage power supplied to the electronic device 501. The power management module 588 may be implemented, for example, as at least part of a Power Management Integrated Circuit (PMIC).

The battery 589 may provide power to at least one component of the electronic device 501. According to one embodiment, battery 589 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

The communication module 590 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 501 and an external electronic device (e.g., the electronic device 502, the electronic device 504, or the server 508), and performing communication via the established communication channel. The communication module 590 may include one or more CPs operable independently of the processor 520 (e.g., AP) and supporting direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 590 may include a wireless communication module 592 (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module 594 (e.g., a Local Area Network (LAN) communication module or a Power Line Communication (PLC) module). These various types of communication modules may be implemented as a single component (e.g., a single IC) or as multiple components (e.g., multiple ICs) separate from one another, the wireless communication module 592 may identify and authenticate the electronic device 501 in a communication network, such as the first network 598 or the second network 599, using user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the subscriber identity module 596.

The antenna module 597 may transmit signals or power to or receive signals or power from outside of the electronic device 501 (e.g., an external electronic device). According to one embodiment, the antenna module 597 may include one or more antennas, whereby at least one antenna suitable for a communication scheme used in a communication network, such as the first network 598 or the second network 599, may be selected, for example, by the communication module 590 (e.g., the wireless communication module 592). Signals or power may then be transmitted or received between the communication module 590 and the external electronic device via the selected at least one antenna.

At least some of the above components may be coupled to each other and communicate signals (e.g., commands or data) communicatively therebetween via an inter-peripheral communication scheme (e.g., bus, General Purpose Input Output (GPIO), Serial Peripheral Interface (SPI), or Mobile Industry Processor Interface (MIPI)).

According to one embodiment, commands or data may be sent or received between the electronic device 501 and the external electronic device 504 via the server 508 coupled with the second network 599. Each of electronic devices 502 and 504 may be the same type of device or a different type of device as electronic device 501. All or some of the operations to be performed at electronic device 501 may be performed at one or more of external electronic devices 502, 504, or 508. For example, if the electronic device 501 should automatically perform a function or service or should perform a function or service in response to a request from a user or another device, the electronic device 501 may request the one or more external electronic devices to perform at least part of the function or service instead of performing the function or service, or the electronic device 501 may request the one or more external electronic devices to perform at least part of the function or service in addition to performing the function or service. The one or more external electronic devices that receive the request may perform the requested at least part of the functions or services or perform additional functions or additional services related to the request and transmit the result of the execution to the electronic device 501. The electronic device 501 may provide the result as at least a partial reply to the request with or without further processing of the result. For this purpose, for example, cloud computing technology, distributed computing technology, or client-server computing technology may be used.

One embodiment may be implemented as software (e.g., program 540) including one or more instructions stored in a storage medium (e.g., internal memory 536 or external memory 538) readable by a machine (e.g., electronic device 501). For example, under control of the processor, the processor of electronic device 501 may invoke and execute at least one of the one or more instructions stored in the storage medium with or without the use of one or more other components. Accordingly, the machine may be operable to perform at least one function in accordance with the invoked at least one instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" means that the storage medium is a tangible device and does not include a signal (e.g., an electromagnetic wave), but the term does not distinguish between data being stored semi-permanently in the storage medium and data being stored temporarily in the storage medium.

According to one embodiment, the method of the present disclosure may be included and provided in a computer program product. The computer program product may be used as a product for conducting a transaction between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be read via an application Store (e.g., Play Store)^TM) The computer program product is published (e.g. downloaded or uploaded) online, or may be distributed (e.g. downloaded or uploaded) directly between two user devices (e.g. smartphones). At least part of the computer program product may be temporarily generated if it is published online, or at least part of the computer program product may be at least temporarily stored in a machine readable storage medium, such as a memory of a manufacturer's server, a server of an application store, or a forwarding server.

According to one embodiment, each of the above components (e.g., modules or programs) may comprise a single entity or multiple entities. One or more of the above components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as the corresponding one of the plurality of components performed the one or more functions prior to integration. Operations performed by a module, program, or another component may be performed sequentially, in parallel, repeatedly, or in a heuristic manner, or one or more of the operations may be performed in a different order, or omitted, or one or more other operations may be added.

While certain embodiments of the present disclosure have been described in the detailed description of the disclosure, the disclosure may be modified in various forms without departing from the scope of the disclosure. Accordingly, the scope of the present disclosure should be determined not only based on the described embodiments, but also based on the appended claims and their equivalents.