阅读说明：本技术 一种自适应控制电路及控制方法 (Self-adaptive control circuit and control method ) 是由 张俏 李新磊 于 2021-08-04 设计创作，主要内容包括：本发明提供了一种自适应控制电路及控制方法,应用于同步整流电路,所述控制方法包括：检测当前开关周期内所述同步整流电路的同步整流管最小导通时间结束后的漏源电压,以及根据检测的所述同步整流管的漏源电压调整所述同步整流管下一开关周期的最小导通时间。使得同步整流管在干扰信号持续时间较小时,采用小的最小导通时间；在干扰信号持续时间较长时,采用长的最小导通时间。(The invention provides a self-adaptive control circuit and a control method, which are applied to a synchronous rectification circuit, wherein the control method comprises the following steps: and detecting the drain-source voltage of the synchronous rectifier tube after the minimum on-time of the synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished, and adjusting the minimum on-time of the next switching period of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube. When the duration of the interference signal is shorter, the synchronous rectifier tube adopts the minimum conduction time; when the duration of the interference signal is long, a long minimum on-time is used.)

1. An adaptive control method applied to a synchronous rectification circuit, comprising:

detecting a drain-source voltage of the synchronous rectifier tube of the synchronous rectifier circuit after the minimum on-time is over in the current switching period, and

and adjusting the minimum conduction time of the next switching period of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube.

2. The method of claim 1, wherein adjusting the minimum on-time of the next switching cycle of the synchronous rectifier based on the detected drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum on-time of the next switching period.

3. The method of claim 2, wherein adjusting the minimum on-time of the next switching cycle of the synchronous rectifier based on the detected drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, reducing the minimum on-time of the next switching period.

4. The method of claim 1, wherein adjusting the minimum on-time of the next switching cycle of the synchronous rectifier based on the detected drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum on-time of the next switching period.

5. The method of claim 3,

when the detected drain-source voltage of the synchronous rectifier tube is not larger than the first threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and adding a second time; and

and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and reducing the second time.

6. The method of claim 1, wherein detecting a drain-source voltage within a current switching cycle that is delayed from an end of a minimum on-time of the synchronous rectifier by a first end of time.

7. The method of claim 6, wherein the first time is set to be not less than a sum of a logic delay time inside a chip, a driving pull-down time, and a turn-off time of the synchronous rectifier tube.

8. The method of claim 6, wherein the first time is set to be not less than a sum of a logic delay time inside a chip, a driving pull-down time, a turn-off time of the synchronous rectifier, and a charging time of a parasitic capacitance of the synchronous rectifier.

9. The method of claim 2, wherein the first threshold voltage is determined by a threshold voltage at which a body diode of the synchronous rectifier tube conducts.

10. The method of claim 9, wherein the first threshold voltage is set less than zero.

11. The method of claim 3, wherein the second threshold voltage is substantially greater than a drain-source voltage at a turn-off time of the synchronous rectifier.

12. An adaptive control circuit applied to a synchronous rectification circuit, comprising:

the voltage detection circuit is configured to detect drain-source voltage after the minimum conduction time of a synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished; and

the adjusting circuit is configured to adjust the minimum conducting time of the next switching period of the synchronous rectifying tube according to the drain-source voltage of the synchronous rectifying tube.

13. The adaptive control circuit of claim 12, wherein adjusting the minimum on-time of the synchronous rectifier for a next switching cycle based on the drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum on-time of the next switching period.

14. The adaptive control circuit of claim 13, wherein adjusting the minimum on-time of the synchronous rectifier for a next switching cycle based on the drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, reducing the minimum on-time of the next switching period.

15. The adaptive control circuit of claim 12, wherein adjusting the minimum on-time of the synchronous rectifier for a next switching cycle based on the drain-source voltage of the synchronous rectifier comprises:

and when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum on-time of the next switching period.

16. The adaptive control circuit of claim 14,

when the detected drain-source voltage of the synchronous rectifier tube is not larger than the first threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and adding a second time; and

and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and reducing the second time.

17. The adaptive control circuit of claim 12, wherein the adjustment circuit comprises:

the comparison circuit inputs the drain-source voltage and the reference voltage of the synchronous rectifier tube and outputs a comparison signal;

the logic circuit receives the comparison signal and outputs a counting instruction; and

and the minimum on-time generating circuit receives the counting instruction and outputs a signal representing the minimum on-time of the next switching period of the synchronous rectifier tube.

18. An adaptive control circuit according to claim 17, wherein the logic circuit outputs the count instruction in dependence on the comparison signal after a first time end time delay from the minimum on-time end time of the current switching cycle.

19. The adaptive control circuit of claim 17, wherein the comparison circuit comprises:

a first comparison circuit, a positive input end of which receives a first threshold voltage and a negative input end of which receives a drain-source voltage of the synchronous rectifier tube and outputs a first comparison signal; and

and the positive input end of the second comparison circuit receives the drain-source voltage of the synchronous rectifier tube, and the negative input end of the second comparison circuit receives a second threshold voltage and outputs a second comparison signal.

20. The adaptive control circuit of claim 19, wherein the logic circuit comprises:

an exclusive-or gate having an input terminal receiving the first comparison signal and the second comparison signal;

an inverter, the input end of which receives a first time signal; and

and the D end of the trigger circuit receives an output signal of the exclusive-OR gate, the reset end of the trigger circuit receives a minimum on-time signal of the current switching period, and the clock end of the trigger circuit receives an output signal of the phase inverter.

21. The adaptive control circuit of claim 20, wherein the minimum on-time generation circuit comprises:

an up-down counter for receiving the first comparison signal and the output signal of the trigger circuit and outputting a numerical value signal;

a digital-to-analog conversion circuit for receiving the numerical value signal, outputting an analog signal corresponding to the numerical value signal after digital-to-analog conversion,

wherein the up-down counter receives the first comparison signal and an output signal of the flip-flop as the count instruction.

22. The method of claim 18, wherein the first time is set to be not less than a sum of a logic delay time inside a chip, a driving pull-down time, and a turn-off time of the synchronous rectifier tube.

23. The method of claim 18, wherein the first time is set to be not less than a sum of a logic delay time inside a chip, a driving pull-down time, a turn-off time of the synchronous rectifier and a charging time of a parasitic capacitance of the synchronous rectifier.

24. The method of claim 13, wherein the first threshold voltage is determined by a threshold voltage at which a body diode of the synchronous rectifier tube conducts.

25. The method of claim 24, wherein the first threshold voltage is set to less than zero.

26. The method of claim 14, wherein the second threshold voltage is substantially greater than a drain-source voltage at a turn-off time of the synchronous rectifier.

27. The method of claim 26, wherein the second threshold voltage is set greater than zero.

Technical Field

The invention relates to the technical field of power electronics, in particular to a self-adaptive control circuit and a control method.

Background

Synchronous rectification is a method of using a power MOSFET with low on-resistance instead of a rectifier diode to reduce the rectification loss. The power MOSFET is a voltage controlled device that has a linear current-voltage characteristic when turned on. When a power MOSFET is used as a rectifier, the gate voltage is required to be synchronous with the phase of the rectified voltage so as to complete the rectification function.

In most existing designs, when a synchronous rectification chip detects that the drain-source voltage of a synchronous rectification MOSFET is negative, the MOSFET is turned on, and when the synchronous rectification chip detects that the current in a channel of the synchronous rectification MOSFET is close to 0, the MOSFET is turned off. In practical applications, a large interference signal is present during switching operation, which tends to cause malfunction.

As shown in FIG. 1a, when the circuit is operated under heavy load, the duration of the interference signal caused by the switching action is long, which results in the minimum on-time T_ON-MINWave of drain-source voltage Vdsen of synchronous rectification after finishingForm resonance to V_{OFF_TH}Leading the synchronous rectification controller to be turned off in advance; as shown in FIG. 1b, when the circuit is in light load, the duration of the interference signal caused by the switching action is small, and the minimum on-time T is_ON-MINFreewheeling to zero longer than the secondary side will result in T_ON-MINThe drain-source voltage Vdsen of the post-synchronous rectification is larger than 0V, so that the synchronous rectification controller is turned off too late, negative current is caused, and abnormal work or circuit damage can be caused.

Disclosure of Invention

In view of the above, the present invention provides an adaptive control circuit and a control method thereof to solve the existing problems.

According to a first aspect of the present invention, an adaptive control method applied to a synchronous rectification circuit is provided, which includes: and detecting the drain-source voltage of the synchronous rectifier tube after the minimum on-time of the synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished, and adjusting the minimum on-time of the next switching period of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube.

Preferably, adjusting the minimum on-time of the next switching cycle of the synchronous rectifier according to the detected drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum on-time of the next switching period.

Preferably, adjusting the minimum on-time of the next switching cycle of the synchronous rectifier according to the detected drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, reducing the minimum on-time of the next switching period.

Preferably, adjusting the minimum on-time of the next switching cycle of the synchronous rectifier according to the detected drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum on-time of the next switching period.

Preferably, when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjusting the minimum on-time of the next switching cycle to be the minimum on-time of the current switching cycle and adding a second time; and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and reducing the second time.

Preferably, the drain-source voltage delayed from the minimum on-time end time of the synchronous rectifier tube by the first time end time in the current switching period is detected.

Preferably, the first time is set to be not less than the sum of a logic delay time inside a chip, a driving pull-down time, and a turn-off time of the synchronous rectifier tube.

Preferably, the first time is set to be not less than the sum of a logic delay time inside a chip, a driving pull-down time, a turn-off time of the synchronous rectifier tube and a charging time of a parasitic capacitance of the synchronous rectifier tube.

Preferably, the first threshold voltage is determined by a threshold voltage at which a body diode of the synchronous rectifier tube is turned on.

Preferably, the first threshold voltage is set to be less than zero.

Preferably, the second threshold voltage is substantially greater than the drain-source voltage at the turn-off time of the synchronous rectifier.

According to a second aspect of the present invention, an adaptive control circuit applied to a synchronous rectification circuit is provided, comprising: the voltage detection circuit is configured to detect drain-source voltage after the minimum conduction time of a synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished; and the regulating circuit is configured to adjust the minimum conducting time of the next switching period of the synchronous rectifying tube according to the drain-source voltage of the synchronous rectifying tube.

Preferably, the adjusting the minimum on-time of the next switching period of the synchronous rectifier according to the drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, increasing the minimum on-time of the next switching period.

Preferably, the adjusting the minimum on-time of the next switching period of the synchronous rectifier according to the drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, reducing the minimum on-time of the next switching period.

Preferably, the adjusting the minimum on-time of the next switching period of the synchronous rectifier according to the drain-source voltage of the synchronous rectifier comprises: and when the detected drain-source voltage of the synchronous rectifier tube is greater than the first threshold voltage and less than the second threshold voltage, not changing the minimum on-time of the next switching period.

Preferably, when the detected drain-source voltage of the synchronous rectifier tube is not greater than the first threshold voltage, adjusting the minimum on-time of the next switching cycle to be the minimum on-time of the current switching cycle and adding a second time; and when the detected drain-source voltage of the synchronous rectifier tube is not less than the second threshold voltage, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and reducing the second time.

Preferably, the adjusting circuit includes: the comparison circuit inputs the drain-source voltage and the reference voltage of the synchronous rectifier tube and outputs a comparison signal; the logic circuit receives the comparison signal and outputs a counting instruction; and the minimum conduction time generating circuit receives the counting instruction and outputs a signal representing the minimum conduction time of the next switching period of the synchronous rectifier tube.

Preferably, the logic circuit outputs the count instruction according to the comparison signal at a first time end time delayed from a minimum on-time end time of a current switching cycle.

Preferably, the comparison circuit includes: a first comparison circuit, a positive input end of which receives a first threshold voltage and a negative input end of which receives a drain-source voltage of the synchronous rectifier tube and outputs a first comparison signal; and a second comparison circuit, wherein the positive input end of the second comparison circuit receives the drain-source voltage of the synchronous rectifier tube, and the negative input end of the second comparison circuit receives a second threshold voltage and outputs a second comparison signal.

Preferably, the logic circuit comprises: an exclusive-or gate having an input terminal receiving the first comparison signal and the second comparison signal; an inverter, the input end of which receives a first time signal; and a D end of the trigger circuit receives an output signal of the exclusive-OR gate, a reset end of the trigger circuit receives a minimum on-time signal of the current switching period, and a clock end of the trigger circuit receives an output signal of the phase inverter.

Preferably, the minimum on-time generation circuit includes: an up-down counter for receiving the first comparison signal and the output signal of the trigger circuit and outputting a numerical value signal; and the digital-to-analog conversion circuit receives the numerical value signal, outputs an analog signal corresponding to the numerical value signal after digital-to-analog conversion, and the up-down counter receives the first comparison signal and an output signal of the trigger to be used as the counting instruction.

Preferably, the first time is set to be not less than the sum of logic delay time inside a chip, driving pull-down time and turn-off time of the synchronous rectifier tube.

Preferably, the first time is set to be not less than a sum of a logic delay time inside a chip, a pull-down driving time, a turn-off time of the synchronous rectifier and a charging time of a parasitic capacitance of the synchronous rectifier.

Preferably, the first threshold voltage is determined by a threshold voltage at which a body diode of the synchronous rectifier tube is turned on.

Preferably, the first threshold voltage is set to be less than zero.

Preferably, the second threshold voltage is substantially greater than the drain-source voltage at the turn-off time of the synchronous rectifier.

Preferably, the second threshold voltage is set greater than zero.

The invention provides a self-adaptive control circuit and a control method, which are applied to a synchronous rectification circuit, wherein the control method comprises the following steps: and detecting the drain-source voltage of the synchronous rectifier tube after the minimum on-time of the synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished, and adjusting the minimum on-time of the next switching period of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube. When the duration of the interference signal is shorter, the synchronous rectifier tube adopts the minimum conduction time; when the duration of the interference signal is long, a long minimum on-time is used.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1a is a waveform of a synchronous rectification circuit in a heavy load according to the prior art;

FIG. 1b is a waveform of a synchronous rectification circuit in light load according to the prior art;

FIG. 2 is a block diagram of an adaptive control circuit according to an embodiment of the present invention;

FIG. 3 is a circuit block diagram of a regulating circuit according to an embodiment of the present invention;

FIG. 4a is a first operating waveform of the adaptive control circuit according to the embodiment of the present invention;

FIG. 4b is a second operating waveform of the adaptive control circuit according to the embodiment of the present invention;

fig. 5 is a flowchart of an adaptive control method according to an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 2 is a block diagram of an adaptive control circuit according to an embodiment of the present invention. As shown in fig. 2, the adaptive control circuit 20 includes a voltage detection circuit 21 and an adjustment circuit 22. In the present invention, the adaptive control circuit 20 is applied to a synchronous rectification circuit. The voltage detection circuit 21 is configured to detect a drain-source voltage Vds after the minimum on-time of the synchronous rectifier M2 of the synchronous rectifier circuit in the current switching period is ended. It should be understood that any circuit capable of detecting the drain-source voltage is within the scope of the present invention. The regulating circuit 22 is used for adjusting the minimum on-time of the next switching period of the synchronous rectifier tube M2 according to the drain-source voltage Vds of the synchronous rectifier tube M2. The synchronous rectification circuit of the present invention may be any type of rectification circuit, such as a full-wave rectification circuit, a full-bridge rectification circuit, a half-wave rectification circuit, and a voltage-doubler rectification circuit, which is not limited in this respect.

Specifically, the voltage detection circuit 21 is configured to detect that the synchronous rectifier M2 of the synchronous rectifier circuit starts delaying the first time T when the minimum on-time ends in the current switching period_AEnd time of (2)When the drain-source voltage Vds of the synchronous rectifier M2 detected by the voltage detection circuit 21 is not greater than the first threshold voltage V1, the minimum on-time of the next switching cycle of the synchronous rectifier M2 is increased; when the drain-source voltage Vds of the synchronous rectifier M2 detected by the voltage detection circuit 21 is not less than a second threshold voltage V2, the minimum on-time of the next switching period of the synchronous rectifier M2 is reduced; when the drain-source voltage of the synchronous rectifier detected by the voltage detection circuit 21 is greater than the first threshold voltage V1 and less than the second threshold voltage V2, the minimum on-time of the next switching period of the synchronous rectifier M2 is not changed. Further, when the detected drain-source voltage of the synchronous rectifier M2 is not greater than the first threshold voltage V1, the minimum on-time of the next switching cycle is adjusted to be the minimum on-time of the current switching cycle and increased by a second time T_B(ii) a And when the detected drain-source voltage of the synchronous rectifier tube M2 is not less than the second threshold voltage V2, adjusting the minimum on-time of the next switching period to be the minimum on-time of the current switching period and reducing the minimum on-time by a second time T_B。

In the present invention, the first time T_AThe sampling delay time of the voltage Vds after the minimum conduction time of the synchronous rectifier tube is shown. In this embodiment, the first time T_AIs set to be not less than the sum of logic delay time inside the chip, drive pull-down time and turn-off time of the synchronous rectifier tube. If the parasitic capacitance Cds of the synchronous rectifier tube is charged by the leakage inductance energy after the synchronous rectifier tube is turned off and is increased, the first time T is_AIs set to be not less than the sum of a logic delay time inside a chip, a drive pull-down time, a turn-off time of the synchronous rectifier, and a charging time of a parasitic capacitance of the synchronous rectifier. The second time T_BThe minimum on-time adjustment value of the synchronous rectifier tube is larger than zero, and can be set according to the parameters of the synchronous rectifier tube. In this embodiment, the second time T_BCan be set to 400 ns and 600ns, preferably 500 ns. The first threshold voltage V1 is determined by the threshold voltage of the body diode of the synchronous rectifier. In bookIn an embodiment, when the threshold voltage at which the body diode is turned on is positive, the first threshold voltage V1 is set to be less than the threshold voltage at which the body diode is turned on and less than zero; when the threshold voltage at which the body diode is turned on is negative, the first threshold voltage V1 is set to be greater than the threshold voltage at which the body diode is turned on and less than zero. For example, the value is generally set to-200 mV to-500 mV, preferably to-300 mV. The second threshold voltage V2 is set to be significantly greater than the drain-source voltage at the turn-off time of the synchronous rectifier, and the second threshold voltage V2 is set to be greater than 0, which is typically set to 2V in this embodiment.

Fig. 3 is a circuit configuration diagram of a regulator circuit according to an embodiment of the present invention. As shown in fig. 3, the adjusting circuit 22 includes a comparing circuit 31, a logic circuit 32, and a minimum on-time generating circuit 33. The comparison circuit 31 is configured to receive the drain-source voltage Vds of the synchronous rectifier M2 and a reference voltage, and output a comparison signal. The logic circuit 32 is configured to receive the comparison signal and output a count instruction. The logic circuit 32 is configured to output the count instruction according to the comparison signal after starting to delay for a first time when the minimum on-time of the current cycle is over. The minimum on-time generation circuit 33 receives the counting command, and outputs a signal representing the minimum on-time of the next switching cycle of the synchronous rectifier according to the counting command.

Specifically, the comparison circuit 31 includes a first comparison circuit CMP1 and a second comparison circuit CMP 2. A positive input terminal of the first comparison circuit CMP1 receives a first threshold voltage V1, a negative input terminal receives a drain-source voltage Vds of the synchronous rectifier, and outputs a first comparison signal Vc 1; the positive input end of the second comparator CMP2 receives the drain-source voltage Vds of the synchronous rectifier, and the negative input end receives the second threshold voltage V2, and outputs a second comparison signal Vc 2. When the drain-source voltage Vds is less than the first threshold voltage V1, outputting a first comparison signal Vc1 as a high level; otherwise, the first comparison signal Vc1 is output as low level. When the drain-source voltage Vds is greater than the second threshold voltage V2, outputting a second comparison signal Vc2 as a high level; otherwise, the second comparison signal Vc2 is output as low level.

The logic circuit 32 includes an exclusive or gate U1, an inverter U2, and a flip-flop circuit U3. Wherein the inputs of the exclusive or gate U1 receive the first comparison signal Vc1 and the second comparison signal Vc 2; an input terminal of the inverter U2 receives the first time signal V representing a first time TA_TASaid first time signal V_TAThe period from the minimum on-time ending moment to the first time TA ending is valid; the D end of the trigger circuit U3 receives the output signal of the exclusive-OR gate U1, and the reset end reset receives the minimum on-time signal V of the current switching period_TON-MIN(N)The clock terminal clk receives the output signal of the inverter U2. When the drain-source voltage Vds is less than the first threshold voltage V1 or when the drain-source voltage Vds is greater than the second threshold voltage V2, the output signal of the exclusive or gate U1 is at a high level; when the drain-source voltage Vds is greater than the first threshold voltage V1 and less than a second threshold voltage V2, the output signal of the xor gate U1 is low. When the D end of the trigger receives a high level, the reset end reset of the trigger is a low level, and the clock end clk is a rising edge, the output signal of the trigger circuit is a high level; when the D end of the trigger is received to be low level, the output signal of the trigger circuit is low level.

The minimum on-time generation circuit 33 includes an up-down counter U4 and a digital-to-analog conversion circuit U5. The up-down counter U4 receives the first comparison signal VC1 and the output signal of the trigger circuit U3 and outputs a value signal. The digital-to-analog conversion circuit U5 receives the numerical signal, and outputs an analog signal corresponding to the numerical signal after digital-to-analog conversion. The up-down counter receives the first comparison signal and an output signal of the trigger to serve as the counting instruction, and the analog signal represents the minimum conducting time of the next switching period of the synchronous rectifier tube. When the first comparison signal Vc1 received by the up-down counter U4 is at a high level and the output signal of the flip-flop circuit U3 is also at a high level, the count command is 1, and the up-down counter U4 increments by 1; when the first comparison signal Vc1 is at low level, the flip-flop circuit U3When the output signal is at a high level, the counting command is 0, and the up-down counter U4 is decremented by 1; when the first comparison signal CMP1 is at a low level and the output signal of the flip-flop circuit is also at a low level, the up-down counter U4 is not incremented or decremented. The numerical value signal output by the up-down counter U4 is a binary numerical value signal, and is (0,0,0) < (1,1,1) from small to large. If the numerical signal output by the up-down counter U4 is (0,0,0), the voltage of the output analog signal is the minimum after the conversion by the digital-to-analog conversion circuit U5, and the corresponding T is_ON-MINMinimum; if the numerical signal output by the up-down counter U4 is (1,1,1), the analog signal voltage output after the conversion by the digital-to-analog conversion circuit U5 is the maximum and the corresponding T_ON-MINAnd max. The invention adopts a scheme that the D flip-flop is connected with the up-down counter in series, and of course, in other embodiments, a pure digital scheme can be adopted, which is not limited herein.

Fig. 4a is a first operating waveform of the adaptive control circuit according to the embodiment of the present invention. As shown in fig. 4a, when the synchronous rectification circuit operates under light load, the minimum on-time of the current switching period is much longer than the duration of the interference signal.

the time t1 is the end time of the minimum on-time of the synchronous rectifier tube M2 in the current switching period; the time T2 is the delay of the first time T after the end of the minimum conduction time of the synchronous rectifier M2 in the current switching period_AThe latter moment. And detecting a drain-source voltage Vds of the synchronous rectifier tube M2 at a time t2, wherein the drain-source voltage Vds is greater than a second threshold voltage V2, a first comparison signal Vc1 output by the first comparison circuit is at a low level, a second comparison signal output by the second comparison circuit is at a high level, and the xor gate U1 outputs a high level. At times t1-t2, the minimum on-time signal V_TON-MIN(N)Low, i.e. the reset terminal reset of the flip-flop is zero. First time signal V_TAIs a pulse, the output signal V of the inverter U2_U2Is low and at time t2, V_U2Rises to high level and is a rising edge. At time t2, the output signal of the exclusive or gate, i.e. high level, is received at the D terminal of the flip-flop U3,the set terminal reset is zero, and the clock terminal clk receives the output signal V of the inverter U2_U2At the rising edge, the output signal V of the flip-flop U3_U3Is at a high level; the up-down counter U4 receives a first comparison signal Vc1 and an output signal V of a flip-flop U3_U3Output a low level V_U4I.e. the up-down counter is decreased by 1, the minimum on-time of the next switching cycle is decreased.

In the next switching cycle, the adjusted minimum on-time T is detected_ON-MIN(N+1)Delaying by a first time T after the end (time T3)_AAnd a drain-source voltage Vds at the later time t4, where the drain-source voltage Vds is greater than a first threshold voltage V1 and smaller than a second threshold voltage V2, a first comparison signal Vc1 output by the first comparison circuit CMP1 is at a low level, a second comparison signal output by the second comparison circuit is at a low level, and the xor gate U1 outputs a low level. At times t3-t4, the minimum on-time signal V_TON-MIN(N+1)Is low level; at time t4, the output signal V of the inverter U2_U2Rising to high level as rising edge; at time t4, when the D terminal of the flip-flop U3 receives the output signal of the XOR gate U1, i.e. the low level, the flip-flop outputs V_U3Is low. A first comparison signal Vc1 received by the up-down counter and an output signal V of the trigger_U3And if the current is low level, the up-down counter is not added or not reduced, and the minimum on-time of the next switching period is not changed.

Fig. 4b is a second operation waveform of the adaptive control circuit according to the embodiment of the present invention. As shown in fig. 4b, when the synchronous rectification circuit operates under a heavy load, the minimum on-time of the current switching period is less than the duration of the interference signal.

the time t1 is the end time of the minimum on-time of the synchronous rectifier tube M2 in the current switching period; the time T2 is the delay of the first time T after the end of the minimum conduction time of the synchronous rectifier M2 in the current switching period_AThe latter moment. Detecting a drain-source voltage Vds of the synchronous rectifier tube M2 at a time t2, wherein the drain-source voltage Vds is smaller than a first threshold voltage V1, and a first comparison signal Vc1 output by the first comparison circuit is highAnd the level of the second comparison signal output by the second comparison circuit is low, and the exclusive or gate U1 outputs high. At times t1-t2, the minimum on-time signal V_TON-MIN(N)Low, i.e. the reset terminal reset of the flip-flop is zero. First time signal V_TAIs a pulse, the output signal V of the inverter U2_U2Is low and at time t2, V_U2Rises to high level and is a rising edge. At time t2, the D terminal of the flip-flop U3 receives the output signal of the xor gate, i.e., high level, the set terminal reset is zero, and the clock terminal clk receives the output signal V2 of the inverter U2_U2At the rising edge, the output signal V of the flip-flop U3_U3Is at a high level; the up-down counter U4 receives a first comparison signal Vc1 and an output signal V of a flip-flop U3_U3Output a high level V_U4I.e. the up-down counter is incremented by 1, the minimum on-time of the next switching cycle is increased.

In the next switching period, the first time T is delayed after the adjusted minimum on time is detected_AA later drain-source voltage Vds that is greater than the first threshold voltage V1 and less than the second threshold voltage V2. As described above, the minimum on-time of the next switching cycle is not changed.

The invention also discloses a synchronous rectification control method, which is applied to the synchronous rectification circuit and comprises the following steps: and detecting the drain-source voltage of the synchronous rectifier tube after the minimum on-time of the synchronous rectifier tube of the synchronous rectifier circuit in the current switching period is finished, and adjusting the minimum on-time of the next switching period of the synchronous rectifier tube according to the detected drain-source voltage of the synchronous rectifier tube.

Fig. 5 is a flowchart of an adaptive control method according to an embodiment of the present invention, including:

step 51: detecting drain-source voltage Vds at a time delayed for a first time after the minimum conduction time of the synchronous rectifier tube in the current switching period;

step 52: judging the drain-source voltage Vds and the first threshold voltage and the second threshold voltage;

step 53 a: if the drain-source voltage Vds is not larger than the first threshold voltage, increasing the minimum conduction time of the next switching-on and switching-off period; specifically, the minimum on-time of the next switching period is adjusted to be the minimum on-time of the current switching period and added with a second time;

step 53 b: if the drain-source voltage Vds is not less than the second threshold voltage, reducing the minimum on-time of the next switching-on and switching-off period; specifically, the minimum on-time of the next switching period is adjusted to be the minimum on-time of the current switching period and reduced by the second time;

step 53 c: if the drain-source voltage Vds is greater than the first threshold voltage and less than the second threshold voltage, the minimum on-time of the next switching period is not changed.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.