阅读说明：本技术 基于单极性晶体管的压控振荡器及模数转换器 (Voltage-controlled oscillator based on unipolar transistor and analog-digital converter ) 是由 徐煜明 陈荣盛 吴朝晖 李斌 于 2021-08-30 设计创作，主要内容包括：本发明公开了一种基于单极性晶体管的压控振荡器及模数转换器,其中压控振荡器包括：环形振荡器；延时单元,包括第一晶体管、第二晶体管和第一电容；第一晶体管的漏极连接电源电压VDD,第一晶体管的源极与第二晶体管的漏极连接,第二晶体管的源极接地,第二晶体管的漏极通过第一电容接地；第二晶体管的漏极连接至环形振荡器的输入端,环形振荡器的输出端连接至第一晶体管的栅极,第二晶体管的栅极连接控制电压Vctrl；第一晶体管工作在饱和区,第二晶体管工作在深三极管区；延时单元的延时远大于环形振荡器的延时。本发明提出一种仅使用n管或p管来设计压控振荡器的方案,满足特殊工艺上的要求,可广泛应用于半导体集成电路领域。(The invention discloses a voltage-controlled oscillator and an analog-to-digital converter based on a unipolar transistor, wherein the voltage-controlled oscillator comprises: a ring oscillator; the delay unit comprises a first transistor, a second transistor and a first capacitor; the drain electrode of the first transistor is connected with a power supply voltage VDD, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the source electrode of the second transistor is grounded, and the drain electrode of the second transistor is grounded through a first capacitor; the drain electrode of the second transistor is connected to the input end of the ring oscillator, the output end of the ring oscillator is connected to the grid electrode of the first transistor, and the grid electrode of the second transistor is connected with the control voltage Vctrl; the first transistor works in a saturation region, and the second transistor works in a deep triode region; the delay of the delay unit is much larger than that of the ring oscillator. The invention provides a scheme for designing a voltage-controlled oscillator by only using an n-tube or a p-tube, meets the requirements on special processes, and can be widely applied to the field of semiconductor integrated circuits.)

1. A unipolar transistor based voltage controlled oscillator, comprising:

the ring oscillator comprises n inverters which are sequentially connected, wherein n is an odd number;

the delay unit comprises a first transistor, a second transistor and a first capacitor;

the drain electrode of the first transistor is connected with a power supply voltage VDD, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the source electrode of the second transistor is grounded, and the drain electrode of the second transistor is grounded through the first capacitor; the drain electrode of the second transistor is connected to the input end of the ring oscillator, the output end of the ring oscillator is connected to the grid electrode of the first transistor, and the grid electrode of the second transistor is connected with a control voltage Vctrl;

acquiring the output end of an mth inverter as the output end of the voltage-controlled oscillator along the direction from the input end of the ring oscillator to the output end of the ring oscillator, wherein m is an odd number and is less than n-1;

the first transistor works in a saturation region, and the second transistor works in a deep triode region; the delay of the delay unit is much larger than the delay of the ring oscillator.

2. A unipolar transistor based voltage controlled oscillator as claimed in claim 1, wherein m-n-2.

3. The unipolar transistor based voltage controlled oscillator of claim 1, further comprising a level boost circuit;

the level lifting circuit is used for lifting the voltage of the control voltage Vctrl so that the control voltage Vctrl satisfies the following conditions: vctrl > VDD-Vth, where Vth is the threshold voltage of the transistor.

4. The unipolar transistor based voltage controlled oscillator of claim 3, wherein the level boost circuit comprises a third transistor and a fourth transistor;

the grid electrode of the third transistor is used as an input end of the level lifting circuit, the source electrode of the third transistor is grounded, the drain electrode of the third transistor is connected with the source electrode of the fourth transistor, and the grid electrode of the fourth transistor and the drain electrode of the fourth transistor are both connected to a bias voltage VSS;

the drain electrode of the third transistor outputs the control voltage Vctrl, and the bias voltage VSS is larger than the power supply voltage VDD.

5. The unipolar transistor based voltage controlled oscillator of claim 1, wherein the inverter comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a grid electrode of the fifth transistor and a drain electrode of the fifth transistor are both connected to a bias voltage VSS, a source electrode of the fifth transistor is connected with a drain electrode of the sixth transistor, and a source electrode of the sixth transistor is grounded;

the drain of the seventh transistor is connected with a power supply voltage VDD, the gate of the seventh transistor is connected with the source of the fifth transistor, the source of the seventh transistor is connected with the drain of the eighth transistor, and the source of the eighth transistor is grounded;

and the grid electrode of the sixth transistor is connected with the grid electrode of the eighth transistor and is used as the input end of the inverter, and the source electrode of the seventh transistor is used as the output end of the inverter.

6. The unipolar transistor based voltage controlled oscillator of claim 1, wherein the output frequency of the voltage controlled oscillator is expressed by:

wherein, T_ROIs the delay of a ring oscillator, T_DELAYFor the delay of the delay unit, μ C_oxIs a parameter of the transistor that is,is the width and length of the second transistorRatio, V_ctrlFor controlling the voltage, V_thIs the threshold voltage of the transistor and C is the first capacitance.

7. The unipolar transistor-based voltage-controlled oscillator of claim 1, wherein a width-to-length ratio of the first transistor is substantially greater than a width-to-length ratio of the second transistor.

8. An analog-to-digital converter, comprising:

the follow hold circuit comprises a ninth transistor and a second capacitor, wherein the gate of the ninth transistor is connected with the clock signal Clk, the drain of the ninth transistor is connected with the input signal, and the source of the ninth transistor is grounded through the second capacitor;

the input end of the voltage-controlled oscillator is connected with the source electrode of the ninth transistor and is used for outputting a pulse signal according to the voltage of the source electrode of the ninth transistor;

the enabling end of the counter is connected with a clock signal Clk and is used for counting the output pulses of the voltage-controlled oscillator;

the output trigger is used for latching the output signal of the counter in the previous period after receiving the trigger of the clock signal Clk;

the voltage controlled oscillator is implemented using a unipolar transistor based voltage controlled oscillator as claimed in any one of claims 1 to 7.

9. The analog-to-digital converter according to claim 8, wherein the resolution N of the analog-to-digital converter is calculated by the following formula:

wherein f is_maxIs the maximum oscillation frequency of the voltage controlled oscillator, f_minIs the minimum oscillation frequency of the voltage controlled oscillator, f_errorTo be pressure-controlledMaximum linearity error of the oscillator.

10. An analog-to-digital converter as claimed in claim 8, characterized in that the hold time T of the follow-and-hold circuit_HThe following conditions are satisfied:

wherein f is_errorIs the maximum linearity error of the voltage controlled oscillator.

Technical Field

The invention relates to the field of semiconductor integrated circuits, in particular to a voltage-controlled oscillator and an analog-to-digital converter based on unipolar transistors.

Background

It is well known that standard silicon-based complementary oxide semiconductor (CMOS) technology is complementary transistor (with both n-and p-transistors). However, some special processes such as thin film transistors, gallium nitride processes, etc. tend to be unipolar transistors (only n-tubes or p-tubes). For these processes, conventional CMOS circuit design techniques are no longer applicable. Therefore, it is necessary to develop circuits using only n or p transistors for these processes.

A Voltage Controlled Oscillator (VCO) is an important circuit module, and is widely used in various functional circuits, including constituting an analog-to-digital converter (ADC), but there is no technical solution of voltage controlled oscillators designed for unipolar transistors at present.

Disclosure of Invention

To solve at least some of the technical problems in the prior art, an object of the present invention is to provide a voltage controlled oscillator and an analog-to-digital converter based on unipolar transistors.

The technical scheme adopted by the invention is as follows:

a unipolar transistor based voltage controlled oscillator comprising:

the ring oscillator comprises n inverters which are sequentially connected, wherein n is an odd number; the inverter is composed of a plurality of transistors with the same polarity;

the delay unit comprises a first transistor, a second transistor and a first capacitor;

the drain electrode of the first transistor is connected with a power supply voltage VDD, the source electrode of the first transistor is connected with the drain electrode of the second transistor, the source electrode of the second transistor is grounded, and the drain electrode of the second transistor is grounded through the first capacitor;

the drain electrode of the second transistor is connected to the input end of the ring oscillator, the output end of the ring oscillator is connected to the grid electrode of the first transistor, and the grid electrode of the second transistor is connected with a control voltage Vctrl;

acquiring the output end of an mth inverter as the output end of the voltage-controlled oscillator along the direction from the input end of the ring oscillator to the output end of the ring oscillator, wherein m is an odd number and is less than n-1;

the first transistor works in a saturation region, and the second transistor works in a deep triode region; the delay of the delay unit is much larger than the delay of the ring oscillator.

Further, m-n-2.

Further, the voltage-controlled oscillator further comprises a level-up circuit;

the level lifting circuit is used for lifting the voltage of the control voltage Vctrl so that the control voltage Vctrl satisfies the following conditions: vctrl > VDD-Vth, where Vth is the threshold voltage of the transistor.

Further, the level-raising circuit includes a third transistor and a fourth transistor;

the grid electrode of the third transistor is used as an input end of the level lifting circuit, the source electrode of the third transistor is grounded, the drain electrode of the third transistor is connected with the source electrode of the fourth transistor, and the grid electrode of the fourth transistor and the drain electrode of the fourth transistor are both connected to a bias voltage VSS;

the drain electrode of the third transistor outputs the control voltage Vctrl, and the bias voltage VSS is larger than the power supply voltage VDD.

Further, the inverter includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

a grid electrode of the fifth transistor and a drain electrode of the fifth transistor are both connected to a bias voltage VSS, a source electrode of the fifth transistor is connected with a drain electrode of the sixth transistor, and a source electrode of the sixth transistor is grounded;

the drain of the seventh transistor is connected with a power supply voltage VDD, the gate of the seventh transistor is connected with the source of the fifth transistor, the source of the seventh transistor is connected with the drain of the eighth transistor, and the source of the eighth transistor is grounded;

and the grid electrode of the sixth transistor is connected with the grid electrode of the eighth transistor and is used as the input end of the inverter, and the source electrode of the seventh transistor is used as the output end of the inverter.

Further, the expression of the output frequency of the voltage-controlled oscillator is:

wherein, T_ROIs the delay of a ring oscillator, T_DELAYFor the delay of the delay unit, μ C_oxIs a parameter of the transistor that is,is the width-to-length ratio, V, of the second transistor_ctrlFor controlling the voltage, V_thIs the threshold voltage of the transistor and C is the first capacitance.

Further, the width-to-length ratio of the first transistor is much larger than that of the second transistor.

The other technical scheme adopted by the invention is as follows:

an analog-to-digital converter comprising:

the follow hold circuit comprises a ninth transistor and a second capacitor, wherein the gate of the ninth transistor is connected with the clock signal Clk, the drain of the ninth transistor is connected with the input signal, and the source of the ninth transistor is grounded through the second capacitor;

the input end of the voltage-controlled oscillator is connected with the source electrode of the ninth transistor and is used for outputting a pulse signal according to the voltage of the source electrode of the ninth transistor;

the enabling end of the counter is connected with a clock signal Clk and is used for counting the output pulses of the voltage-controlled oscillator;

the output trigger is used for latching the output signal of the counter in the previous period after receiving the trigger of the clock signal Clk;

the voltage-controlled oscillator is implemented by adopting a voltage-controlled oscillator based on unipolar transistors as described above.

Further, the resolution N of the analog-to-digital converter is calculated by the following formula:

wherein f is_maxIs the maximum oscillation frequency of the voltage controlled oscillator, f_minIs the minimum oscillation frequency of the voltage controlled oscillator, f_errorIs the maximum linearity error of the voltage controlled oscillator.

Further, the holding time T of the follow-hold circuit_HThe following conditions are satisfied:

wherein f is_errorIs the maximum linearity error of the voltage controlled oscillator.

The invention has the beneficial effects that: the invention provides a scheme for designing a voltage-controlled oscillator by only using an n-tube or a p-tube, which meets the requirements on special processes. In addition, an analog-to-digital converter is further designed on the basis of a voltage-controlled oscillator designed by unipolar transistors.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a circuit diagram of a voltage controlled oscillator based on unipolar transistors in an embodiment of the present invention;

FIG. 2 is a waveform diagram of nodes Va, Vb of a voltage controlled oscillator in an embodiment of the invention;

FIG. 3 is a circuit diagram of a voltage controlled oscillator with a level-up circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a voltage transfer characteristic of a boost circuit in accordance with an embodiment of the present invention;

FIG. 5 is a circuit diagram of a mode converter in an embodiment of the invention;

FIG. 6 is a timing diagram of the mode converter in an embodiment of the invention;

FIG. 7 is a diagram illustrating linearity error of a voltage controlled oscillator according to an embodiment of the present invention;

fig. 8 is a circuit diagram of an inverter in an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

The present embodiment provides a VCO circuit design using only n-transistors, and then an ADC design is implemented on the basis of the VCO circuit. It should be noted that the present embodiment only discusses a pure n-type circuit as an example, but the proposed technical solution is also applicable to a pure p-type circuit. For a pure p-type circuit, the circuit of the invention is only required to be turned over up and down, and therefore, the details are not described.

As shown in fig. 1, the present embodiment provides a voltage-controlled oscillator based on unipolar transistors, including:

the ring oscillator comprises n inverters which are sequentially connected, wherein n is an odd number;

a delay unit including a first transistor T1, a second transistor T2, and a first capacitor C1;

the drain of the first transistor T1 is connected to the power supply voltage VDD, the source of the first transistor T1 is connected to the drain of the second transistor T2, the source of the second transistor T2 is grounded, and the drain of the second transistor T2 is grounded through the first capacitor C1;

the drain of the second transistor T2 is connected to the input terminal of the ring oscillator, the output terminal of the ring oscillator is connected to the gate of the first transistor T1, and the gate of the second transistor T2 is connected to the control voltage Vctrl;

acquiring the output end of an mth inverter as the output end of the voltage-controlled oscillator along the direction from the input end of the ring oscillator to the output end of the ring oscillator, wherein m is an odd number and is less than n-1;

the first transistor T1 operates in a saturation region, and the second transistor T2 operates in a deep triode region; the delay of the delay unit is much larger than that of the ring oscillator.

In the present embodiment, a delay unit (including a first transistor T1, a second transistor T2, and a first capacitor C1) is inserted in the ring oscillator. Since the delay cells are in phase, the number of ring oscillator stages is odd for oscillation. The operating principle of the ring oscillator is as follows: first, assume that Va is high, then the first capacitor will charge, Vb rises, when Vb rises to high, the inverter chain level is triggered to flip, Va goes low, then the first capacitor will discharge, Vb falls, when Vb falls to low, the inverter chain level is triggered to flip, and Va goes high again. The above period is cyclically reciprocated, thereby generating oscillation. The corresponding node waveforms are shown in fig. 2. The output signal is taken from the ring oscillator, which is the same as the node Va, and the output signal from the mth inverter is selected, and in some embodiments, the output signal is taken at the output of the third last inverter. As shown in fig. 1. If the capacitor is charged for a time much less than the discharge time by proper design, the oscillation period is approximately equal to the discharge time (i.e., the delay of the delay unit), and the output should be a series of narrow pulses as shown in fig. 2.

The second transistor T2 acts as a resistor during the discharge of the first capacitor, the discharge time being dependent on the time constant R2C1, where R2 is the equivalent resistance of the second transistor T2. Therefore, to make the oscillation frequency and the input control voltage Vctrl linear, it is critical that T2 be in the deep triode region (VDS < VGS-Vth). A transistor in the deep triode region is equivalent to a linear voltage controlled resistor:

in some alternative embodiments, the width-to-length ratio of the first transistor T1 is much greater than the width-to-length ratio of the second transistor T2.

The following discusses the size (the size refers to the transistor width-to-length ratio) of the first transistor T1 and the second transistor T2. First, as described above, only when the charging time of the first capacitor is much shorter than the discharging time, the oscillation period can be considered to be equal to the delay time of the delay unit, and thus the oscillation frequency is considered to be linearly controlled by the control voltage Vctrl. To satisfy the requirement that the charging time is much shorter than the discharging time, it is obvious that the size of the pull-up transistor T1 (i.e. the first transistor T1) is much larger than that of the pull-down transistor T2 (i.e. the second transistor T2). In addition, in FIG. 1, Vb is supposed to rise to a high level without any hypothesis. In fact, however, Vb cannot rise to the desired high level due to the weak pull-down action of the second transistor T2 (which is still conductive although it is in the deep triode region). We assume that Vb can reach the highest level Vh. Vh is the result of the cooperation of the pull-up tube T1 (in saturation region) and the pull-down tube T2 (in deep triode region). Giving the expression of Vh:

note from the equation that Vh varies with changes in the control voltage Vctrl, which will introduce linearity errors into the VCO. Interestingly, if T1 is satisfied much more than T2, then the variation in Vh will be suppressed and Vh will also be closer to the ideal high level. When the aspect ratio of the first transistor T1 is much larger than that of the second transistor T2, Vgs1 tends to Vth, i.e., Vh tends to VDD-Vth, and thus is not affected by the control voltage Vctrl. In general, it is required that the size of T1 be much larger than that of T2.

In some optional embodiments, the voltage controlled oscillator further comprises a level-up circuit; the level lifting circuit is used for lifting the voltage of the control voltage Vctrl, so that the control voltage Vctrl satisfies the following conditions: vctrl > VDD-Vth, where Vth is the threshold voltage of the transistor.

As shown in fig. 3, in some alternative embodiments, the level raising circuit includes a third transistor T3 and a fourth transistor T4;

the gate of the third transistor T3 is used as the input terminal of the level-up circuit, the source of the third transistor T3 is grounded, the drain of the third transistor T3 is connected to the source of the fourth transistor T4, and the gate of the fourth transistor T4 and the drain of the fourth transistor T4 are both connected to the bias voltage VSS;

the drain of the third transistor T3 outputs a control voltage Vctrl, the bias voltage VSS > the power supply voltage VDD.

When the control voltage Vctrl is not lifted, the working range of the control voltage Vctrl is relatively small, and the performance of the voltage-controlled oscillator is limited, so that the level lifting circuit is designed to lift the control voltage Vctrl in this embodiment.

The generation of the control voltage Vctrl is discussed below. As mentioned above, the circuit requires the second transistor T2 to operate in the deep triode region, which means Vctrl > VDD-Vth. However, if Vctrl is an output signal of the preceding stage circuit, its value must be between (0, VDD), and the requirement for operating the second transistor T2 in the deep triode region is not satisfied. Therefore, it is necessary to design the level-up circuit as shown in fig. 3, which is composed of a third transistor T3 and a fourth transistor T4, and is actually a "diode load-connected" inverter/amplifier. The essence lies in that: the bias voltage VSS is supplied instead of the supply voltage VDD. As can be seen from the "diode-loaded" inverter/amplifier nature, as the input rises gradually from 0, the output falls gradually from VSS. Since VSS > VDD, it is possible to raise an input signal having a value between (0, VDD) to between (VDD, VSS) as long as the design is proper. The key points here are: the T3/T4 ratio needs to be carefully designed according to the magnitude relationship of VSS and VDD to control the falling rate of the output so that the output remains larger than VDD-Vth when the input rises to VDD. As an example, fig. 4 shows the case of a boosted circuit voltage transfer curve when VSS is 2VDD and T3/T4 is 1. Easy analogy yields: when VSS approaches VDD (VDD +2Vth < VSS <2VDD), T3/T4 is reduced, slowing down the output droop rate; conversely, when VSS is far from VDD (2VDD < VSS), T3/T4 may be increased as appropriate, thereby increasing the output droop rate. The "diode load connected" inverter/amplifier has a good linearity, and when it is normally operated (the third transistor T3 and the fourth transistor T4 are both in the saturation region), its output falling rate (small signal gain) is determined only by T3/T4, regardless of the input signal. This indicates that the boost circuit does not introduce linearity errors into the VCO. Although the signal will be inverted after the boost circuit, this does not affect the main function of the VCO circuit.

The choice of RO stage number (i.e., inverter chain stage number) and capacitance value is discussed below. In fig. 1 we do not assume that the signal transfer from Vb to Va is instantaneous and actually takes place with a delay through the inverter chain. We can write a more complete expression of the oscillation frequency:

wherein, T_ROIs the delay of the inverter chain, T_DELAYIs the delay of the delay unit. Obviously, to improve the linearity of the VCO, T needs to be satisfied_RO<<T_DEALY. Therefore, the number of RO stages is as small as possible while ensuring the start-up. Usually taking the minimum RO stage number that causes the circuit to start oscillating. The capacitance value is a compromise between linearity and oscillation frequency. The capacitance becomes large, T_DELAYLarger, better VCO linearity, but lower frequency; capacitance becomes small, T_DELAYThe smaller the VCO linearity, the higher the frequency.

As shown in fig. 8, in some alternative embodiments, the inverter includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

the gate of the fifth transistor T5 and the drain of the fifth transistor T5 are both connected to the bias voltage VSS, the source of the fifth transistor T5 is connected to the drain of the sixth transistor T6, and the source of the sixth transistor T6 is grounded;

a drain of the seventh transistor T7 is connected to the power supply voltage VDD, a gate of the seventh transistor T7 is connected to the source of the fifth transistor T5, a source of the seventh transistor T7 is connected to the drain of the eighth transistor T8, and a source of the eighth transistor T8 is grounded;

a gate of the sixth transistor T6 is connected to a gate of the eighth transistor T8 and serves as an input terminal of the inverter, and a source of the seventh transistor T7 serves as an output terminal of the inverter.

As shown in fig. 8, the inverter circuit is powered by two power sources VSS and VDD, and VSS > VDD +2Vth is required to be satisfied in order to achieve an ideal high level, and VSS is often taken to be 2VDD in practice for simplicity.

As shown in fig. 5, the present embodiment further provides an analog-to-digital converter, including:

a follower hold circuit including a ninth transistor T9 and a second capacitor C2, the gate of the ninth transistor T9 being connected to the clock signal Clk, the drain of the ninth transistor T9 being connected to the input signal, the source of the ninth transistor T9 being connected to ground through a second capacitor C2;

a voltage-controlled oscillator, an input terminal of which is connected to the source of the ninth transistor T9, for outputting a pulse signal according to a voltage at the source of the ninth transistor T9;

the enabling end of the counter is connected with a clock signal Clk and is used for counting the output pulse of the voltage-controlled oscillator;

the output trigger is used for latching the output signal of the counter in the previous period after receiving the trigger of the clock signal Clk;

the voltage-controlled oscillator is implemented by using a voltage-controlled oscillator based on unipolar transistors as above.

As shown in fig. 5, the ADC is constructed by combining the VCO described above with a follow/hold (T/H) circuit (including a ninth transistor T9, a second capacitor C2), an n-bit counter, and an n-bit output flip-flop. Fig. 6 gives the timing sequence. When Clk is at high level, the T/H circuit follows the input signal, and the counter is reset to zero. When Clk is low, the T/H circuit keeps the input signal of the previous moment, the counter enables to work, and the VCO output pulse is counted. The output flip-flop triggers each time Clk rises, latching the output signal of the counter of the previous cycle.

Hold time T_HDetermined by the maximum linearity error of the VCO. The VCO maximum linearity error is shown in fig. 7. Assuming that the solid line is the actual curve of the VCO, connecting the two endpoints thereof to obtain the dashed line as the ideal curve, and the maximum error of the solid line and the dashed line in the y direction is the maximum linear error f of the VCO_error. Hold time T_HMust satisfyThe error can be resolved. Following time T_TDepends on the time constant R9C2 of the T/H circuit, where R9 is the equivalent resistance of T9. For a step input, the response at node Vc is:

it is clear that the worst case occurs at VinFrom Vin, min to Vin, max (or vice versa). We can now give the sampling rate of the ADC as fs 1/(T)_T+T_H). To prevent overflow, the number of bits n of the counter and output flip-flop should satisfy 2ⁿ>T_HFmax, fmax is the maximum oscillation frequency of the VCO (as shown in fig. 7). The counting process can be implemented by a computer program or by a circuit.

If the counting process is ideal (i.e., can count decimals), the resolution N of the ADC can be given by:

in practice, the counter can only count in integers, so the resolution is slightly lower than the ideal resolution given by the above equation.

In summary, the VCO and the ADC of the present embodiment have the following beneficial effects compared with the prior art:

(1) the embodiment provides a voltage-controlled oscillator only consisting of unipolar transistors, and the voltage-controlled oscillator comprises a ring oscillator, a delay unit and a level-raising circuit.

(2) In the embodiment, when the delay unit is designed: t1> > T2, i.e. the width-to-length ratio of the first transistor is much larger than that of the second transistor, so as to suppress the variation of the voltage Vh and further reduce the error of the VCO.

(3) By designing the boost circuit to be powered by VSS instead of VDD, the ratio of T3/T4 needs to be carefully designed according to the magnitude relation between VSS and VDD so as to control the falling rate of the output, so that the output is still larger than VDD-Vth when the input rises to VDD, and the performance of the VCO is improved.

(4) Inverter chain order and capacitance design strategy: the minimum RO stage number for starting the circuit oscillation is obtained, the capacitance value is compromised between the linearity and the oscillation frequency, and the performance of the VCO is improved.

(5) The embodiment provides an analog-to-digital converter, which is composed of four parts: VCO, T/H circuit, n-bit counter, n-bit output trigger. ADC time sequence: when Clk is high, T/H circuit followsInputting signal, resetting counter to zero. When Clk is low, the T/H circuit keeps the input signal of the previous moment, the counter enables to work, and the VCO output pulse is counted. The output flip-flop triggers each time Clk rises, latching the output signal of the counter of the previous cycle. Based on the analog-to-digital converter, the embodiment further provides a method for determining a series of parameters of the ADC, where the parameters include: following time T_TRetention time T_HSampling rate fs, counter and output trigger number of bits N, resolution N.

In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.