阅读说明：本技术 驱动装置、芯片、拍摄装置和无人机 (Drive arrangement, chip, shooting device and unmanned aerial vehicle ) 是由 黄睿 陈龙 蔡畅 于 2020-07-28 设计创作，主要内容包括：本申请提供一种驱动装置、芯片、拍摄装置和无人机,驱动装置中通过控制器与复用电路连接,向复用电路发送控制信号；复用电路与储能电容单元连接,响应所述控制器的控制,对所述储能电容单元进行充电或放电,以及向目标负载输出驱动信号,其中,复用电路包括滤波电路单元,所述滤波电路单元电连接在所述控制器与所述目标负载之间,以及所述储能电容单元与所述目标负载之间；当对所述储能电容单元进行充电时,所述滤波电路单元作为充电回路的无源网络使用,当所述储能电容单元进行放电时,所述滤波电路单元作为EMI滤波器使用,从而实现了对充电回路和放电回路的结构复用,降低了驱动装置的体积,精简了控制线路,降低线路损耗减小功耗。(The application provides a driving device, a chip, a shooting device and an unmanned aerial vehicle, wherein the driving device is connected with a multiplexing circuit through a controller and sends a control signal to the multiplexing circuit; the multiplexing circuit is connected with the energy storage capacitor unit, responds to the control of the controller, charges or discharges the energy storage capacitor unit, and outputs a driving signal to a target load, wherein the multiplexing circuit comprises a filter circuit unit which is electrically connected between the controller and the target load and between the energy storage capacitor unit and the target load; when the energy storage capacitor unit is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter, so that structural multiplexing of the charging loop and the discharging loop is realized, the size of the driving device is reduced, a control circuit is simplified, the line loss is reduced, and the power consumption is reduced.)

1. A drive device for driving a motor, comprising: the energy storage capacitor unit comprises a controller, an energy storage capacitor unit and a multiplexing circuit;

The controller is connected with the multiplexing circuit and used for sending a control signal to the multiplexing circuit;

the multiplexing circuit is connected with the energy storage capacitor unit and used for responding to a control signal of the controller, charging or discharging the energy storage capacitor unit and outputting a driving signal to a target load;

the multiplexing circuit comprises a filter circuit unit which is electrically connected between the controller and the target load and between the energy storage capacitor unit and the target load;

when the energy storage capacitor unit is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter.

2. The driving apparatus as claimed in claim 1, wherein the multiplexing circuit further comprises a switching circuit unit electrically connected between the controller and the filtering circuit unit and between the energy storage capacitor unit and the filtering circuit unit for controlling the energy storage capacitor unit to be charged or discharged.

3. The driving apparatus according to claim 2, wherein the multiplexing circuit further comprises a blocking circuit unit electrically connected between the filter circuit unit and the target load;

When the energy storage capacitor unit supplies power to the target load through the filter circuit unit, the blocking circuit unit plays a blocking role, and circulation is avoided.

4. The driving apparatus according to claim 3, wherein the multiplexing circuit specifically includes a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first inductance unit, a second inductance unit, a first blocking diode, and a second blocking diode;

one end of the first switch unit is connected with a grounding end through the second switch unit, and the other end of the first switch unit is connected with the high-voltage end of the energy storage capacitor unit; one end of the first inductance unit is connected with the target load, and the other end of the first inductance unit is connected between the first switch unit and the second switch unit; the anode of the first anti-circulating current diode is connected with a power supply end, and the cathode of the first anti-circulating current diode is connected between the first inductance unit and the target load;

one end of the fourth switch unit is connected with a grounding end through the third switch unit, and the other end of the fourth switch unit is connected with the high-voltage end of the energy storage capacitor unit; one end of the second inductance unit is connected with the target load, and the other end of the second inductance unit is connected between the fourth switch unit and the third switch unit; the anode of the second anti-circulation diode is connected with a power supply end, and the cathode of the second anti-circulation diode is connected between the second inductance unit and the target load; the low-voltage end of the energy storage capacitor unit is connected with the grounding end;

The control end of the first switch unit, the control end of the second switch unit, the control end of the third switch unit and the control end of the fourth switch unit are all connected with the controller; the controller is specifically configured to send out a control signal for controlling the turn-on timings of the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit.

5. The driving device according to claim 4, wherein the filter circuit unit specifically comprises a first filter capacitor unit and a second filter capacitor unit;

one end of the first filter capacitor unit is connected between the first inductor unit and the target load, and the other end of the first filter capacitor unit is connected with a grounding end;

one end of the second filter capacitor unit is connected between the second inductor unit and the target load, and the other end of the second filter capacitor unit is connected with a grounding end.

6. The driving apparatus according to claim 4 or 5, wherein the multiplexing circuit further comprises a main gate driving unit, the main gate driving unit is configured to convert a control signal from the controller into a gate driving signal for driving the gate of the switching tube;

the input end of the main grid electrode driving unit is connected with the controller, the first output end of the main grid electrode driving unit is connected with the control end of the first switch unit, the second output end of the main grid electrode driving unit is connected with the control end of the second switch unit, the third output end of the main grid electrode driving unit is connected with the control end of the third switch unit, and the fourth output end of the main grid electrode driving unit is connected with the control end of the fourth switch unit.

7. The driving apparatus as claimed in claim 1, wherein the energy storage capacitor unit comprises 2 capacitor sub-units;

the driving device further includes: and the capacitor voltage equalizing unit is connected between the 2 capacitor subunits and is used for equalizing voltage of the 2 capacitor subunits.

8. The driving apparatus as claimed in claim 7, wherein the capacitance voltage equalizing unit comprises: the device comprises a first reference voltage division unit, a second reference voltage division unit, a comparator, a positive feedback impedance unit, a negative feedback impedance unit, an oscillation capacitor unit and a filter inductor unit;

the first reference voltage division unit and the second reference voltage division unit are connected between the high-voltage end and the grounding end of the energy storage capacitor unit in series; a positive phase input end of the comparator is connected between the first reference voltage division unit and the second reference voltage division unit, and an inverted phase input end of the comparator is connected with a ground end through the oscillation capacitor unit; the first end of the filter inductance unit is connected with the output end of the comparator, and the second end of the filter inductance unit is connected between the 2 capacitor subunits; one end of the positive feedback impedance unit is connected with a positive phase input end of the comparator, and the other end of the positive feedback impedance unit is connected with an output end of the comparator; one end of the negative feedback impedance unit is connected with the inverting input end of the comparator, and the other end of the negative feedback impedance unit is connected with the second end of the filter inductance unit.

9. The driving apparatus according to claim 8, wherein the capacitance equalizing unit further comprises a buffer unit;

and the output end of the comparator is connected with the first end of the filter inductance unit through the buffer unit.

10. The drive arrangement of claim 8 or 9, wherein the capacitive subunit comprises 2ⁿA capacitor cell, and 2ⁿ-1 said capacitor voltage equalizing units connected tree-like, said n being an integer greater than 0.

11. The drive device according to claim 1, further comprising a pre-boosting unit;

the multiplexing circuit is connected with a power supply end through the pre-boosting unit; the pre-boosting unit is used for boosting the voltage of the power supply end and then transmitting the boosted voltage to the multiplexing circuit.

12. The driving apparatus as claimed in claim 11, wherein the pre-boosting unit comprises a first half-bridge control unit and a second half-bridge energy storage unit;

the first half-bridge control unit is connected with the controller, the second half-bridge energy storage unit, the power supply end and the ground end, and is used for responding to the control of the controller and transmitting a power supply voltage signal of the power supply end or a ground voltage signal of the ground end to the second half-bridge energy storage unit;

The second half-bridge energy storage unit is further connected with the controller, the multiplexing circuit, the direct current end and the grounding end and used for responding to the control of the controller when the first half-bridge control unit transmits the grounding voltage signal, the direct current end is charged to store energy, and the first half-bridge control unit transmits the power voltage signal, the controller is controlled to be turned on, and the grounding end is boosted, discharged and output to the multiplexing circuit.

13. The driving apparatus as claimed in claim 12, wherein the number of the second half-bridge energy storage units is 1;

and the direct current end corresponding to the second half-bridge energy storage unit is a power supply end.

14. The driving apparatus as claimed in claim 12, wherein the number of the second half-bridge energy storage units is M greater than 1;

m it is individual second half-bridge energy storage unit connects gradually, every second half-bridge energy storage unit all with first half-bridge control unit connects, and the direct current end that first second half-bridge energy storage unit of order corresponds is the output of power supply unit, and the direct current end that all the other M-1 second half-bridge energy storage units correspond is the output of the preceding second half-bridge energy storage unit of order, the last second half-bridge energy storage unit of order with multiplex circuit connects.

15. The drive device according to any one of claims 12 to 14,

the first half-bridge control unit includes: the grid-connected inverter comprises a first grid driver, a first field-effect tube and a second field-effect tube; the first field effect transistor and the second field effect transistor are connected between a power supply end and a grounding end in a forward series mode; the high-side driving signal output end of the first grid driver is connected with the grid electrode of the first field effect transistor, the half-bridge module output end of the first grid driver is connected between the first field effect transistor and the second field effect transistor, the low-side driving signal output end of the first grid driver is connected with the grid electrode of the second field effect transistor, and the high-side input end and the low-side input end of the first grid driver are connected with the controller;

the second half-bridge energy storage unit comprises: the first flying capacitor, the first output capacitor, the second gate driver, the coupling impedor, the coupling capacitor, the third field effect transistor and the fourth field effect transistor; the third field effect transistor and the fourth field effect transistor are connected in series in an opposite direction, the drain electrode of the third field effect transistor is connected with a grounding end through the first output capacitor, and the source electrode of the fourth field effect transistor is connected with a direct current end; a high-side driving signal output end of the second gate driver is connected with a gate of the third field effect transistor, a low-side driving signal output end of the second gate driver is connected with a gate of the fourth field effect transistor through the coupling capacitor, one end of the coupling impedor is connected with the direct current end, the other end of the coupling impedor is connected between the fourth field effect transistor and the coupling capacitor, and a high-side input end and a low-side input end of the second gate driver are connected with the controller; one end of the first flying capacitor is connected with the output end of the half-bridge module of the second grid driver, and the other end of the first flying capacitor is connected between the first field effect transistor and the second field effect transistor.

16. The driving apparatus as claimed in claim 15, wherein the first half-bridge control unit further comprises a first bootstrap diode and a first isolation capacitor; the anode of the first bootstrap diode is connected with the chip power supply end of the first grid driver, and the cathode of the first bootstrap diode is connected with the floating power supply end of the first grid driver; one end of the first isolation capacitor is connected with the floating power supply end of the first grid driver, and the other end of the first isolation capacitor is connected with the output end of the half-bridge module of the first grid driver, wherein the chip power supply end of the first grid driver is also connected with the first power supply end;

the second half-bridge control unit further comprises a second bootstrap diode and a second isolation capacitor; the anode of the second bootstrap diode is connected with a second power supply end, and the cathode of the second bootstrap diode is connected with the floating power supply end of the second grid driver; one end of the second isolation capacitor is connected with the floating power supply end of the second grid driver, and the other end of the second isolation capacitor is connected with the output end of the half-bridge module of the second grid driver; the chip power supply end of the second gate driver is further connected to the first power supply end, and the voltage of the second power supply end is the sum of the voltage of the power supply end and the voltage of the first power supply end.

17. The driving apparatus as claimed in claim 11, wherein the pre-boosting unit comprises a single substantially voltage-doubling unit;

the multiplexing circuit is connected with a power supply end through the single basic voltage doubling unit, and the power supply end is a voltage-doubling front power supply end of the single basic voltage doubling unit;

the basic voltage doubling unit is used for boosting the voltage of the power supply terminal by 2 times and transmitting the boosted voltage to the multiplexing circuit.

18. The driving device according to claim 11, wherein the pre-boosting unit specifically includes K basic voltage doubling units sequentially connected in sequence, where K is an integer greater than 1;

the multiplexing circuit is connected with a power supply end through the K basic voltage doubling units which are sequentially connected; the K basic voltage doubling units which are sequentially connected are used for boosting the voltage of the power supply end by 2K times and transmitting the boosted voltage to the multiplexing circuit;

the K basic voltage doubling units are sequentially connected with one another, and the first basic voltage doubling unit is connected with a power supply end and a grounding end and used for boosting the voltage of the power supply end by 2 times and outputting the boosted voltage; the other K-1 basic voltage doubling units are connected with a grounding end and a voltage doubling output end of the previous basic voltage doubling unit in sequence and used for outputting the output voltage of the previous basic voltage doubling unit in sequence after being superposed with the voltage of the power supply end by 2 times; the power supply end is a voltage-multiplying front power supply end of the first basic voltage-multiplying unit in the sequence, and the voltage-multiplying output end of the first basic voltage-multiplying unit in the sequence is a voltage-multiplying front power supply end of the rest K-1 basic voltage-multiplying units.

19. The drive device according to claim 17 or 18, wherein the substantially voltage doubling unit comprises: the second filter capacitor is connected with the first filter impedor, the second filter impedor, the third filter impedor, the fourth filter impedor, the first filter capacitor, the second filter capacitor, the third filter capacitor, the fourth filter capacitor, the second output capacitor and the second flying capacitor;

the fifth field effect tube and the sixth field effect tube are connected between a voltage-multiplying front power supply end and a grounding end in a forward series mode, the seventh field effect tube and the eighth field effect tube are connected between the voltage-multiplying front power supply end and the grounding end in a reverse series mode, and the eighth field effect tube is connected with the grounding end through the second output capacitor;

one end of the first filtering impedor is connected with a voltage-multiplying front power supply end, the other end of the first filtering impedor is connected with the controller through the first filtering capacitor, and the grid electrode of the fifth field effect transistor is connected between the first filtering impedor and the first filtering capacitor;

one end of the second filtering impedor is connected with a ground terminal, the other end of the second filtering impedor is connected with the controller through the second filtering capacitor, and the grid electrode of the sixth field effect transistor is connected between the second filtering impedor and the second filtering capacitor;

One end of the third filtering impedor is connected with a voltage-multiplying front power supply end, the other end of the third filtering impedor is connected with the controller through the third filtering capacitor, and the grid electrode of the seventh field effect transistor is connected between the third filtering impedor and the third filtering capacitor;

one end of the fourth filtering impedor is connected with a ground end through the second output capacitor, the other end of the fourth filtering impedor is connected with the controller through the fourth filtering capacitor, and the grid electrode of the eighth field effect transistor is connected between the fourth filtering impedor and the fourth filtering capacitor;

a first end of the second flying capacitor is connected between the fifth field effect transistor and the sixth field effect transistor, and a second end of the second flying capacitor is connected between the seventh field effect transistor and the eighth field effect transistor;

the fifth field effect transistor and the eighth field effect transistor are P-type field effect transistors; the sixth field effect transistor and the seventh field effect transistor are N-type field effect transistors.

20. The driving apparatus as claimed in claim 19, wherein said first terminal of said second flying capacitor further forms an inverted pulse output terminal for outputting a pulse signal having the same voltage value as the voltage at the power supply terminal and having a phase opposite to the signal inputted to the voltage doubling unit from said controller.

21. The drive device according to claim 20, wherein the pre-booster unit further includes: adder units corresponding to the basic voltage doubling units one by one, and T +1 switch selectors, wherein T is the number of the adder units;

the T adder units are sequentially connected, and each adder unit is connected with the reverse pulse output end of one basic voltage doubling unit through one switch selector; the last adder unit in the sequence is also connected with the voltage-multiplying output end of the last basic voltage-multiplying unit in the sequence through a switch selector, the adding output ends of the rest T-1 adder units are connected with the adding input end of the adder unit before the sequence, and the adding output end of the first adder unit in the sequence is connected with the multiplexing circuit;

the T +1 switch selectors are used for controlling the voltage output by the addition output end of the sequential first adder unit to the multiplexing circuit.

22. The driving device according to claim 21, wherein the adder unit comprises in particular: the third flying capacitor, the ninth field effect transistor, the tenth field effect transistor, the fifth filter impedor, the sixth filter impedor, the fifth filter capacitor, the sixth filter capacitor and the addition capacitor;

The ninth field effect transistor and the tenth field effect transistor are connected between an addition input end and a grounding end in an inverted series manner, and the tenth field effect transistor is connected with the grounding end through the addition capacitor;

one end of the fifth filtering impedor is connected with an addition input end, the other end of the fifth filtering impedor is connected with the controller through the fifth filtering capacitor, and the grid electrode of the ninth field effect transistor is connected between the fifth filtering impedor and the fifth filtering capacitor;

one end of the sixth filtering impedor is connected with a ground end through the addition capacitor, the other end of the sixth filtering impedor is connected with the controller through the sixth filtering capacitor, and the grid electrode of the tenth field effect transistor is connected between the sixth filtering impedor and the sixth filtering capacitor;

one end of the third flying capacitor is connected with an inverted pulse output end, and the other end of the third flying capacitor is connected between the ninth field effect transistor and the tenth field effect transistor;

wherein the ninth field effect transistor is an N-type field effect transistor, and the tenth field effect transistor is a P-type field effect transistor;

and one end of the addition capacitor connected with the tenth field effect transistor is an addition output end of the adder unit.

23. A chip comprising a driving device according to any one of claims 1 to 22.

24. A photographing apparatus, characterized by comprising a target load, an

A chip as claimed in claim 23 or a drive means as claimed in any one of claims 1 to 22.

25. An unmanned aerial vehicle comprising a main body and the camera of claim 24 mounted on the main body.

Technical Field

The embodiment of the application relates to the technical field of electronics, especially, relate to a drive arrangement, chip, shooting device and unmanned aerial vehicle.

Background

In the driving design of various terminal devices, an energy storage capacitor assembly is usually used to realize driving higher than a power supply voltage. The driving device needs to perform charging and discharging management on the energy storage capacitor assembly, and meanwhile, the problem of high current surge caused by inconstant discharging power in the driving process is avoided.

In the related art, the operations of the charge management unit and the discharge driving unit are generally controlled by a controller, respectively.

However, the complicated control circuit of the controller, the independent modular charging management and discharging driving result in the increase of the product volume and power consumption, and it is difficult to meet the requirements of miniaturization and low power consumption of the terminal device.

Disclosure of Invention

The application provides a drive arrangement, chip, shooting device and unmanned aerial vehicle, through the structure multiplexing to the return circuit of charging and the return circuit that discharges, reduced drive arrangement's volume, retrencied control scheme, reduced the line loss and reduced the consumption.

According to a first aspect of the present application, there is provided a driving apparatus comprising: the energy storage capacitor unit comprises a controller, an energy storage capacitor unit and a multiplexing circuit;

the controller is connected with the multiplexing circuit and used for sending a control signal to the multiplexing circuit;

The multiplexing circuit is connected with the energy storage capacitor unit and used for responding to a control signal of the controller, charging or discharging the energy storage capacitor unit and outputting a driving signal to a target load;

the multiplexing circuit comprises a filter circuit unit which is electrically connected between the controller and the target load and between the energy storage capacitor unit and the target load;

when the energy storage capacitor unit is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter.

According to a second aspect of the present application, there is provided a chip comprising the driving device of the first aspect of the present application.

According to a third aspect of the present application, there is provided a camera comprising a target load, and a chip as described in the second aspect of the present application or a driving device as described in the first aspect of the present application.

According to the fourth aspect of this application, provide an unmanned aerial vehicle, including the main part fuselage with install in the shooting device as the first aspect of this application on the main part fuselage.

The application provides a driving device, a chip, a shooting device and an unmanned aerial vehicle, wherein the driving device is connected with a multiplexing circuit through a controller and sends a control signal to the multiplexing circuit; the multiplexing circuit is connected with the energy storage capacitor unit, responds to the control of the controller, charges or discharges the energy storage capacitor unit, and outputs a driving signal to a target load, wherein the multiplexing circuit comprises a filter circuit unit which is electrically connected between the controller and the target load and between the energy storage capacitor unit and the target load; when the energy storage capacitor unit is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit is discharged, the filter circuit unit is used as an EMI filter, so that structural multiplexing of the charging loop and the discharging loop is realized, the size of the driving device is reduced, a control circuit is simplified, the line loss is reduced, and the power consumption is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a driving device according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of another driving device provided in the embodiments of the present application;

FIGS. 2A-2C are schematic views of charge and discharge stages based on the structure of FIG. 2 according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of another driving apparatus provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of another driving apparatus provided in the embodiment of the present application;

fig. 5 is a schematic structural diagram of a capacitor voltage equalizing unit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another capacitor voltage equalizing unit provided in the embodiment of the present application;

fig. 7 is a schematic structural diagram of another capacitor voltage equalizing unit according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a tree-connected capacitor voltage equalizing unit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a pre-boosting driving apparatus according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a pre-boosting unit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another pre-boosting unit according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of another pre-boosting unit according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a pre-boosting unit according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a pre-boosting unit according to an embodiment of the present disclosure;

Fig. 15 is a schematic structural diagram of an adder unit according to an embodiment of the present application;

fig. 16 is a schematic diagram of a chip structure provided in an embodiment of the present application;

fig. 17 is a schematic structural diagram of a shooting device according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of an unmanned aerial vehicle provided in an embodiment of the present application.

Reference numerals:

10: a drive device; 11: a controller; 12: an energy storage capacitor unit; 13: a multiplexing circuit;

q1: a first switching unit Q1; q2: a second switching unit; q3: a third switching unit; q4: a fourth switching unit; l1: a first inductance unit; l2: a second inductance unit; d1: a first ring current blocking diode; d2: a second ring current blocking diode;

vcap: a voltage node; vs: a power supply terminal; c1: a first filter capacitor unit; c2: a second filter capacitor unit; 131: a main gate driving unit; g 1: a first output terminal; g 2: a second output terminal; g 3: a third output terminal; g 4: a fourth output terminal;

121: a capacitor sub-unit; 14: a capacitor voltage-sharing unit; rp 1: a first reference voltage dividing unit; rp 2: a second reference voltage dividing unit; u1: a comparator; RF +: a positive feedback impedance unit; RF-: a negative feedback impedance unit; cosc: an oscillation capacitance unit; lo: a filter inductance unit;

141: a buffer unit; 14 a: a first capacitor voltage-sharing unit; 14 b: a second capacitance voltage-sharing unit; 14 c: a third capacitor voltage-sharing unit; CL 1: a first storage capacitor; CL 2: a second storage capacitor; CL 3: a third storage capacitor; CL 4: a fourth storage capacitor;

15: a pre-boosting unit; 151: a first half-bridge control unit; 152: a second half-bridge energy storage unit; 1511: a first gate driver; g1: a first field effect transistor; g2: a second field effect transistor; cfly 1: a first flying capacitor; cout 1: a first output capacitor; 1521: a second gate driver; rd: a coupling impedor; cd: a coupling capacitor; g3: a third field effect transistor; g4: a fourth field effect transistor; db 1: a first bootstrap diode; cb 1: a first isolation capacitor; db 2: a second bootstrap diode; cb 2: a second isolation capacitor;

153: a substantially voltage doubling unit; g5: a fifth field effect transistor; g6: a sixth field effect transistor; g7: a seventh field effect transistor; g8: an eighth field effect transistor; r1: a first filter impeder; r2: a second filter impeder; r3: a third filter impeder; r4: a fourth filtered impeder; c31: a first filter capacitor; c32: a second filter capacitor; c33: a third filter capacitor; c34: a fourth filter capacitor; cout 2: a second output capacitor; cfly 2: a second flying capacitor;

153: an adder unit; cfly 3: a third flying capacitor; g9: a ninth field effect transistor; g10: a tenth field effect transistor; r5: a fifth filter impeder; r6: a sixth filter impeder; c35: a fifth filter capacitor; c36: sixth filter capacitance and C +: and an addition capacitor.

Detailed Description

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

In application scenarios such as camera shutter driving, electromagnet magnetizing driving, fill-in light (flash) driving, or ranging system power supply, which need to provide instantaneous high-pulse power driving, a driving device and an energy storage capacitor assembly are usually utilized to drive a target load. In the related art, the charging management and the discharging driving of the energy storage capacitor assembly are respectively realized by two mutually independent circuits, and the circuit volume is larger; and the controller needs to control the charging management module and the discharging driving module respectively by two independent control circuits, and the control circuits are complex.

In order to solve the problems in the related art, the application provides a driving device, which realizes the structural multiplexing of charge management and discharge driving by a multiplexing circuit, reduces the circuit volume, simplifies the control circuit and reduces the energy consumption on the circuit.

Fig. 1 is a schematic structural diagram of a driving device according to an embodiment of the present disclosure. The driving device 10 shown in fig. 1 includes: a controller 11, an energy storage capacitor unit 12 and a multiplexing circuit 13. The controller 11 is connected to the multiplexing circuit 13, and is configured to send a control signal to the multiplexing circuit 13. The multiplexing circuit 13 is connected to the energy storage capacitor unit 12, and is configured to charge or discharge the energy storage capacitor unit 12 in response to a control signal of the controller 11, and output a driving signal to a target load. The multiplexing circuit 13 shown in fig. 1 has a function of performing charge management on the energy storage capacitor unit 12 and a function of controlling the energy storage capacitor unit 12 to discharge to drive a target load, and is a circuit structure multiplexing of a charge management module and a discharge driving module in the related art. The multiplexing circuit 13 includes a filter circuit unit, and the filter circuit unit is electrically connected between the controller 11 and the target load and between the energy storage capacitor unit 12 and the target load; when the energy storage capacitor unit 12 is charged, the filter circuit unit is used as a passive network of a charging loop, and when the energy storage capacitor unit 12 is discharged, the filter circuit unit is used as an Electromagnetic Interference (EMI) filter. The communication between the controller 11 and the multiplexing circuit 13 is connection communication of multiplexed signal lines, and for example, alternate control of charging and discharging can be realized by timing control, and multiplexing and reduction of control lines are realized.

In the embodiment, the driving device is connected with the multiplexing circuit through the controller and sends a control signal to the multiplexing circuit; the multiplexing circuit is connected with the energy storage capacitor unit, responds to the control of the controller, charges or discharges the energy storage capacitor unit, and outputs a driving signal to a target load, wherein the multiplexing circuit comprises a filter circuit unit which is electrically connected between the controller and the target load and between the energy storage capacitor unit and the target load; when charging the energy storage capacitor unit, the filter circuit unit is used as the passive network of the charging circuit, and when discharging the energy storage capacitor unit, the filter circuit unit is used as an EMI filter, and the size occupation of the driving unit is reduced through the simplified design of the circuit multiplexing structure, so that the miniaturization application is facilitated, and the signal line is simplified through the multiplexing of the control signal line, and the reliability of the circuit is improved.

For example, the control signal output by the controller to the multiplexing circuit may be a multiplexed control signal, that is, the controller sends a control signal and controls the multiplexing circuit to charge or discharge the energy storage capacitor unit, and when the charging or discharging is finished, the multiplexing circuit outputs the driving signal to the target load. The controller may output the control signal to the multiplexing circuit as an independent control signal, that is, the controller may transmit one control signal to control the multiplexing circuit to charge or discharge the energy storage capacitor unit, and transmit the other control signal to control the multiplexing circuit to output the driving signal to the target load. The multiplexing circuit can further comprise a switch circuit unit which is electrically connected between the controller and the filter circuit unit and between the energy storage capacitor unit and the filter circuit unit and used for controlling the energy storage capacitor unit to charge or discharge. It is understood that there are other control signal transmission modes in the specific implementation process, and the present application is not limited thereto. An alternative circuit configuration of the multiplexing circuit 13 in fig. 1 will be described below on the basis of the configuration shown in fig. 1. Further, the multiplexing circuit may further include a blocking circuit unit electrically connected between the filter circuit unit and the target load. When the energy storage capacitor unit supplies power to the target load through the filter circuit unit, the blocking circuit unit plays a blocking role, and circulation is avoided. Fig. 2 is a schematic structural diagram of another driving device provided in the embodiment of the present application. In the driving apparatus 10 shown in fig. 2, the controller 11 is not shown, the energy storage capacitor unit 12 is illustrated as a single capacitor, and the multiplexing circuit 13 may specifically include a first switching unit Q1 (illustrated as a fet), a second switching unit Q2 (illustrated as a fet), a third switching unit Q3 (illustrated as a fet), a fourth switching unit Q4 (illustrated as a fet), a first inductance unit L1 (illustrated as a single inductor), a second inductance unit L2 (illustrated as a single inductor), a first blocking current diode D1, and a second blocking current diode D2. As shown in fig. 2, the multiplexing circuit 13 can be understood as a charge-discharge multiplexing H-bridge circuit, and the circuits connected to both sides of the target load are substantially symmetrical. One end of the energy storage capacitor unit 12 is connected to the voltage node Vcap, and the other end is grounded.

As shown in fig. 2, one end of the first switch unit Q1 is connected to the ground terminal through the second switch unit Q2, and the other end is connected to the high-voltage terminal of the energy-storage capacitor unit. One end of the first inductance unit L1 is connected to the target load, and the other end is connected between the first switching unit Q1 and the second switching unit Q2. The anode of the first anti-ringing diode D1 is connected to the power source terminal Vs, and the cathode is connected between the first inductor unit L1 and the target load. One end of the fourth switching unit Q4 is connected to the ground terminal through the third switching unit Q3, and the other end is connected to the high-voltage terminal of the energy storage capacitor unit. One end of the second inductor unit L2 is connected to the target load, and the other end is connected between the fourth switching unit Q4 and the third switching unit Q3. The anode of the second anti-ringing diode D2 is connected to the power source terminal Vs, and the cathode is connected between the second inductor unit L2 and the target load. And the low-voltage end of the energy storage capacitor unit is connected with the grounding end. As shown in fig. 2, the first switching unit Q1, the second switching unit Q2, the third switching unit Q3, and the fourth switching unit Q4 are each exemplified by an N-type field effect transistor, but may be a transistor, a relay, or other components having a switching function. In the present embodiment, the first switch unit Q1, the second switch unit Q2, the third switch unit Q3 and the fourth switch unit Q4 are all connected in the forward direction. For example, in the forward connection, the source of each switch unit shown in fig. 2 is connected to a low potential, the drain is connected to a high potential, and each switch tube is forward biased.

In the example shown in fig. 2, among others, the control terminal of the first switching unit Q1, the control terminal of the second switching unit Q2, the control terminal of the third switching unit Q3, and the control terminal of the fourth switching unit Q4 are connected to the controller. For example, in fig. 2, the gate of the first switching unit Q1, the gate of the second switching unit Q2, the gate of the third switching unit Q3 and the gate of the fourth switching unit Q4 are all connected to a controller, and are used for turning on or off the switching tubes in response to the control of the controller. The controller is specifically configured to issue control signals that control the turn-on timings of the first, second, third, and fourth switching units Q1, Q2, Q3, and Q4.

Since the left half-bridge composed of the first switch unit Q1, the second switch unit Q2, the first inductor unit L1 and the first anti-circulating diode D1 in fig. 2 and the right half-bridge composed of the third switch unit Q3, the fourth switch unit Q4, the second inductor unit L2 and the second anti-circulating diode D2 are symmetrical in structure, the charging and discharging principle is similar, and the charging and discharging process of the left half-bridge is exemplified in this embodiment. The on and off of the first switch unit Q1 and the second switch unit Q2 are controlled by control signals sent by a controller.

Fig. 2A-2C are schematic views of charge and discharge stages based on the structure of fig. 2 according to an embodiment of the present disclosure. The implementation of a complete charging and discharging process in fig. 2 may specifically comprise three stages in sequence: in the first stage, as shown in fig. 2A, the controller controls the first switch unit Q1 to be turned off and the second switch unit Q2 to be turned on, the first blocking diode D1 is forward biased to provide a charging current path, and the power source terminal Vs directly charges the first inductor unit L1, so as to charge the first inductor unit L1; in the second stage, as shown in fig. 2B, the controller controls the first switch unit Q1 to be turned on and the second switch unit Q2 to be turned off, the first inductor unit L1 is equivalent to a current source to discharge to the energy storage capacitor unit in this stage, and the current in the first inductor unit L1 is gradually reduced to 0, so as to charge the energy storage capacitor unit; in the third stage, as shown in fig. 2C, the controller keeps the first switch unit Q1 turned on and the second switch unit Q2 turned off, the energy storage capacitor unit discharges to the target load through the first switch unit Q1 and the first inductor unit L1, so as to drive the target load, and in this stage, the first blocking diode D1 is reversely biased to block the discharging current path from Vs, so as to avoid the occurrence of a circulating current. The three stages shown in fig. 2A-2C are executed circularly, so that the cyclic charge and discharge control of the energy storage capacitor unit can be realized.

Here, the charging phase may be understood as a process in which the power source terminal Vs transfers energy to the energy storage capacitor unit through the first inductor unit L1 in the first phase and the second phase, and the charging power in the charging phase is constant in this embodiment since the energy transfer process is independent of the voltage of the capacitor. The discharging phase may be understood as a third phase, in which the energy storage capacitor unit discharges to the target load through the first switch unit Q1 and the first inductor unit L1. In the structure shown in fig. 2, the first blocking diode D1 and the second blocking diode D2 isolate the charging process and the discharging process of the half-bridge at two sides, and prevent the power source end Vs from being charged by high voltage in the discharging process, thereby realizing the structural multiplexing of the charging path and the discharging path, and reducing the volume of the charging circuit and the discharging circuit. Optionally, the energy storage capacitor unit may further be connected to the controller to implement feedback and monitoring of the charging condition, so that the controller further controls the operating state of each switch unit according to the charging condition of the energy storage capacitor unit, so that the energy storage capacitor unit fluctuates around a preset voltage value all the time.

Fig. 2A-2C show the charging and discharging process of the left half-bridge in fig. 2, and the charging and discharging timings of the left half-bridge and the right half-bridge in fig. 2 for discharging the target load may be performed alternately or synchronously.

As an example of alternately discharging the target load, the discharge timings of the left half-bridge and the right half-bridge may be opposite. In fig. 2, for example, the left half bridge is in the first phase and the second phase in the period T1, that is, the first switching unit Q1 is turned off, the second switching unit Q2 is turned on to charge the first inductance unit L1, then the first switching unit Q1 is turned on, and the second switching unit Q2 is turned off to charge the energy storage capacitance unit; and the right half bridge is in the third stage in the period T1, i.e. the third switching unit Q3 is kept turned off, and the fourth switching unit Q4 is turned on to form a discharge path of the energy storage capacitor unit to the target load. Then, the left half-bridge enters a third stage in a period T2 after T1, i.e., the first switching unit Q1 is kept turned on, and the second switching unit Q2 is turned off to form a discharge path of the energy storage capacitor unit to the target load; during the period T2, the right half-bridge enters the first stage and the second stage, i.e., the fourth switching unit Q4 is turned off, the third switching unit Q3 is turned on to charge the second inductance unit L2, the fourth switching unit Q4 is turned on, and the third switching unit Q3 is turned off to charge the energy storage capacitor unit. The cycle T1-T2 realizes the alternating charging and discharging of the left half bridge and the right half bridge to the target load. The left half-bridge and the right half-bridge alternately discharge to a target load, so that the output current of the power supply end Vs is reduced, the loss of a transmission line is reduced, and the impact on the power supply end Vs is also reduced.

As an example of the synchronous discharge to the target load, the discharge timings of the left half-bridge and the right half-bridge may be the same. In fig. 2, for example, the left half-bridge and the right half-bridge are in the first phase and the second phase at the same time at T1, that is, the first switching unit Q1 is turned off, the second switching unit Q2 is turned on to charge the first inductance unit L1, the fourth switching unit Q4 is turned off, the third switching unit Q3 is turned on to charge the second inductance unit L2, the first switching unit Q1 is turned on, the second switching unit Q2 is turned off to charge the energy storage capacitance unit, the fourth switching unit Q4 is turned on, and the third switching unit Q3 is turned off to charge the energy storage capacitance unit. Then, the left half-bridge and the right half-bridge enter a third phase in a period T2, namely, the first switching unit Q1 is kept turned on, the second switching unit Q2 is kept turned off to form a discharge path of the energy storage capacitor unit to the target load, and meanwhile, the third switching unit Q3 is kept turned off, and the fourth switching unit Q4 is kept turned on to form a discharge path of the energy storage capacitor unit to the target load. The cycle T1-T2 realizes the synchronous charging and discharging of the left half bridge and the right half bridge to the target load. The target load synchronous discharge simplifies the timing control.

In the process of charging the energy storage capacitor unit, since the power source end Vs and the inductance unit equivalent to the current source are connected in series to charge the energy storage capacitor unit, a voltage value higher than the voltage of the power source end Vs can be loaded on the energy storage capacitor unit. In the above embodiment, the first inductance unit L1 and the second inductance unit L2 may be a single inductance as shown in fig. 2, or may be an assembly formed by a plurality of inductances, which is not limited herein. The first switch unit Q1, the second switch unit Q2, the third switch unit Q3, and the fourth switch unit Q4 may be N-type fets, transistors, relays, and other devices with switch control, as shown in fig. 2, and the implementation principle and technical effect of the devices are similar to those of the fets shown in fig. 2, which are not described herein again.

On the basis of the structure shown in fig. 2, fig. 3 is a schematic structural diagram of another driving device provided in the embodiment of the present application. Compared with fig. 2, the filter circuit unit in the multiplexing circuit shown in fig. 3 may specifically include a first filter capacitor unit C1 and a second filter capacitor unit C2, which respectively form LC low-pass filtering with the first inductor unit L1 and the second inductor unit L2, so as to implement filtering during discharging of the energy storage capacitor unit. Specifically, as shown in fig. 3, one end of the first filter capacitor unit C1 is connected between the first inductor unit L1 and the target load, and the other end is connected to the ground. One end of the second filter capacitor unit C2 is connected between the second inductor unit L2 and the target load, and the other end is connected to the ground terminal. The first inductor unit L1 and the second inductor unit L2 are used as charging inductors in the first stage shown in fig. 2A and the second stage shown in fig. 2B, but in the third stage shown in fig. 2C, the first inductor unit L1 and the second inductor unit L2 form a second-order low-pass filter with the first filter capacitor unit C1 and the second filter capacitor unit C2, so that the higher harmonics of the input target load are reduced, and the electromagnetic interference of the target load to the external radiation is reduced. In addition, since the electronic components generally have a problem of energy loss due to their own bulk capacitors (Coss capacitor and Crss capacitor of the switching tube), the first filter capacitor unit C1 and the second filter capacitor unit C2 in this embodiment can recover the bulk capacitor energy in the switching unit. Specifically, in the dead time of the third stage of the embodiment shown in fig. 2C, the bulk capacitor of the second switching unit Q2 may discharge the first filter capacitor unit C1 through the first inductor unit L1, and the energy of the bulk capacitor is transferred to the first filter capacitor unit C1 for storage. In the first phase of the embodiment shown in fig. 2A, the part of the energy stored in the first filter capacitor unit C1 also participates in charging the first inductor unit L1, thereby achieving the recovery of the bulk capacitance energy of the second switch unit Q2 through the first filter capacitor unit C1. The second filter capacitor unit C2 realizes the recovery of the energy of the body capacitor of the third switching unit Q3 based on the same principle.

In the embodiment shown in fig. 2 or fig. 3, fig. 4 is a schematic structural diagram of another driving device provided in the embodiment of the present application. Compared with the circuit shown in fig. 2 or fig. 3, the multiplexing circuit shown in fig. 4 further includes a main gate driving unit 131, where the main gate driving unit 131 is used to convert a control signal from the controller into a gate driving signal for driving the gate of the switching tube, and the main gate driving unit may be a main gate driver. The main gate driving unit 131 has one input terminal to which the multiplexing signal is connected and four output terminals (g1, g2, g3, g 4). Specifically, the input terminal of the main gate driving unit 131 is connected to the controller, the first output terminal g1 is connected to the control terminal of the first switching unit Q1, the second output terminal g2 is connected to the control terminal of the second switching unit Q2, the third output terminal g3 is connected to the control terminal of the third switching unit Q3, and the fourth output terminal g4 is connected to the control terminal of the fourth switching unit Q4. The main gate driving unit 131 converts a control signal from the controller into a switching driving signal that can directly drive each switching unit. In fig. 4, the first switching unit Q1, the second switching unit Q2, the third switching unit Q3 and the fourth switching unit Q4 are fets, and their respective control terminals are gates of the fets. If the first, second, third and fourth switching units Q1, Q2, Q3 and Q4 are transistors, the control terminal is the base of the transistor. If the first, second, third and fourth switching units Q1, Q2, Q3 and Q4 are relays, the control terminal is a switching control port of the relay.

In the above various embodiments, the energy storage capacitor unit may be one capacitor or an assembly of a plurality of capacitors, and is not limited herein. But for the structure that the energy storage capacitor unit comprises two capacitors connected in series, a capacitor voltage equalizing unit can be added for equalizing voltage. Wherein, the capacitor contained in the energy storage capacitor unit can be a farad capacitor.

Fig. 5 is a schematic structural diagram of a capacitor voltage equalizing unit according to an embodiment of the present application. On the basis of the embodiments shown in fig. 2, fig. 3, or fig. 4, the energy storage capacitor unit may specifically include 2 capacitor subunits 121. In order to reduce the voltage imbalance among the 2 capacitor subunits 121 due to the individual difference of the components during the charging and discharging processes of the energy storage capacitor unit, the driving apparatus may further include a capacitor voltage equalizing unit 14 as shown in fig. 5. The capacitor voltage equalizing unit 14 is connected between the 2 capacitor subunits 121 shown in fig. 5, and is used for equalizing the voltage of the 2 capacitor subunits 121. The capacitor subunits 121 are illustrated as a single capacitor in fig. 5, but each capacitor subunit 121 may specifically be an assembly including a plurality of capacitors, or a capacitive assembly formed by a capacitor and other electronic devices. The capacitor subunits 121 on both sides of the access position of the capacitor voltage equalizing unit 14 should have the same structure, so as to implement a symmetrical structure in which 2 capacitor subunits 121 are connected in series, and the specific structure of a single capacitor subunit 121 is not limited in this embodiment. The capacitive sub-unit 121 in the storage capacitive unit may be a farad capacitor.

The capacitor voltage equalizing unit 14 in fig. 5 may include: the voltage divider circuit comprises a first reference voltage dividing unit Rp1, a second reference voltage dividing unit Rp2, a comparator U1, a positive feedback impedance unit RF +, a negative feedback impedance unit RF-, an oscillation capacitor unit Cosc and a filter inductance unit Lo. Specifically, as shown in fig. 5, the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 are connected in series between the high voltage terminal and the ground terminal of the energy storage capacitor unit. The high voltage terminal of the energy storage capacitor unit in fig. 5 is the voltage node Vcap to which the energy storage capacitor unit shown in fig. 2 is connected, so that a stable reference voltage is provided at the node between the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2, and the voltage value is half of the voltage node Vcap. The first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 may be resistors shown in fig. 5 or other impedance type components, for example, and are not limited herein. The non-inverting input (denoted by the symbol +) of the comparator U1 is connected between the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2, thereby connecting a more reference voltage. The inverting input (denoted by the symbol-b) of the comparator U1 is connected to ground via an oscillating capacitor Cosc. The first terminal of the filter inductance unit Lo is connected to the output terminal of the comparator U1, and the second terminal is connected between the 2 capacitor subunits 121. One end of the positive feedback impedance unit RF + is connected with the non-inverting input terminal of the comparator U1, and the other end is connected with the output terminal of the comparator U1. One end of the negative feedback impedance unit RF-is connected with the inverting input terminal of the comparator U1, and the other end is connected with the second terminal of the filter inductance unit Lo. The capacitor voltage-sharing unit 14 shown in fig. 5 can realize high dynamic response precision voltage sharing of the capacitor without communication with a controller.

After the capacitor voltage-sharing unit 14 is powered on, the capacitor voltage-sharing unit can enter an oscillation state with a very high frequency, so that the comparator U1 outputs a Pulse Width Modulation (PWM) wave with a variable duty ratio and frequency. The voltage value of the voltage node Vcap is UCap, the resistance values of the first reference voltage dividing unit Rp1 and the second reference voltage dividing unit Rp2 are both Rp, and the resistance values of the positive feedback impedance unit RF + and the negative feedback impedance unit RF-are both RF. When the voltage of 2 capacitor subunits 121 in the energy storage capacitor unit is unbalanced, the output duty ratio and the output frequency of the comparator U1 will change accordingly, and the voltage of the capacitor subunit 121 fluctuates up and down within the following set error interval:

if the voltage of one of the capacitor sub-units 121 is slightly higher, the energy of the capacitor sub-unit will be absorbed by the filter inductor unit Lo and transferred to the other capacitor sub-unit 121 with lower voltage, so as to achieve energy transfer and voltage equalization.

In fig. 5, the first reference voltage dividing unit Rp1, the second reference voltage dividing unit Rp2, the positive feedback impedance unit RF +, and the negative feedback impedance unit RF-may be a single resistor as shown in fig. 5, or may be an assembly formed by a plurality of resistors; the oscillation capacitor unit Cosc may be a single capacitor as shown in fig. 5, or may be an assembly of a plurality of capacitors; the filter inductor unit Lo may be a single inductor as shown in fig. 5, or may be an assembly formed by multiple inductors, which is not limited herein.

In some embodiments, fig. 6 is a schematic structural diagram of another capacitor voltage equalizing unit provided in the embodiments of the present application. Fig. 7 is a schematic structural diagram of another capacitor voltage equalizing unit according to an embodiment of the present application. In the embodiment shown in fig. 5, to equalize the voltage of the energy storage capacitor unit with a larger capacitance, the capacitor voltage equalizing unit 14 needs a higher voltage equalizing capability. In order to improve the voltage equalizing effect on the energy storage capacitor unit, the capacitor voltage equalizing unit 14 shown in fig. 6 and 7 may further include a buffer unit 141. The output terminal of the comparator U1 is connected to the first terminal of the filter inductor unit Lo through the buffer unit 141. As shown in fig. 6 and 7, the input end of the buffer unit 141 is connected to the output end of the comparator U1, the output end is connected to the first end of the filter inductor unit Lo, and the addition of the buffer unit 141 reduces oscillation and improves the output capability of the rectified current of the capacitor voltage equalizing unit 14, so that the capacitor voltage equalizing unit 14 can realize voltage equalization of a capacitor bank with a larger capacity. The buffer unit 141 may be a Complementary Metal Oxide Semiconductor (CMOS) buffer circuit composed of two field effect transistors as shown in fig. 6, or may be a bipolar transistor buffer circuit composed of two transistors as shown in fig. 7. In comparison, in a capacitor bank voltage-sharing scenario with a lower voltage, a smaller loss can be realized by using the CMOS buffer circuit shown in fig. 6; in the voltage-sharing scenario of the capacitor bank with higher voltage, the bipolar transistor buffer circuit shown in fig. 7 can be used to achieve smaller loss.

Taking farad capacitor as the capacitor subunit 121 as an example, since the single farad capacitor withstand voltage is 2.5V, the withstand voltage of the capacitor bank obtained by equalizing the voltages of the two farad capacitors is 5V. If a capacitor bank with higher withstand voltage is required, a larger number of capacitors need to be connected in series and voltage-equalized. In the above embodiments of the voltage equalizing unit with or without the buffer unit 141, each capacitor subunit 121 in the energy storage capacitor unit may specifically include: 2n capacitor monomers and 2n-1 tree-shaped connected capacitor voltage-sharing units 14, wherein n is an integer larger than 0. It can be understood that, in this embodiment, tree-shaped connection may be performed on the voltage equalizing units, so as to implement expansion combination of the voltage equalizing structure and floating operation, thereby implementing voltage equalization on more than 2 capacitors. Taking the voltage equalizing unit without the buffering unit 141 as an example, fig. 8 is a schematic structural diagram of a tree-connected capacitor voltage equalizing unit according to an embodiment of the present application. In the tree connection structure shown in fig. 8, the first capacitor voltage equalizing unit 14a, the second capacitor voltage equalizing unit 14b, and the third capacitor voltage equalizing unit 14c are three capacitor voltage equalizing circuits having the same structure, the first storage capacitor CL1 and the second storage capacitor CL2 are connected in series to form one capacitor sub-unit 121, and the third storage capacitor CL3 and the fourth storage capacitor CL4 are connected in series to form another capacitor sub-unit 121. The first storage capacitor CL1, the second storage capacitor CL2, the third storage capacitor CL3, and the fourth storage capacitor CL4 are sequentially connected in series between the voltage node Vcap and the ground terminal. The first capacitor voltage equalizing unit 14a is connected between the second storage capacitor CL2 and the third storage capacitor CL3, the second capacitor voltage equalizing unit 14b is connected between the first storage capacitor CL1 and the second storage capacitor CL2, and the third capacitor voltage equalizing unit 14c is connected between the third storage capacitor CL3 and the fourth storage capacitor CL 4. The voltage node Vcap serves as a high-voltage end of the second capacitor voltage-sharing unit 14b, and a space between the second storage capacitor CL2 and the third storage capacitor CL3 serves as a ground end of the second capacitor voltage-sharing unit 14 b; the high-voltage terminal of the third storage capacitor CL3 is between the second storage capacitor CL2 and the third storage capacitor CL3, and the third storage capacitor CL3 is directly connected to the ground terminal. In the structure shown in fig. 8, each capacitor subunit 121 includes 2 capacitor cells and 1 capacitor voltage equalizing unit 14. If there are 4 capacitor units in the capacitor subunit 121, 3 tree-connected capacitor voltage equalizing units 14 are provided. In each capacitor subunit 121, for the voltage-sharing task of 2n capacitor cells, the number of capacitor voltage-sharing units 14 is required to be 1+2+4+ … 2^ (n-1), which is the summation of an equal ratio sequence with 2 as a common ratio, namely 2 n-1. For example, for the voltage equalizing task of 4 capacitor units, n is 2, and the number of capacitor voltage equalizing units 14 included in the capacitor subunit 121 is 4-1 or 3; for an 8 capacitor cell voltage equalization, n is 3, and the capacitor subunit 121 contains 8-1 or 7 capacitor voltage equalization units 14. In this embodiment, the capacitor voltage equalizing unit 14 equalizes voltage of each two capacitor units.

In the various embodiments described above, in the case where the drive voltage required by the target load is high, the drive apparatus needs to perform higher boosting processing on the power source terminal Vs voltage. In addition to boosting by charging with the above-described multiplexing circuit, boosting effect can be improved by introducing the pre-boosting unit 15. Fig. 9 is a schematic structural diagram of a pre-boosting driving apparatus according to an embodiment of the present application. As shown in fig. 9, the driving apparatus may further include a pre-booster unit 15. The multiplexing circuit is connected to the power source terminal Vs through the pre-booster unit 15. The pre-booster unit 15 is configured to boost the voltage of the power source terminal Vs and transmit the boosted voltage to the multiplexing circuit. For example, when the voltage of the power source terminal Vs is increased by 2-4 times by the pre-booster unit 15 and then sent to the multiplexing circuit to charge the energy storage capacitor unit, the current in the multiplexing circuit of this embodiment will be reduced to 1/2-1/4 compared with the original current in the structure without the pre-booster unit 15. The reduction of current in the circuit can realize the reduction of heating and the reduction of the size of the inductor of the energy storage capacitor unit, and further reduces the energy consumption of the circuit.

The pre-boosting unit 15 shown in fig. 9 may be a conventional DC/DC circuit, such as a boost circuit, but the power inductor occupies a large size, resulting in a large overall circuit size. The pre-boosting unit 15 can also be implemented by using a Switched Capacitor Converter (SCC), but the existing diode-switched capacitor converter has low efficiency due to the existence of the diode and needs to be used with the ac power supply. For electronic circuits, an alternating current power supply belongs to an inverter circuit, needs to occupy a certain size, and is used together with a diode array and a capacitor array which are large in size, so that the miniaturization of the circuit is difficult to realize. The diode and the capacitor in the existing diode switch capacitor converter need to bear two times of power supply voltage, the voltage stress is higher, and the cost is not favorable for optimization. In addition, the output impedance of the equivalent model of the diode type switched capacitor converter is high, which is not favorable for a high-power scene.

In order to realize the miniaturization of the structure and the application to the high-power scene, the pre-boosting unit 15 of the embodiment is implemented by introducing a field effect transistor bridge circuit. Fig. 10 is a schematic structural diagram of a pre-boosting unit according to an embodiment of the present application. As shown in fig. 10, the pre-boosting unit 15 specifically includes a first half-bridge control unit 151 and a second half-bridge energy storage unit 152. The first half-bridge control unit 151 is connected to the controller, the second half-bridge energy storage unit 152, the power source terminal Vs and the ground terminal, and is configured to transmit a power source voltage signal of the power source terminal Vs or a ground voltage signal of the ground terminal to the second half-bridge energy storage unit 152 in response to the control of the controller. The second half-bridge energy storage unit 152 is further connected to the controller, the multiplexing circuit, the dc terminal and the ground terminal, and configured to turn on the dc terminal for charging and storing energy in response to the control of the controller when the first half-bridge control unit 151 transmits the ground voltage signal, and turn on the ground terminal for boosting and discharging to output to the multiplexing circuit in response to the control of the controller when the first half-bridge control unit 151 transmits the power voltage signal.

The number of the second half-bridge energy storage units 152 may be 1 or more. If only one second half-bridge energy storage unit 152 is included in the pre-boosting unit 15, the dc terminal corresponding to the second half-bridge energy storage unit 152 is directly the power supply terminal Vs. For example, in fig. 10, 1 first half-bridge control unit 151 and 1 second half-bridge energy storage unit 152 implement a boost output for boosting the voltage of the power source terminal Vs by a factor of 2. If the number of the second half-bridge energy storage units 152 included in the pre-boosting unit 15 is M greater than 1, fig. 11 is a schematic diagram of another pre-boosting unit structure provided in the embodiment of the present application. As shown in fig. 11, the M second half-bridge energy storage units 152 are sequentially connected, each second half-bridge energy storage unit 152 is connected to the first half-bridge control unit 151, the dc terminal corresponding to the first second half-bridge energy storage unit 152 in sequence is the output terminal of the power supply unit, the dc terminals corresponding to the remaining M-1 second half-bridge energy storage units 152 are the output terminals of the second half-bridge energy storage unit 152 before in sequence, and the last second half-bridge energy storage unit 152 in sequence is connected to the multiplexing circuit. As shown in fig. 11, the second half-bridge memory cell in sequence is the last second half-bridge memory cell in sequence, and outputs a voltage 3 times the voltage of the power source terminal Vs. Every second half-bridge memory cell is added with 1 time of power supply voltage on the basis of the output voltage of the previous second half-bridge memory cell. Thus, by increasing the number of the second half-bridge memory cells sequentially connected in sequence, pre-boosting in which the output voltage is superimposed one by one at 1 power supply terminal voltage can be realized. A single second half-bridge memory cell in this embodiment may correspond to one voltage adder cell 153.

Specifically, as shown in fig. 10 or 11, the first half-bridge control unit 151 includes: a first gate driver 1511, a first field effect transistor G1, and a second field effect transistor G2. The first fet G1 and the second fet G2 are connected in series in the forward direction between the power source terminal Vs and the ground terminal. As shown in fig. 10 and 11, the forward series connection can be understood as the first fet G1 and the second fet G2 being connected in series and both being connected in the forward direction. The first fet G1 and the second fet G2 are both N-type fets. The first gate driver 1511 is used for converting the control signal outputted from the controller into gate driving signals for the first fet G1 and the second fet G2. Specifically, the high side driving signal output terminal (Vho) of the first gate driver 1511 is connected to the gate of the first fet G1, the half-bridge module output terminal (VS) of the first gate driver 1511 is connected between the first fet G1 and the second fet G2, the low side driving signal output terminal (Vlo) of the first gate driver 1511 is connected to the gate of the second fet G2, and the high side input terminal (Hin) and the low side input terminal (Lin) of the first gate driver 1511 are connected to the controller.

The second half-bridge energy storage unit 152 includes: the first flying capacitor Cfly1Cfly1, the first output capacitor Cout1Cout1, the second gate driver 1521, the coupling impedor Rd, the coupling capacitor Cd, the third fet G3 and the fourth fet G4. The third field effect transistor G3 and the fourth field effect transistor G4 are connected in series in reverse, the drain of the third field effect transistor G3 is connected to the ground terminal through the first output capacitor Cout1, and the source of the fourth field effect transistor G4 is connected to the dc terminal. As shown in fig. 10 and 11, the reverse series connection can be understood as the third fet G3 and the fourth fet G4 being connected in series and both being connected in reverse. The third fet G3 and the fourth fet G4 are also N-type fets. The second gate driver 1521 is used for converting the control signal output by the controller into gate driving signals for the third fet G3 and the fourth fet G4. A high-side driving signal output end (Vho) of the second gate driver 1521 is connected with a gate of the third fet G3, a low-side driving signal output end (Vlo) of the second gate driver 1521 is connected with a gate of the fourth fet G4 through a coupling capacitor Cd, one end of the coupling impedor Rd is connected with a direct current end, the other end of the coupling impedor Rd is connected between the fourth fet G4 and the coupling capacitor Cd, and a high-side input end (Hin) and a low-side input end (Lin) of the second gate driver 1521 are connected with the controller. One end of the first flying capacitor Cfly1 is connected to the half-bridge module output (VS) of the second gate driver 1521, and the other end is connected between the first fet G1 and the second fet G2.

In the first gate driver 1511 and the second gate driver 1521 of the embodiments shown in fig. 10 and fig. 11, the control signals input to the high-side input terminal (Hin) of each gate driver are synchronized with each other, the control signals input to the low-side input terminals (Lin) are synchronized with each other, and the control signals input to the high-side input terminal (Hin) and the control signals input to the low-side input terminals (Lin) are opposite. Therefore, the voltage of the power supply end is pre-boosted by controlling each field effect transistor in the pre-boosting unit 15. Specifically, for example, when the second fet G2 and the fourth fet G4 are controlled to be turned on and the first fet G1 and the third fet G3 are controlled to be turned off, the power source terminal Vs charges the first flying capacitor Cfly1 in the second half-bridge energy storage unit 152, so that the voltage polarity is left negative and right positive. When the first field effect transistor G1 and the third field effect transistor G3 are controlled to be turned on and the second field effect transistor G2 and the fourth field effect transistor G4 are controlled to be turned off, the power source terminal Vs is connected in series with the first flying capacitor Cfly1 with the voltage between two ends being Vs, the third field effect transistor G3 outputs the voltage of 2Vs to charge the first output capacitor Cout1, and the 2Vs output shown in fig. 10 or the 3Vs output shown in fig. 11 is realized. In the above process, the "inverted half-bridge" formed by the reverse connection of the third fet G3 and the fourth fet G4 shown in fig. 10 and 11 realizes a special synchronous rectification network. The fet is operated in a synchronous rectification mode, i.e., the body diode of the fourth fet G4 is shielded by the conduction of the fourth fet G3, and the body diode of the third fet G3 is shielded by the conduction of the fourth fet.

As shown in fig. 10 and 11, since the fourth fet G4 is an NMOS whose source is connected to a positive voltage, a driving voltage higher than Vs is required for the gate to turn on the fourth fet G4. However, the high-side driving signal output terminal (Vho) of the second gate driver 1521 is already occupied by the third fet G3, so the ac coupling network formed by the coupling resistor Rd and the coupling capacitor Cd, and the ac driving component provided by the low-side driving signal output terminal (Vlo) of the second gate driver 1521 are utilized in the above embodiment to provide the driving voltage for the fourth fet G4. The coupling capacitor Cd isolates a direct-current component output by the low-side drive signal output end (Vlo), and finally, a drive voltage with the amplitude of Vd/2 is coupled out from the gate of the fourth fet G4, so that the fourth fet G4 is driven. The low side driving signal output terminal (Vlo) of the second gate driver 1521 outputs Vd, and the high side driving signal output terminal (Vho) of the second gate driver 1521 outputs Vd with respect to the half bridge module output terminal (VS). For example, Vd is 12V, and the gate voltage passed by capacitive coupling is 6V.

In the above embodiments, both the first gate driver 1511 and the second gate driver 1521 may be bootstrap gate drivers, thereby reducing hardware costs.

In some embodiments of the bootstrap gate driver, the first half-bridge control unit 151 further includes a first bootstrap diode Db1 and a first isolation capacitor Cb 1. As shown in fig. 10 and 11, the anode of the first bootstrap diode Db1 is connected to the chip power supply terminal (Vd) of the first gate driver 1511, and the cathode thereof is connected to the floating power supply terminal (Vb) of the first gate driver 1511. One end of the first isolation capacitor Cb1 is connected to the floating power supply terminal (Vb) of the first gate driver 1511, and the other end is connected to the half-bridge module output terminal (VS) of the first gate driver 1511, wherein the chip power supply terminal (Vd) of the first gate driver 1511 is further connected to the first power supply terminal (Vd in the figure, the first power supply terminal and the voltage value provided by the first power supply terminal are also illustrated by Vd). As shown in fig. 10 and 11, the second half-bridge control unit may further include a second bootstrap diode Db2 and a second isolation capacitor Cb 2. The anode of the second bootstrap diode Db2 is connected to the second power supply terminal (Vd + Vs indicates the second power supply terminal and the voltage value provided by the second power supply terminal), and the cathode is connected to the floating power supply terminal (Vb) of the second gate driver 1521. One end of the second isolation capacitor Cb2 is connected to the floating power supply terminal (Vb) of the second gate driver 1521, and the other end is connected to the half-bridge module output terminal (VS) of the second gate driver 1521; the chip power supply terminal (Vb) of the second gate driver 1521 is further connected to the first power supply terminal, and the voltage of the second power supply terminal is the sum of the voltage of the power supply terminal and the voltage of the first power supply terminal. Since the reference minimum voltage of the third fet G3 is Vs instead of ground, the voltage required to be connected to the bootstrap diode of the bootstrap driver for driving the third fet G3 is Vd + Vs, where Vd may be the voltage required to fully turn on the fet. And Vd is also the voltage value provided by the first power supply terminal. In this embodiment, gate driving of the field effect transistor is realized by means of ac coupling and bootstrap combination.

In the embodiments shown in fig. 10 and 11, each fet may be a silicon fet, or may be a novel wide bandgap semiconductor device such as gallium nitride and silicon carbide, which is not limited herein. The first gate driver 1511 and the second gate driver 1521 may be connected in series with an additional damping resistor or a fast bleeder diode, or may be connected in parallel with components such as a zener diode, which is not limited herein.

In other embodiments of the pre-boosting unit 15, unlike the structures shown in fig. 10 and 11, the pre-boosting unit 15 may be implemented by introducing a P-type field effect transistor, so that the cost of the gate driver may be reduced and the size of the gate driver may be reduced. Fig. 12 is a schematic structural diagram of another pre-boosting unit according to an embodiment of the present application. Fig. 13 is a schematic structural diagram of another pre-boosting unit according to an embodiment of the present application. The pre-boosting unit 15 may specifically include a single or a plurality of basic voltage doubling units 153.

In some embodiments where the pre-booster unit 15 includes a single substantially voltage-doubling unit 153, as shown in fig. 12, the multiplexing circuit is connected through the single substantially voltage-doubling unit 153 to a power supply terminal Vs, which is a voltage-doubling front power supply terminal of the single substantially voltage-doubling unit 153. The voltage doubling unit 153 is used to boost the voltage of the power source by 2 times and transmit the boosted voltage to the multiplexing circuit.

In some embodiments where the pre-boosting unit 15 includes a plurality of basic voltage doubling units 153, as shown in fig. 13, the pre-boosting unit 15 specifically includes K basic voltage doubling units 153 sequentially connected in sequence, where K is an integer greater than 1. The structure shown in fig. 13 can be understood as an extension of the structure shown in fig. 12. The sequential connection may be in a specific manner as illustrated in fig. 13, each of the basic voltage doubling units 153 is connected to the controller, the voltage-doubling front power supply end connected to the first basic voltage doubling unit 153 is the power supply end Vs, the voltage-doubling front power supply end connected to the second basic voltage doubling unit 153 is the output end of the first basic voltage doubling unit 153, and so on, and then the voltage-doubling front power supply end of each of the basic voltage doubling units 153 is the output end of the previous basic voltage doubling unit 153, thereby realizing the voltage boosting of the power supply end by 2K times. Specifically, the multiplexing circuit is connected to the power source terminal Vs through K basic voltage doubling units 153 sequentially connected in sequence, for example. The K sequentially connected basic voltage doubling units 153 are used for boosting the voltage of the power supply terminal by 2K times and transmitting the boosted voltage to the multiplexing circuit. Among the K sequential basic voltage doubling units 153, the first sequential basic voltage doubling unit 153 is connected to the power source terminal Vs and the ground terminal, and is configured to boost the voltage at the power source terminal by 2 times and output the boosted voltage. The remaining K-1 basic voltage doubling units 153 are connected to the ground and the voltage doubling output terminal of the previous basic voltage doubling unit 153, and are configured to output the output voltage of the previous basic voltage doubling unit 153 superimposed with the power supply terminal voltage by 2 times. The power source terminal Vs is the voltage-multiplying front power supply terminal of the first sequential basic voltage-doubling unit 153, and the voltage-multiplying output terminal of the first sequential basic voltage-doubling unit 153 is the voltage-multiplying front power supply terminal of the remaining K-1 basic voltage-doubling units 153.

As shown in fig. 12, the basic voltage doubling unit 153 specifically includes: a fifth field effect transistor G5, a sixth field effect transistor G6, a seventh field effect transistor G7, an eighth field effect transistor G8, a first filter resistor R1, a second filter resistor R2, a third filter resistor R3, a fourth filter resistor R4, a first filter capacitor C31, a second filter capacitor C32, a third filter capacitor C33, a fourth filter capacitor C34, a second output capacitor Cout2, and a second flying capacitor Cfly 2. The fifth field effect transistor G5 and the sixth field effect transistor G6 are connected in series between the voltage-multiplying front power supply terminal and the ground terminal in the forward direction, the seventh field effect transistor G7 and the eighth field effect transistor G8 are connected in series between the voltage-multiplying front power supply terminal and the ground terminal in the reverse direction, and the eighth field effect transistor G8 is connected to the ground terminal through the second output capacitor Cout 2. The forward series connection means that the fifth field effect transistor G5 and the sixth field effect transistor G6 are connected in series and are connected positively; the reverse series connection means that the seventh field effect transistor G7 and the eighth field effect transistor G8 are connected in series and are connected in reverse. The fifth field-effect tube G5 and the eighth field-effect tube G8 are P-type field-effect tubes; the sixth fet G6 and the seventh fet G7 are N-type fets. One end of the first filter resistor R1 is connected with the voltage-multiplying front power supply end, the other end is connected with the controller through the first filter capacitor C31, and the grid of the fifth field effect transistor G5 is connected between the first filter resistor R1 and the first filter capacitor C31. One end of the second filter resistor R2 is connected to the ground, the other end is connected to the controller through the second filter capacitor C32, and the gate of the sixth fet G6 is connected between the second filter resistor R2 and the second filter capacitor C32. One end of the third filter resistor R3 is connected with the voltage-multiplying front power supply end, the other end is connected with the controller through a third filter capacitor C33, and the grid of the seventh field effect transistor G7 is connected between the third filter resistor R3 and the third filter capacitor C33. One end of the fourth filter resistor R4 is connected to the ground terminal through the second output capacitor Cout2, the other end is connected to the controller through the fourth filter capacitor C34, and the gate of the eighth fet G8 is connected between the fourth filter resistor R4 and the fourth filter capacitor C34. A first terminal of a second flying capacitor Cfly2 is connected between fifth fet G5 and sixth fet G6, and a second terminal of the second flying capacitor Cfly2 is connected between seventh fet G7 and eighth fet G8.

In the basic voltage doubling unit 153 shown in fig. 12, the fifth fet G5, the sixth fet G6, the seventh fet G7, and the eighth fet G8 are MOS transistors, wherein the fifth fet G5 and the eighth fet G8 are PMOS transistors, and the sixth fet G6 and the seventh fet G7 are NMOS transistors. The first filter resistor R1, the second filter resistor R2, the third filter resistor R3, the fourth filter resistor R4, the first filter capacitor C31, the second filter capacitor C32, the third filter capacitor C33 and the fourth filter capacitor C34 form an RC high-pass filter in pairs. The voltage-multiplying front power supply end in fig. 12 is a power supply end Vs, and a control signal sent from the controller is connected between the first filter capacitor C31 and the second filter capacitor C32, and between the third filter capacitor C33 and the fourth filter capacitor C34, so as to realize synchronous control of the fifth fet G5, the sixth fet G6, the seventh fet G7, and the eighth fet G8. The voltage of the output value multiplexing unit after the voltage doubling of the basic voltage doubling unit 153 is 2 Vs. The controller sends out a control signal to drive the fifth field-effect tube G5, the sixth field-effect tube G6, the seventh field-effect tube G7 and the eighth field-effect tube G8 through the high-pass filter, and the first filter capacitor C31, the second filter capacitor C32, the third filter capacitor C33 and the fourth filter capacitor C34 bear the pressure difference between the control signal and the voltage rail. Due to the inverse of the NMOS and PMOS turn-on conditions, when the sixth fet G6 and the seventh fet G7 are turned on simultaneously, the fifth fet G5 and the eighth fet G8 are turned off, the power source terminal Vs charges the second flying capacitor Cfly2 through the sixth fet G6 and the seventh fet G7, and the voltage polarity of the second flying capacitor Cfly2 is positive, negative, and positive. When the fifth field effect transistor G5 and the eighth field effect transistor G8 are turned on, the sixth field effect transistor G6 and the seventh field effect transistor G7 are turned off, and at this time, the power source terminal Vs is connected in series with the second flying capacitor Cfly2 which is negative on the left and positive on the right to charge the second output capacitor Cout2, and the output voltage on the second output capacitor Cout2 is 2Vs, that is, 2 times of the input voltage.

In the above embodiment of the basic voltage doubling unit 153, the first terminal of the second flying capacitor Cfly2 also forms an inverted pulse output terminal for outputting a pulse signal having the same voltage value as the voltage at the power supply and having a phase opposite to the signal input to the voltage doubling unit by the controller. A pulse signal having an amplitude Vs and a phase opposite to the control signal can thus be extracted from the substantially voltage doubling unit 153. In the embodiment of the substantially voltage doubling unit 153 shown in fig. 12 and 13, only one control signal needs to be input to the substantially voltage doubling unit 153, thereby reducing the complexity of the control circuit.

On the basis of leading out the inverted pulse output end, fig. 14 is a schematic diagram of a structure of another pre-boosting unit provided in the embodiment of the present application. The pre-boosting unit 15 shown in fig. 14 may further include: adder units corresponding to the basic voltage doubling units 153 one to one, and T +1 switch selectors, T being the number of adder units. The T adder units are connected in sequence, and each adder unit is connected to the reverse pulse output terminal of a basic voltage doubling unit 153 through a switch selector. The last adder unit in sequence is further connected with the voltage-multiplying output end of the last basic voltage-multiplying unit 153 in sequence through a switch selector, the adding output ends of the rest T-1 adder units are connected with the input end of the adder unit in front of the sequence, and the adding output end of the first adder unit in sequence is connected with the multiplexing circuit. The T +1 switch selectors are used for controlling the voltage output by the addition output end of the sequential first adder unit to the multiplexing circuit.

For example, on the basis of the single basic voltage doubling unit 153 shown in fig. 12, only 1 adder unit and 2 switching selectors may be added, thereby realizing pre-boosting of 0-3 times Vs by gating the switching selectors.

For example, in addition to the plurality of basic voltage doubling units 153 shown in fig. 13, the number of adder units is also plural. When T basic voltage doubling units 153 with reverse pulse output ends are connected in sequence, T +1 direct current voltage outputs are provided, and the magnitudes of the direct current voltage outputs are 2^T,2^T,2^T… 2 Vs 2,2,1 times, having T-way inverted pulse signal output with peak values of 2^T… 2 Vs 2,2,1 times, in combinationThe T adder units can obtain a T +1 bit digital voltage multiplier. Taking fig. 14 as an example, the pre-boosting unit 15 includes 4 basic voltage doubler units 153, 4 adder units, and 5 switch selectors (D00, D01, D02, D03, D04), so that voltage doubler of any integer multiple of 0 to 63 times the voltage of the power supply terminal can be realized. Assuming that 3 times the voltage of the power supply terminal, i.e., 3Vs, is to be output to the multiplexing circuit, D00 and D01 are controlled to be connected to their corresponding inverted pulse output terminals, and the other switch selectors are grounded. In this way, the configuration of the pre-boost output can be achieved by the configuration of the switch selector. By analogy, a digital voltage multiplier with eight, ten, twelve or even higher digits can be realized.

In the various embodiments of pre-boosting shown in fig. 12 to 14, the control signal lines are simple to wire, so that the anti-interference capability of the lines is improved, and the circuit size is reduced.

Fig. 15 is a schematic structural diagram of an adder unit according to an embodiment of the present application. The adder unit 153 shown in fig. 15 specifically includes: a third flying capacitor Cfly3, a ninth fet G9, a tenth fet G10, a fifth filter resistor R5, a sixth filter resistor R6, a fifth filter capacitor C35, a sixth filter capacitor C36, and a summing capacitor C +. The ninth fet G9 and the tenth fet G10 are connected in series and in reverse between the summing input terminal and the ground terminal, and the tenth fet G10 is connected to the ground terminal through the summing capacitor C +. Here, the reverse series connection is that the ninth fet G9 and the tenth fet G10 are connected in series with each other and are connected in reverse. One end of the fifth filter resistor R5 is connected to the summing input (the voltage at the summing input is indicated by V1 in the figure), the other end is connected to the controller through a fifth filter capacitor C35, and the gate of the ninth fet G9 is connected between the fifth filter resistor R5 and the fifth filter capacitor C35. One end of the sixth filter resistor R6 is connected to the ground through the addition capacitor C +, the other end is connected to the controller through the sixth filter capacitor C36, and the gate of the tenth fet G10 is connected between the sixth filter resistor R6 and the sixth filter capacitor C36. The third flying capacitor Cfly3 has one end connected to the inverted pulse output terminal of the voltage doubling unit 153 (the voltage of the inverted pulse output terminal is indicated by V2), and the other end connected between the ninth fet G9 and the tenth fet G10. Wherein, the ninth fet G9 is an N-type fet, and the tenth fet G10 is a P-type fet. The end of the summing capacitor C + connected to the tenth fet G10 is the summing output of the adder unit 153 (the voltage at the summing output is shown schematically as V1+ V2).

In the adder unit 153 shown in fig. 15, two of the fifth impedance filter R5, the sixth impedance filter R6, the fifth filter capacitor C35, and the sixth filter capacitor C36 constitute a high-pass filter. For example, when the control signal sent by the controller is at a high level, the pulse signal with the peak value V2 provided by the inverted pulse output terminal of the voltage doubling unit 153 is at a low level, the ninth fet G9 is turned on, and the addition input terminal charges the third flying capacitor Cfly3 through the ninth fet G9, and the polarity is left negative and right positive; when the control signal is at a low level, the tenth fet G10 is turned on, the inverted pulse output terminal of the voltage doubling unit 153 provides the pulse signal with the peak value V2 at a high level, V2 is connected in series with the third flying capacitor Cfly3 with a voltage at both ends V1, and then the voltage is output to the adding capacitor C +, and the voltage at the adding capacitor C + is V1+ V2, thereby realizing the voltage addition. The adder unit 153 needs a direct current voltage V1 and a pulse signal with a peak value of V2, and V2 needs to be inverted with respect to the control signal received by the adder from the controller, so that the voltage of V1+ V2 can be finally output, and the voltage addition in the pre-booster unit 15 is realized.

The ninth fet G9 and the tenth fet G10 may be silicon fets, or may be novel wide bandgap semiconductor devices such as gallium nitride and silicon carbide, which are not limited herein.

Fig. 16 is a schematic diagram of a chip structure according to an embodiment of the present application. The present application further provides a chip 20 as shown in fig. 16, including the driving device 10 according to any of the above embodiments. The chip may specifically be a driver chip for a target load. The chip 20 may be, for example, a flash chip, a shutter chip, a magnetron chip, etc., and is not limited herein.

Fig. 17 is a schematic structural diagram of a shooting device according to an embodiment of the present application. The camera 30 shown in fig. 17 includes a target load, and the chip 20 or the driving device 10 according to any of the above embodiments. In fig. 17, the imaging device 30 includes the chip 20 as an example.

It should be understood that the present application can be applied to various application scenarios of instantaneous high pulse power driving, and the camera is only an example of one application scenario, and the present application is not limited thereto.

Fig. 18 is a schematic structural diagram of an unmanned aerial vehicle provided in an embodiment of the present application. The unmanned aerial vehicle shown in fig. 18 includes a main body 40 and the camera 30 mounted on the main body 40.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

It should be understood that, in this application, "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in this application, "plurality" means two or more.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.