阅读说明：本技术 一种具有隐埋层的brt及其制造方法 (BRT with buried layer and manufacturing method thereof ) 是由 王彩琳 杨武华 刘园园 张如亮 于 2021-08-10 设计创作，主要内容包括：本发明公开了一种具有隐埋层的BRT,n～(-)漂移区上部设有p基区及n～(+)阴极区；n～(-)漂移区上部的p基区的两侧设有与p基区两侧相接触的隐埋层；在隐埋层上方靠外侧设有p～(++)分流区,两侧的p～(++)分流区上表面铝层与n～(+)阴极区上表面铝层连成阴极K；部分n～(+)阴极区、p基区及部分p～(++)分流区上表面共同设有栅氧化层及多晶硅层的栅极G；阴极K与栅极G之间设有磷硅玻璃层；在n～(-)漂移区下表面依次设有nFS层、p～(+)阳极区和金属化阳极A；该隐埋层选用N型的掺杂层；或者选用隐埋二氧化硅层。本发明还公开了该种具有隐埋层BRT的制造方法。本发明的BRT,有效抑制了电压折回现象,降低了器件通态压降并提高开关速度,从而降低了能耗。(The invention discloses a BRT, n with a buried layer ‑ The upper part of the drift region is provided with a p base region and n + A cathode region; n is ‑ Buried layers which are contacted with the two sides of the p base region are arranged on the two sides of the p base region on the upper part of the drift region; p is arranged above the buried layer and close to the outer side ++ Shunting region, p on both sides ++ The aluminum layer and n on the upper surface of the shunting region + The aluminum layer on the upper surface of the cathode region is connected into a cathode K; part n + Cathode region, p-base region and part of p ++ The upper surface of the shunting region is provided with a gate oxide layer and a grid G of a polycrystalline silicon layer together; a phosphorosilicate glass layer is arranged between the cathode K and the grid G; at n ‑ nFS layers and p are sequentially arranged on the lower surface of the drift region + An anode region and a metallized anode A; theThe buried layer is an N-type doped layer; or a buried silicon dioxide layer is selected. The invention also discloses a manufacturing method of the BRT with the buried layer. The BRT effectively inhibits the voltage folding phenomenon, reduces the on-state voltage drop of the device, and improves the switching speed, thereby reducing the energy consumption.)

1. A BRT having a buried layer, characterized by: with n^-Drift region as substrate, in n^-A p-base region is arranged at the middle position of the upper part of the drift region, and n is arranged at the middle position of the upper part of the p-base region⁺A cathode region; at n^-Buried layers which are contacted with the two sides of the p base region are respectively arranged on the two sides of the p base region on the upper part of the drift region; p is arranged above the buried layer and close to the outer side⁺⁺Shunting region, p on both sides⁺⁺Aluminum layer on upper surface of shunt region and n⁺The aluminum layers in the middle of the upper surface of the cathode region are connected to form a cathode K; part n⁺Cathode region, p-base region and part of p⁺⁺A layer of gate oxide layer is arranged on the upper surfaces of the shunting areas together, and a heavily doped polycrystalline silicon layer is arranged on the upper surface of the gate oxide layer and serves as a grid G; a phosphosilicate glass (PSG) layer is arranged between the cathode K and the grid G; at n^-nFS layers are arranged on the lower surface of the drift region, and p is arranged on the lower surface of the nFS layer⁺Anode region at p⁺The lower surface of the anode region is provided with a plurality of layers of metallized anodes A;

the buried layer selects an N-type doped layer as a current carrier storage layer, which is called a buried N-type current carrier storage layer for short; or a buried silicon dioxide layer is selected as a carrier blocking layer, which is called a buried oxide layer for short.

2. The BRT with buried layer of claim 1, wherein: the concentration of the buried N-type carrier storage layer is 2 x 10¹⁵cm^-3～9×10¹⁵cm^-3The thickness is 0.6 to 2 μm.

3. The BRT with buried layer of claim 1, wherein: the lateral spacing deviation Delta x between the buried N-type carrier storage layer and the p base region is-0.25 to 1.5 mu m; buried N-type carrier storage layer and p⁺⁺The longitudinal spacing deltay of the shunting region is 0.5 to 2 μm.

4. The BRT with buried layer of claim 1, wherein: the thickness of the buried silicon dioxide layer is 0.5 μm.

5. The device of claim 1 having a buried layerBRT, characterized by: the lateral spacing deviation Delta x between the buried silicon dioxide layer and the p base region is-0.5 to 1.5 mu m; buried silicon dioxide layer and p⁺⁺The longitudinal spacing deltay of the shunting region is 0 to 1.5 mu m.

6. A method of fabricating a BRT with a buried layer according to any of claims 1 to 5, embodied in the following steps:

step 1, selecting an original high-resistance zone melting medium silicon single crystal polished wafer as n^-Drift region, pre-processed n^-Injecting phosphorus ions on the lower surface of the drift region, annealing and propelling, and forming nFS layers on the lower surface;

step 2, removing the oxide layer on the surface of the silicon wafer treated in the step 1, and forming sacrificial oxide layers on the upper surface and the lower surface by adopting dry oxygen oxidation;

step 3, photoetching is carried out on the upper surface of the silicon wafer processed in the step 2, boron ion injection windows of the p base region and the terminal field ring region are formed, and boron ion injection is carried out by adopting photoresist masking; then, boron ion implantation is carried out on the lower surface, annealing and propulsion are carried out after photoresist is removed, and a selective p base region is formed on the upper surface of the silicon chip, so that p is formed on the lower surface⁺An anode region;

step 4, forming n completely identical to the p base region injection window on the upper surface of the silicon wafer processed in the step 3 through photoetching⁺Injecting phosphorus ion into the window of the cathode region, then adopting photoresist to mask the window, removing photoresist, then advancing and annealing to form n⁺A cathode region implementing a self-aligned N channel;

step 5, forming an ion implantation window of the N-type buried layer on the upper surface of the silicon wafer processed in the step 4 through photoetching, performing high-energy phosphorus ion or oxygen ion implantation by utilizing photoresist masking, and forming a buried N-type carrier storage layer or a buried silicon dioxide layer by adopting an inverse doping process;

step 6, removing the oxide layer on the surface of the silicon wafer treated in the step 5, carrying out dry oxygen oxidation again, then forming a polycrystalline silicon layer by adopting chemical vapor deposition, and doping;

step 7, photoetching the upper surface of the silicon wafer processed in the step 6, removing the polycrystalline silicon layer and reserving the grid oxide layer to form p⁺⁺Injecting boron ions into the window of the shunting region, then adopting photoresist to mask the window for boron ion injection, and annealing after removing the photoresist to form p⁺⁺A shunting region;

8, depositing phosphorosilicate glass on the upper surface of the silicon wafer treated in the step 7, and refluxing to realize cell surface planarization;

step 9, photoetching the upper surface of the silicon wafer processed in the step 8 to form a cathode contact hole, performing secondary reflux, depositing a metal aluminum layer on the upper surface, reversely etching, sputtering four layers of metalized films of aluminum, titanium, nickel and silver on the lower surface in sequence, forming a metalized cathode K on the upper surface and forming a multi-layer metalized anode A on the lower surface after alloying;

and step 10, throwing a polyimide film on the upper surface of the silicon wafer processed in the step 9, forming a pressure welding area pattern of a grid electrode and a cathode by photoetching, carrying out polyimide curing treatment, carrying out passivation protection on the surface of a terminal area, and scribing to obtain the silicon wafer.

Technical Field

The invention belongs to the technical field of power semiconductor devices, relates to a BRT with a buried layer, and further relates to a manufacturing method of the BRT with the buried layer.

Background

The base resistance controlled thyristor (BRT) is another MOS-gated thyristor developed on the basis of the existing MOS-controlled thyristor (MCT). Compared with MCT, although the fabrication process of BRT is greatly simplified, a very serious voltage foldback (Snapback) phenomenon still exists at low current, resulting in a slow turn-on speed and large turn-on loss.

Disclosure of Invention

The invention aims to provide a BRT with a buried layer, which solves the problems of low opening speed and large opening loss caused by the structural limitation of the BRT in the prior art.

Another object of the present invention is to provide a method for manufacturing such a BRT with a buried layer.

The invention adopts the technical scheme that the BRT with the buried layer is n^-Drift region as substrate, in n^-A p-base region is arranged at the middle position of the upper part of the drift region, and n is arranged at the middle position of the upper part of the p-base region⁺A cathode region; at n^-Buried layers which are contacted with the two sides of the p base region are respectively arranged on the two sides of the p base region on the upper part of the drift region; p is arranged above the buried layer and close to the outer side⁺⁺Shunting region, p on both sides⁺⁺Aluminum layer on upper surface of shunt region and n⁺The aluminum layers in the middle of the upper surface of the cathode region are connected to form a cathode K; part n⁺Cathode region, p-base region and part of p⁺⁺A layer of gate oxide layer is arranged on the upper surfaces of the shunting areas together, and a heavily doped polycrystalline silicon layer is arranged on the upper surface of the gate oxide layer and serves as a grid G; a phosphosilicate glass (PSG) layer is arranged between the cathode K and the grid G; at n^-nFS layers are arranged on the lower surface of the drift region, and p is arranged on the lower surface of the nFS layer⁺Anode region at p⁺The lower surface of the anode region is provided with a plurality of layers of metallized anodes A;

the buried layer selects an N-type doped layer as a current carrier storage layer, which is called a buried N-type current carrier storage layer for short; or a buried silicon dioxide layer is selected as a carrier blocking layer, which is called a buried oxide layer for short.

The invention adopts another technical scheme that the manufacturing method of the BRT with the buried layer is specifically implemented according to the following steps:

step 1, selecting an original high-resistance zone melting medium silicon single crystal polished wafer as n^-Drift region, pre-processed n^-Injecting phosphorus ions on the lower surface of the drift region, annealing and propelling, and forming nFS layers on the lower surface;

step 2, removing the oxide layer on the surface of the silicon wafer treated in the step 1, and forming sacrificial oxide layers on the upper surface and the lower surface by adopting dry oxygen oxidation;

step 3, photoetching is carried out on the upper surface of the silicon wafer processed in the step 2, boron ion injection windows of the p base region and the terminal field ring region are formed, and boron ion injection is carried out by adopting photoresist masking; then, boron ion implantation is carried out on the lower surface, high-temperature annealing and propulsion are carried out after photoresist stripping, a selective p base region is formed on the upper surface of the silicon chip, and p is formed on the lower surface⁺An anode region;

step 4, forming n completely identical to the p base region injection window on the upper surface of the silicon wafer processed in the step 3 through photoetching⁺Injecting phosphorus ion into the window of the cathode region, then adopting photoresist to mask the window, removing photoresist, and then carrying out high-temperature propulsion and annealing to form n⁺A cathode region implementing a self-aligned N channel;

step 5, forming an ion implantation window of an N-type buried layer on the upper surface of the silicon wafer processed in the step 4 through photoetching, performing high-energy phosphorus ion or oxygen ion implantation by utilizing photoresist masking, and forming a buried N-type carrier storage layer BN-CS or a buried silicon dioxide layer BOX by adopting an inverse doping process;

step 6, removing the oxide layer on the surface of the silicon wafer treated in the step 5, carrying out dry oxygen oxidation again, then forming a polycrystalline silicon layer by adopting chemical vapor deposition, and doping;

step 7, photoetching the upper surface of the silicon wafer processed in the step 6, removing the polycrystalline silicon layer and reserving the grid oxide layer to form p⁺⁺Boron ion implantation window of shunt regionOpening, implanting boron ions by masking with photoresist, removing photoresist, and annealing to form p⁺⁺A shunting region;

step 8, depositing phosphorosilicate glass on the upper surface of the silicon wafer treated in the step 7, and refluxing at high temperature to realize cell surface planarization;

step 9, photoetching the upper surface of the silicon wafer processed in the step 8 to form a cathode contact hole, performing secondary reflux, depositing a metal aluminum layer on the upper surface, reversely etching, sputtering four layers of metalized films of aluminum, titanium, nickel and silver on the lower surface in sequence, forming a metalized cathode K on the upper surface and forming a multi-layer metalized anode A on the lower surface after alloying;

and step 10, throwing a polyimide film on the upper surface of the silicon wafer processed in the step 9, forming a pressure welding area pattern of a grid electrode and a cathode by photoetching, carrying out polyimide curing treatment, carrying out passivation protection on the surface of a terminal area, and scribing to obtain the silicon wafer.

The invention has the beneficial effect that the introduction of the buried layer can play a role of blocking holes from being p when the device is conducted⁺⁺The action of the extraction of the shunt area enables the device to generate an electron Injection Enhancement (IE) effect similar to an IGBT, and the conduction of the thyristor is accelerated, so that the voltage retracing phenomenon is restrained. The IGBT device has the advantages of very low on-state voltage drop, high turn-off speed, complete compatibility of the manufacturing process and the IGBT, low process cost and suitability for practical application. The device structure of the invention not only has simple driving circuit, but also has low on-state voltage drop and high switching speed, and can effectively inhibit voltage retrace (Snapback) phenomenon of BRT and improve the compromise relation of the on-state voltage drop and the turn-off energy consumption.

Drawings

FIG. 1 is a schematic diagram of the basic structure of a prior art base resistance controlled thyristor (BRT);

FIG. 2 is a schematic diagram of the basic structure of a BRT with a buried layer according to the present invention;

FIG. 3 is a forward blocking characteristic curve of a BRT with a buried N-type carrier storage layer (hereinafter, referred to as BN-CS-BRT) and a BRT with a buried silicon dioxide layer (hereinafter, referred to as BOX-BRT) of the present invention and a prior art BRT at normal temperature (300K) and high temperature (400K);

FIG. 4 is a comparison curve of ON-state characteristics of BN-CS-BRT and BOX-BRT of the present invention versus prior art BRT at normal temperature (300K) and high temperature (400K);

FIG. 5 shows the cathode side electron injection efficiency γ of the BN-CS-BRT and BOX-BRT of the present invention and the BRT of the prior art_nCurrent density J with cathode_KComparing the change curves;

FIG. 6 shows the anode side hole injection efficiency γ of the BN-CS-BRT and BOX-BRT of the present invention and the prior art BRT_pCurrent density J with anode_AComparing the change curves;

FIG. 7 is the concentration of the buried N-type carrier storage layer of the BN-CS-BRT of the invention versus the device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (a);

FIG. 8 is thickness of buried N-type carrier storage layer of BN-CS-BRT of the invention versus device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (a);

FIG. 9 shows the on-state voltage drop and minority carrier lifetime τ of BN-CS-BRT and BOX-BRT of the present invention and BRT of the prior art_p0The relationship curve of (1);

FIG. 10 is a graph comparing the BN-CS-BRT and BOX-BRT of the present invention with prior art BRT on-state voltage drop versus turn-off loss trade-off;

FIG. 11 is a lateral spacing deviation Deltax of a buried N-type carrier storage layer and a p-base region of the BN-CS-BRT of the invention versus the on-state voltage drop V of the device_TAnd breakdown voltage V_BRThe influence of (a);

FIG. 12 shows a buried N-type carrier storage layer and p of BN-CS-BRT according to the present invention⁺⁺Longitudinal spacing Deltay of shunting region to device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (a);

FIG. 13 is a plot of lateral spacing deviation Δ x of buried oxide and p-base regions versus device on-state voltage drop V for the BOX-BRT of the present invention_TAnd breakdown voltage V_BRThe influence of (a);

FIG. 14 shows a buried oxide layer and p of the BOX-BRT of the present invention⁺⁺Longitudinal spacing Deltay of shunting region to device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (a);

fig. 15 is a schematic process flow diagram of the fabrication of a BRT with a buried layer according to the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, the main structure of a base resistance controlled thyristor (BRT) of the prior art is formed by n⁺Cathode region, p-base region, n^-Drift region, nFS layers and p⁺An anode region, wherein p⁺⁺Shunting region and n⁺The cathode regions are connected through an aluminum layer to form a cathode; heavily doped polysilicon layer and its lower gate oxide layer and n^-The drift region and the p-base region respectively form a pMOS and an nMOS and are controlled by the same grid voltage.

Referring to fig. 2, the BRT with buried layer of the present invention has a structure in which the entire device is formed with n^-Drift region as substrate, in n^-A p-base region is arranged at the middle position of the upper part of the drift region, and n is arranged at the middle position of the upper part of the p-base region⁺A cathode region; at n^-Buried layers which are contacted with the two sides of the p base region are respectively arranged on the two sides of the p base region on the upper portion of the drift region, the buried layers are N-type doped layers or silicon dioxide layers, and the buried layers refer to BN-CS or BOX shown in figure 2; p is arranged above the buried layer and close to the outer side⁺⁺Shunting region, p on both sides⁺⁺Aluminum layer on upper surface of shunt region and n⁺The aluminum layers in the middle of the upper surface of the cathode region are connected to form a cathode K; part n⁺Cathode region, p-base region and part of p⁺⁺A layer of gate oxide layer is arranged on the upper surfaces of the shunting areas together, and a heavily doped polycrystalline silicon layer is arranged on the upper surface of the gate oxide layer and serves as a grid G; a phosphosilicate glass (PSG) layer is arranged between the cathode K and the grid G; at n^-nFS layers are arranged on the lower surface of the drift region, and p is arranged on the lower surface of the nFS layer⁺Anode region at p⁺The lower surface of the anode region is provided with a plurality of layers of metallized anodes A.

Comparing fig. 1 and 2, it can be seen that the difference between the BRT device structure of the present invention and the BRT structure of the prior art is that the present invention is at n^-Buried layers (i.e. BN-CS or BOX) which are in contact with the two sides of the p-base region are respectively arranged on the two sides of the p-base region above the drift region, and the buried layers adopt N-type doped layers as carrier storage layers(abbreviated as buried N-type carrier storage layer, BN-CS) or buried silicon dioxide layer (abbreviated as buried oxide layer, BOX) as a carrier blocking layer.

The concentration of the buried N-type carrier storage layer is 1X 10¹⁵cm^-3～9×10¹⁵cm^-3The thickness is 0.6-2 μm; the lateral spacing deviation Delta x between the buried N-type carrier storage layer and the p base region is-0.25 mu m-1.2 mu m; buried N-type carrier storage layer and p⁺⁺The longitudinal spacing deltay of the shunting region is 0.5 to 1.5 mu m.

The thickness of the buried silicon dioxide layer is 0.5 μm; the lateral spacing deviation Delta x between the buried silicon dioxide layer and the p base region is-0.5-1.5 μm; buried silicon dioxide layer and p⁺⁺The longitudinal distance delta of the shunting region is 0-1.5 mu m.

The working principle of the BRT device structure is as follows:

when a positive voltage applied to the gate-cathode is greater than a threshold voltage, an N channel is formed on the surface of the p-base region under the gate, and electrons are emitted from N⁺The cathode region is implanted to N through the N channel^-Drift region of n^-The potential of the drift region is reduced; when is composed of p⁺J formed by anode region and nFS layer₁When the potential of the junction is greater than its turn-on voltage, p⁺The anode region starts to n^-The drift region injects holes. Holes injected into the anode region are combined with electrons from the N channel, accumulated below the buried layer and enter the p base region, and the potential of the p base region is increased. If the potential of the p base region rises and exceeds the p base region and the n⁺J formed in the cathode region₃At the turn-on voltage of the junction, n⁺The cathode region starts to move towards n^-The drift region injects electrons, and thus the npn transistor on the cathode side and the pnp transistor on the anode side drive each other. When the current amplification factor of the two is larger than 1, the main thyristor is switched on, so that the on-state voltage drop of the device is greatly reduced. Therefore, in the conducting process, the buried layer is beneficial to accumulation of holes below the buried layer and in the p base region, so that electron injection enhancement is generated on the cathode side, conduction of a thyristor in a device is accelerated, and the voltage retracing (Snapback) phenomenon is avoided.

When the negative voltage applied to the grid is larger than the threshold voltage, n below the grid^-Forming a P channel on the surface of the drift region, and connecting the P base region with the P⁺⁺The shunting region is communicated, so that the holes are extracted to the cathode through the P channel, and the device is rapidly turned off. If the device is to be restored to the forward blocking state, a voltage of-5V is still applied between the gate and the cathode to maintain the P channel, thereby providing a path for leakage current. Otherwise, a higher forward blocking voltage cannot be maintained.

Feature verification

In order to evaluate a plurality of characteristics of the BRT with the buried layer of the present invention, forward blocking characteristics, conducting characteristics and switching characteristics of the BRT with the two kinds of buried layers at normal temperature (300K) and high temperature (400K) were simulated by professional simulation software, taking 6.5kV voltage class as an example, and compared with the characteristics of the BRT in the prior art.

1. Forward blocking characteristics

Referring to fig. 3, the forward blocking characteristic curves of the BRT having the buried N-type carrier storage layer (hereinafter, referred to as BN-CS-BRT) and the BRT having the buried silicon dioxide layer (hereinafter, referred to as BOX-BRT) according to the present invention and the prior art BRT at normal temperature (300K) and high temperature (400K) are shown. As can be seen from FIG. 3, at room temperature of 300K, the blocking voltages of the three can reach 7800V; at the high temperature of 400K, compared with the BRT in the prior art, the blocking voltage and the leakage current of the BN-CS-BRT are both reduced, while the blocking voltage of the BOX-BRT is improved, and the leakage current is obviously reduced. This demonstrates the better blocking characteristics of the BOX-BRT of the present invention.

2. Forward conduction characteristic

Referring to FIG. 4, it shows the on-state characteristic comparison curves of the present invention BN-CS-BRT and BOX-BRT with the prior art BRT at normal temperature (300K) and high temperature (400K). Therefore, the two devices with the buried layer BRT can effectively inhibit the Snapback phenomenon, and the current density J at the anode can be controlled_ALess than 40A/cm²The on-state voltage drop of the BOX-BRT and the BN-CS-BRT is significantly lower than that of the BRT of the prior art.

Referring to FIG. 5, the cathode side electron injection efficiency γ of the BRT of the present invention and the BRT of the prior art are shown_nCurrent density J with cathode_KAnd (4) comparing the change curves. As can be seen from FIG. 5, the BN-CS-BRT and BOX of the present inventionCathode electron injection efficiency γ for BRT devices_nThe structure is higher than the BRT structure in the prior art, and the BOX-BRT is more remarkable under high current, which shows that the IE effect in the BOX-BRT is stronger than that in the BN-CS-BRT in the invention.

Referring to FIG. 6, the anode side hole injection efficiency γ of the invention BN-CS-BRT and BOX-BRT and the prior art BRT is shown_pCurrent density J with anode_AAnd (4) comparing the change curves. As can be seen from FIG. 6, the anode side hole injection efficiency γ of the present invention BN-CS-BRT and the prior art BRT_pIdentical, and the efficiency gamma of the anode hole injection of the BOX-BRT device of the invention_pIs slightly higher than BN-CS-BRT and BRT of the prior art.

Referring to FIG. 7, the ON voltage drop V of the invention BN-CS-BRT and BOX-BRT is the same as that of the prior art BRT at the same anode current density_TAnd minority carrier lifetime τ_p0And (4) comparing the relation curves. As can be seen from FIG. 7, the on-state voltage drop of all three structures decreases with increasing base carrier lifetime, and the V of the BRT of the prior art is reduced under the same minority carrier lifetime_TV of maximum, BN-CS-BRT_TSecond, V of BOX-BRT_TAnd the lowest. This shows that the BN-CS-BRT and BOX-BRT can improve the on-state voltage drop of the device by adopting the invention.

Referring to FIG. 8, the BN-CS-BRT and BOX-BRT of the present invention have the same life time as the BRT of the prior art and the power density E of the present invention is cut off_offAnd the on-state voltage drop V_TThe trade-off relationship of (c) to (d). As can be seen from FIG. 8, the on-state characteristics and the off-state characteristics of the BOX-BRT are best compromised, and the BRT of the prior art is inferior to BN-CS-BRT. This shows that the BN-CS-BRT and the BOX-BRT can improve the compromise relationship between the on-state voltage drop and the turn-off energy consumption of the device.

3. Effect of Key Structure parameters on device characteristics

The key structural parameters affecting the device characteristics are the concentration and thickness of the buried N-type carrier storage layer and the position or position of the buried oxide layer.

Referring to FIG. 9, the concentration of the buried N-type carrier storage layer of the BN-CS-BRT of the invention is related to the on-state voltage drop V of the device_TAnd breakdown voltage V_BRThe influence of (c). As can be seen from fig. 9, when the concentration of the N-type carrier storage layer is expressed from 110¹⁵cm^-3Increased to 1 × 10¹⁶cm^-3On state voltage drop V_TGradually decreasing, breakdown voltage V_BRFirst slowly decreases, and when the concentration of the N-type carrier storage layer is more than 9 x 10¹⁵cm^-3Time V_BRSharply decreases when V_TAre small.

Referring to FIG. 10, the thickness of the buried N-type carrier storage layer of the BN-CS-BRT of the invention is related to the on-state voltage drop V of the device_TAnd breakdown voltage V_BRThe influence of (c). As can be seen from FIG. 10, when the thickness of the N-type carrier storage layer is increased from 0.6 μm to 2.5 μm, the on-state voltage drop V is increased_TGradually decreasing, breakdown voltage V_BRAlso decreases slowly first, but when the thickness of the N-type carrier storage layer is more than 2 μm, V_BRSharply decreases when V_TAnd is also small.

Referring to FIG. 11, the lateral spacing deviation Deltax between the buried N-type carrier storage layer and the p-base region of the BN-CS-BRT of the invention is related to the on-state voltage drop V of the device_TAnd breakdown voltage V_BRThe influence of (c). As can be seen from fig. 11, when the lateral pitch deviation Δ x between the buried N-type carrier storage layer and the p-base region is 0 (i.e., they are exactly connected), the on-state voltage drop V is large_TLow, simultaneous breakdown voltage V_BRHigher. When the lateral distance deviation delta x between the N-type carrier storage layer and the p-base region<0 (i.e., the two overlap), the on-state pressure drop V increases with the absolute value of Δ x_TSmall variation, breakdown voltage V_BRA sharp drop; when the lateral distance deviation delta x between the buried N-type carrier storage layer and the p-base region>0 (i.e., the two do not overlap), the on-state voltage drop V increases with the value of Δ x_TGradually increasing, breakdown voltage V_BRRemain almost unchanged.

Referring to FIG. 12, the buried N-type carrier storage layer and p of BN-CS-BRT of the present invention⁺⁺Longitudinal spacing Deltay of shunting region to device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (c). As can be seen from FIG. 12, the buried N-type carrier storage layer and p are formed⁺⁺The longitudinal spacing Deltay of the flow-dividing region is increased, and the on-state pressure drop V is increased_TGradually increasing, breakdown voltage V_BRIncreasing first and then decreasing; when Δ y is 1 μm, the on-state voltage drop V_TLow, simultaneous breakdown voltage V_BRHigher.

As is clear from fig. 9, 10, 11, and 12, the higher the concentration and the thicker the thickness of the buried N-type carrier storage layer are, the better the conduction characteristics are, but the blocking characteristics are deteriorated; the larger the transverse spacing deviation delta x between the buried N-type carrier storage layer and the p-base region is, the better the conduction characteristic is and the poorer the blocking characteristic is; buried N-type carrier storage layer and p⁺⁺The larger the longitudinal distance deltay of the shunt area is, the worse the conduction characteristic is, and the blocking voltage is increased and then decreased. Therefore, in the actual manufacturing process, the concentration of the buried N-type carrier storage layer can be controlled to be 2 x 10¹⁵cm^-3～9×10¹⁵cm^-3Within the range, the thickness can be controlled within the range of 0.6 to 2.0 μm; the lateral spacing deviation Delta x between the buried N-type carrier storage layer and the p-base region can be controlled to be-0.25-1.5 mu m and p⁺⁺The longitudinal distance delta y of the shunting region can be controlled between 0.5 and 2 mu m.

Referring to FIG. 13, the lateral spacing deviation Δ x of the buried oxide layer and the p-base region of the BOX-BRT of the present invention versus the device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (c). As can be seen from FIG. 13, when the lateral spacing deviation Δ x of the buried oxide layer from the p-base region is<0 (i.e., the two overlap), the on-state pressure drop V increases with the absolute value of Δ x_TReduced breakdown voltage V_BRThe variation is small; when the lateral spacing deviation delta x of the buried oxide layer and the p base region>0 (i.e., the two do not overlap), the on-state voltage drop V increases with the value of Δ x_TObviously increased breakdown voltage V_BRThe increase is slower.

Referring to FIG. 14, there are shown a buried oxide layer and p of the BOX-BRT of the present invention⁺⁺Longitudinal spacing Deltay of shunting region to device on-state voltage drop V_TAnd breakdown voltage V_BRThe influence of (a); as can be seen in FIG. 14, the buried oxide layer and p⁺⁺On-state pressure drop V as the longitudinal separation Deltay of the splitting zone increases_TGradually increased, breakdown voltage V_BRSlightly increased and then kept unchanged; when Δ y is 0.2 μm, the on-state pressure drop V_TLow, simultaneous breakdown voltage V_BRHigher.

Referring to fig. 13 and 14, the larger the lateral pitch deviation between the buried oxide layer and the p-base region, the better the blocking characteristic and the worse the conduction characteristic; buried oxide layer and p⁺⁺The larger the longitudinal distance of the shunt area is, the smaller the blocking voltage change is, and the worse the conduction characteristic is. Therefore, in the practical manufacturing process, the transverse spacing deviation Delta x between the buried oxide layer and the p base region can be controlled to be-0.5-1.5 mu m and p⁺⁺The longitudinal distance delta y of the shunting area can be controlled to be 0-1.5 mu m.

Referring to fig. 15, the method for manufacturing a BRT having a buried layer according to the present invention is specifically implemented according to the following steps:

step 1, selecting an original high-resistance zone melting medium silicon single crystal polished wafer as n^-Drift region, pre-processed n^-Injecting phosphorus ions on the lower surface of the drift region, annealing and propelling, and forming nFS layers on the lower surface;

step 2, removing the oxide layer on the surface of the silicon wafer treated in the step 1, and forming sacrificial oxide layers on the upper surface and the lower surface by adopting dry oxygen oxidation;

step 3, photoetching is carried out on the upper surface of the silicon wafer processed in the step 2 to form boron ion implantation windows of a p-base region and a terminal field ring region (not shown in the picture 15), and then boron ion implantation is carried out by adopting photoresist masking; then, boron ion implantation is carried out on the lower surface, high-temperature annealing and propulsion are carried out after photoresist stripping, a selective p base region is formed on the upper surface of the silicon chip, and p is formed on the lower surface⁺An anode region;

step 4, forming n completely identical to the p base region injection window on the upper surface of the silicon wafer processed in the step 3 through photoetching⁺Injecting phosphorus ion into the window of the cathode region, then adopting photoresist to mask the window, removing photoresist, and then carrying out high-temperature propulsion and annealing to form n⁺A cathode region implementing a self-aligned N channel;

step 5, forming an ion implantation window of an N-type buried layer on the upper surface of the silicon wafer processed in the step 4 through photoetching, performing high-energy phosphorus ion (P +) or oxygen ion (O +) implantation by utilizing photoresist masking, and forming a buried N-type carrier storage layer (BN-CS) or a buried silicon dioxide layer (BOX) by adopting a reverse doping process;

step 6, removing the oxide layer on the surface of the silicon wafer treated in the step 5, carrying out dry oxygen oxidation again, then forming a polycrystalline silicon layer by adopting chemical vapor deposition, and doping;

step 7, photoetching the upper surface of the silicon wafer processed in the step 6, removing the polycrystalline silicon layer and reserving the grid oxide layer to form p⁺⁺Injecting boron ions into the window of the shunting region, then adopting photoresist to mask the window for boron ion injection, and annealing after removing the photoresist to form p⁺⁺A shunting region;

step 8, depositing phosphorosilicate glass on the upper surface of the silicon wafer treated in the step 7, and refluxing at high temperature to realize cell surface planarization;

step 9, photoetching the upper surface of the silicon wafer processed in the step 8 to form a cathode contact hole, performing secondary reflux, depositing a metal aluminum layer on the upper surface, reversely etching, sputtering four layers of metalized films of aluminum, titanium, nickel and silver on the lower surface in sequence, forming a metalized cathode K on the upper surface and forming a multi-layer metalized anode A on the lower surface after alloying;

and step 10, throwing a polyimide film on the upper surface of the silicon wafer processed in the step 9, forming a pressure welding area pattern of a grid electrode and a cathode by photoetching, carrying out polyimide curing treatment, carrying out passivation protection on the surface of a terminal area, and scribing to obtain the silicon wafer.

Referring to fig. 15, in the manufacturing process of the device of the present invention, five ion implantations are required: the first time is phosphorus ion (P)⁺) Injecting to form nFS layer on the back; second time is boron ion (B)⁺) Implanting, advancing and annealing to form selective p-base region and terminal field ring region on upper surface and p on lower surface⁺An anode region; the third time is to proceed phosphorus ion (P) in the center of the surface of the P-base region⁺) N is formed after implantation, propulsion and annealing⁺A cathode region; the fourth step is to perform high-energy phosphorus ions (P) on both sides of the P base region⁺) Implanted or oxygen ion (O)⁺) Injecting and annealing to form a buried N-type carrier storage layer or a buried oxide layer; the fifth is at n^-Boron ions (B) are carried out on two sides of the p base region on the surface of the drift region⁺) Implanting, annealing to form p⁺⁺A shunting region.