阅读说明：本技术 多赫蒂放大器和通信装置 (Doherty amplifier and communication device ) 是由 小松崎优治 坂田修一 新庄真太郎 大塚浩志 于 2019-04-25 设计创作，主要内容包括：以如下方式构成多赫蒂放大器(1),具有：第1晶体管(16),其对第1信号进行放大,输出放大后的第1信号；第2晶体管(20),其对第2信号进行放大,输出放大后的第2信号；以及合成电路(31),其对从第1晶体管(16)输出的放大后的第1信号和从第2晶体管(20)输出的放大后的第2信号进行合成,输出放大后的第1信号与放大后的第2信号的合成信号,根据频率对以同相方式合成由第1晶体管(16)放大的第1信号和由第2晶体管(20)放大的第2信号的信号模式、以及以异相方式合成由第1晶体管(16)放大的第1信号和由第2晶体管(20)放大的第2信号的信号模式进行切换,动作模式根据切换后的信号模式而被切换成多赫蒂动作模式或异相动作模式。(A Doherty amplifier (1) is configured in such a manner that it has: a 1 st transistor (16) which amplifies the 1 st signal and outputs the amplified 1 st signal; a 2 nd transistor (20) which amplifies the 2 nd signal and outputs the amplified 2 nd signal; and a combining circuit (31) that combines the amplified 1 st signal output from the 1 st transistor (16) and the amplified 2 nd signal output from the 2 nd transistor (20), outputs a combined signal of the amplified 1 st signal and the amplified 2 nd signal, and switches, in accordance with the frequency, a signal mode in which the 1 st signal amplified by the 1 st transistor (16) and the 2 nd signal amplified by the 2 nd transistor (20) are combined in an in-phase manner, and a signal mode in which the 1 st signal amplified by the 1 st transistor (16) and the 2 nd signal amplified by the 2 nd transistor (20) are combined in an out-of-phase manner, the operation mode being switched to a doherty operation mode or an out-of-phase operation mode in accordance with the switched signal mode.)

1. A doherty amplifier, characterized in that the doherty amplifier has:

a 1 st transistor for amplifying the 1 st signal and outputting the amplified 1 st signal;

a 2 nd transistor for amplifying the 2 nd signal and outputting the amplified 2 nd signal; and

a synthesis circuit that synthesizes the amplified 1 st signal output from the 1 st transistor and the amplified 2 nd signal output from the 2 nd transistor and outputs a synthesized signal of the amplified 1 st signal and the amplified 2 nd signal,

the signal mode in which the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor are synthesized in an in-phase manner according to the frequency and the signal mode in which the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor are synthesized in an out-of-phase manner are switched, and the operation mode is switched to a doherty operation mode or an out-of-phase operation mode according to the switched signal mode.

2. The Doherty amplifier of claim 1,

the Doherty amplifier has:

a 1 st output circuit that transmits the amplified 1 st signal output from the 1 st transistor to the synthesizing circuit; and

a 2 nd output circuit having an electrical length longer than that of the 1 st output circuit, transmitting the amplified 2 nd signal output from the 2 nd transistor to the combining circuit,

the 1 st output circuit modulates impedance when the synthesizing circuit is viewed from the 1 st transistor in accordance with a frequency of a 1 st signal amplified by the 1 st transistor,

the 2 nd output circuit modulates impedance when the synthesizing circuit is viewed from the 2 nd transistor in accordance with a frequency of a 2 nd signal amplified by the 2 nd transistor.

3. The Doherty amplifier of claim 2,

an operation mode in which the amplitude of the 1 st signal amplified by the 1 st transistor is equal to or greater than the amplitude of the 2 nd signal amplified by the 2 nd transistor and the difference between the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor is constant is a 1 st doherty operation mode.

4. The Doherty amplifier of claim 2,

an operation mode in which the amplitude of the 1 st signal amplified by the 1 st transistor is the same as the amplitude of the 2 nd signal amplified by the 2 nd transistor, the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor are in opposite phases, and the difference between the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor monotonically decreases as the current of the synthesis signal output from the synthesis circuit increases is a 1 st out-of-phase operation mode.

5. The Doherty amplifier of claim 2,

an operation mode in which the amplitude of the 1 st signal amplified by the 1 st transistor is the same as the amplitude of the 2 nd signal amplified by the 2 nd transistor, the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor are in opposite phases, and the difference between the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor monotonically increases as the current of the synthesis signal output from the synthesis circuit increases is a 2 nd out-of-phase operation mode.

6. The Doherty amplifier of claim 2,

an operation mode in which the amplitude of the 1 st signal amplified by the 1 st transistor is equal to or less than the amplitude of the 2 nd signal amplified by the 2 nd transistor, the difference between the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor is constant, and the frequency is lower than the frequency in the 1 st doherty operation mode is the 2 nd doherty operation mode.

7. The Doherty amplifier of claim 2,

an operation mode in which the amplitude of the 1 st signal amplified by the 1 st transistor is equal to or less than the amplitude of the 2 nd signal amplified by the 2 nd transistor, the difference between the phase of the 1 st signal amplified by the 1 st transistor and the phase of the 2 nd signal amplified by the 2 nd transistor is constant, and the frequency is higher than the frequency in the 1 st doherty operation mode is a 3 rd doherty operation mode.

8. A Doherty amplifier according to any one of claims 3 to 7, characterized in that,

the doherty amplifier has a signal source that outputs a 1 st signal amplified by the 1 st transistor to an input terminal of the 1 st transistor and outputs a 2 nd signal amplified by the 2 nd transistor to an input terminal of the 2 nd transistor.

9. The Doherty amplifier of claim 8,

in the 1 st doherty action mode,

the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are respectively the 1 st frequency,

an amplitude of a 1 st signal output from the signal source to the input terminal of the 1 st transistor and an amplitude of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor each monotonically increase with an increase in voltage of a composite signal output from the composite circuit, and the amplitude of the 1 st signal when the amplitude of the 2 nd signal is zero is larger than zero,

the output power of the 1 st transistor becomes a saturation power when the amplitude of the 1 st signal is maximum, the output power of the 2 nd transistor becomes a saturation power when the amplitude of the 2 nd signal is maximum,

the phase of the 1 st signal output from the signal source to the input terminal of the 1 st transistor is advanced by 90 degrees with respect to the phase of the 2 nd signal output from the signal source to the input terminal of the 2 nd transistor.

10. The Doherty amplifier of claim 9,

in the 1 st out-of-phase operating mode,

the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are respectively the 2 nd frequency lower than the 1 st frequency,

an amplitude of a 1 st signal output from the signal source to the input terminal of the 1 st transistor and an amplitude of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor each monotonically increase with an increase in current of a composite signal output from the composite circuit, and the amplitude of the 1 st signal is the same value as the amplitude of the 2 nd signal,

the output power of the 1 st transistor becomes a saturation power when the amplitude of the 1 st signal is maximum, the output power of the 2 nd transistor becomes a saturation power when the amplitude of the 2 nd signal is maximum,

the phase of the 1 st signal output from the signal source to the input terminal of the 1 st transistor monotonically decreases as the current of the synthesized signal output from the synthesis circuit increases,

a phase of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor monotonically increases with an increase in current of a synthesized signal output from the synthesizing circuit,

the phase of the 1 st signal and the phase of the 2 nd signal are equal in absolute value and different in sign from each other.

11. The Doherty amplifier of claim 9,

in the 2 nd out-of-phase mode of operation,

the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are respectively a 3 rd frequency higher than the 1 st frequency,

an amplitude of a 1 st signal output from the signal source to the input terminal of the 1 st transistor and an amplitude of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor each monotonically increase with an increase in current of a composite signal output from the composite circuit, and the amplitude of the 1 st signal is the same value as the amplitude of the 2 nd signal,

the output power of the 1 st transistor becomes a saturation power when the amplitude of the 1 st signal is maximum, the output power of the 2 nd transistor becomes a saturation power when the amplitude of the 2 nd signal is maximum,

a phase of a 1 st signal output from the signal source to the input terminal of the 1 st transistor monotonically increases with an increase in current of a synthesized signal output from the synthesizing circuit,

a phase of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor monotonically decreases with an increase in current of a synthesized signal output from the synthesizing circuit,

the phase of the 1 st signal and the phase of the 2 nd signal are equal in absolute value and different in sign from each other.

12. The Doherty amplifier of claim 10,

in the 2 nd doherty action mode,

the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are respectively a 4 th frequency lower than the 2 nd frequency,

an amplitude of a 1 st signal output from the signal source to the input terminal of the 1 st transistor and an amplitude of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor each monotonically increase with an increase in voltage of a composite signal output from the composite circuit, and an amplitude of the 2 nd signal when the amplitude of the 1 st signal is zero is larger than zero,

the output power of the 1 st transistor becomes a saturation power when the amplitude of the 1 st signal is maximum, the output power of the 2 nd transistor becomes a saturation power when the amplitude of the 2 nd signal is maximum,

the phase of the 1 st signal output from the signal source to the input terminal of the 1 st transistor is advanced by 45 degrees with respect to the phase of the 2 nd signal output from the signal source to the input terminal of the 2 nd transistor.

13. The Doherty amplifier of claim 11,

in the 3 rd doherty action mode,

the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are respectively a 5 th frequency higher than the 3 rd frequency,

an amplitude of a 1 st signal output from the signal source to the input terminal of the 1 st transistor and an amplitude of a 2 nd signal output from the signal source to the input terminal of the 2 nd transistor each monotonically increase with an increase in voltage of a composite signal output from the composite circuit, and an amplitude of the 2 nd signal when the amplitude of the 1 st signal is zero is larger than zero,

the output power of the 1 st transistor becomes a saturation power when the amplitude of the 1 st signal is maximum, the output power of the 2 nd transistor becomes a saturation power when the amplitude of the 2 nd signal is maximum,

the phase of the 1 st signal output from the signal source to the input terminal of the 1 st transistor is advanced by 135 degrees with respect to the phase of the 2 nd signal output from the signal source to the input terminal of the 2 nd transistor.

14. The Doherty amplifier of claim 2,

the electrical length of the 1 st output circuit varies according to the frequency of the 1 st signal amplified by the 1 st transistor,

an electrical length of the 2 nd output circuit varies according to a frequency of the 2 nd signal amplified by the 2 nd transistor.

15. The Doherty amplifier of claim 14,

when the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor are the 1 st frequencies, respectively, the electrical length of the 2 nd output circuit is 90 degrees longer than the electrical length of the 1 st output circuit.

16. The Doherty amplifier of claim 15,

the 1 st output circuit has:

a 1 st transmission line having one end connected to the output terminal of the 1 st transistor and the other end connected to the 1 st input terminal of the combining circuit, and having an electrical length of less than 90 degrees; and

a 1 st capacitor connected in parallel with the 1 st transmission line,

the 2 nd output circuit has:

a 2 nd transmission line having one end connected to an output terminal of the 2 nd transistor and having an electrical length of less than 90 degrees;

a 3 rd transmission line having one end connected to the other end of the 2 nd transmission line and the other end connected to the 2 nd input terminal of the combining circuit, and having an electrical length of 90 degrees; and

a 2 nd capacitor connected in parallel with the 2 nd transmission line.

17. The Doherty amplifier of claim 16,

the characteristic impedance of the 1 st transmission line is higher than the output resistance of the 1 st transistor,

the characteristic impedance of the 2 nd transmission line is higher than the output resistance of the 2 nd transistor,

the 1 st capacitor has the same capacitance as the output capacitance of the 1 st transistor,

the 2 nd capacitor has the same capacitance as the output capacitance of the 2 nd transistor.

18. The Doherty amplifier of claim 1,

the input terminal of the 1 st transistor and the input terminal of the 2 nd transistor are applied with a bias voltage equal to a threshold voltage, respectively.

19. The Doherty amplifier of claim 1,

a bias voltage higher than the critical voltage and lower than a 1 st threshold voltage is applied to an input terminal of the 1 st transistor,

the 1 st threshold voltage is a voltage higher than the critical voltage.

20. The Doherty amplifier of claim 1,

a bias voltage higher than the critical voltage and lower than a 1 st threshold voltage is applied to an input terminal of the 2 nd transistor,

the 1 st threshold voltage is a voltage higher than the critical voltage.

21. The Doherty amplifier of claim 1,

a bias voltage lower than the threshold voltage and higher than a 2 nd threshold voltage is applied to an input terminal of the 1 st transistor,

the 2 nd threshold voltage is a voltage lower than the critical voltage.

22. The Doherty amplifier of claim 1,

a bias voltage lower than the threshold voltage and higher than a 2 nd threshold voltage is applied to an input terminal of the 2 nd transistor,

the 2 nd threshold voltage is a voltage lower than the critical voltage.

23. The Doherty amplifier of claim 1,

the doherty amplifier has a control circuit which controls bias voltages applied to an input terminal of the 1 st transistor and an input terminal of the 2 nd transistor, respectively.

24. The Doherty amplifier of claim 1,

the doherty amplifier has a control circuit which controls bias voltages applied to an output terminal of the 1 st transistor and an output terminal of the 2 nd transistor, respectively.

25. A communication apparatus comprising the doherty amplifier according to claim 1 as an amplifier for amplifying a 1 st signal and a 2 nd signal which are communication signals, respectively.

Technical Field

The invention relates to a Doherty amplifier and a communication device.

Background

In a general doherty amplifier, a phase shift element is connected to an output side of a carrier amplifier, and a phase shift element is connected to an input side of a peak amplifier.

On the other hand, the following patent document 1 discloses a doherty amplifier: the amplitude and phase can be matched between the output signal of the carrier amplifier and the output signal of the peak amplifier.

In the doherty amplifier disclosed in patent document 1, a 1 st phase adjuster is connected to a stage before a carrier amplifier, and a 2 nd phase adjuster is connected to a stage before a peak amplifier.

In the doherty amplifier disclosed in patent document 1, the 1 st phase adjuster adjusts the phase of a signal input to the carrier amplifier, and the 2 nd phase adjuster adjusts the phase of a signal input to the peak amplifier.

In the doherty amplifier disclosed in patent document 1, when both the carrier amplifier and the peak amplifier operate, the output power of the carrier amplifier and the output power of the peak amplifier are combined by the summing node.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 2015-89130

Disclosure of Invention

Problems to be solved by the invention

In the doherty amplifier disclosed in patent document 1, even if the frequency of the input signal changes, the impedance when the summing node is viewed from the carrier amplifier cannot be modulated. Even if the frequency of the input signal changes, the impedance when the summing node is viewed from the peak amplifier cannot be modulated. Therefore, there is a problem that the amplification efficiency of the doherty amplifier is sometimes deteriorated.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a doherty amplifier and a communication device capable of widening efficiency characteristics at the time of back-off even when the frequency of a 1 st signal amplified by a 1 st transistor and the frequency of a 2 nd signal amplified by a 2 nd transistor are changed.

Means for solving the problems

The doherty amplifier of the present invention comprises: a 1 st transistor for amplifying the 1 st signal and outputting the amplified 1 st signal; a 2 nd transistor for amplifying the 2 nd signal and outputting the amplified 2 nd signal; and a synthesizing circuit for synthesizing the amplified 1 st signal output from the 1 st transistor and the amplified 2 nd signal output from the 2 nd transistor, outputting a synthesized signal of the amplified 1 st signal and the amplified 2 nd signal, and switching between a signal mode of synthesizing the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor in an in-phase manner and a signal mode of synthesizing the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor in an out-of-phase manner according to a frequency, wherein the operation mode is switched to a doherty operation mode or an out-of-phase operation mode according to the switched signal mode.

Effects of the invention

According to the present invention, the doherty amplifier is constructed in the following manner: a signal mode in which the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor are synthesized in an in-phase manner and a signal mode in which the 1 st signal amplified by the 1 st transistor and the 2 nd signal amplified by the 2 nd transistor are synthesized in an out-of-phase manner are switched in accordance with a frequency, and an operation mode is switched to a Doherty operation mode or an out-of-phase operation mode in accordance with the switched signal mode. Therefore, in the doherty amplifier of the present invention, even if the frequency of the 1 st signal amplified by the 1 st transistor and the frequency of the 2 nd signal amplified by the 2 nd transistor change, the efficiency characteristic at the time of back-off can be made wide.

Drawings

Fig. 1 is a block diagram showing a communication device including the doherty amplifier 1 of embodiment 1.

Fig. 2 is an explanatory diagram showing frequencies of a plurality of operation modes of the doherty amplifier 1.

Fig. 3 is a block diagram showing the doherty amplifier 1 of embodiment 1.

Fig. 4A is an explanatory diagram showing the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13, fig. 4B is an explanatory diagram showing the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13, and fig. 4C is an explanatory diagram showing the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 5 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 1 st doherty operation mode.

Fig. 6 is an explanatory diagram showing a load change in the operation at the time of back-off of the doherty amplifier 1 in the 1 st doherty operation mode.

Fig. 7A is an explanatory diagram showing the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13, fig. 7B is an explanatory diagram showing the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13, and fig. 7C is an explanatory diagram showing the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 8 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 1 st out-of-phase operation mode.

Fig. 9 is an explanatory diagram showing a load change in the operation at the time of back-off of the doherty amplifier 1 in the 1 st out-phase operation mode.

Fig. 10A is an explanatory diagram showing the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13, fig. 10B is an explanatory diagram showing the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13, and fig. 10C is an explanatory diagram showing the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 11 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 2 nd out-phase operation mode.

Fig. 12A is an explanatory diagram showing the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13, fig. 12B is an explanatory diagram showing the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13, and fig. 12C is an explanatory diagram showing the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 13 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 2 nd doherty operation mode.

Fig. 14A is an explanatory diagram showing the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13, fig. 14B is an explanatory diagram showing the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13, and fig. 14C is an explanatory diagram showing the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 15 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 3 rd doherty operation mode.

Fig. 16 is a block diagram showing the 1 st output circuit 24 of the doherty amplifier 1 of embodiment 5.

Fig. 17 is a block diagram showing the 2 nd output circuit 27 of the doherty amplifier 1 of embodiment 5.

Fig. 18 is a block diagram showing the 1 st output circuit 24 of the doherty amplifier 1 of embodiment 6.

Fig. 19 is a block diagram showing the 2 nd output circuit 27 of the doherty amplifier 1 of embodiment 6.

Fig. 20 is a block diagram showing the doherty amplifier 1 of embodiment 8.

Fig. 21 is a block diagram showing the doherty amplifier 1 of embodiment 9.

Detailed Description

Hereinafter, in order to explain the present invention in more detail, a mode for carrying out the present invention will be described with reference to the drawings.

Embodiment mode 1

Fig. 1 is a block diagram showing a communication device including the doherty amplifier 1 of embodiment 1.

In fig. 1, a doherty amplifier 1 divides a communication signal into a 1 st signal and a 2 nd signal, and amplifies the 1 st signal and the 2 nd signal, respectively.

The doherty amplifier 1 switches a signal mode of combining the 1 st signal amplified by the 1 st transistor 16 and the 2 nd signal amplified by the 2 nd transistor 20 in an in-phase manner and a signal mode of combining the 1 st signal amplified by the 1 st transistor 16 and the 2 nd signal amplified by the 2 nd transistor 20 in an out-of-phase manner according to a frequency.

The operation mode of the doherty amplifier 1 is switched to the doherty operation mode or the outphasing operation mode according to the signal mode after the switching.

As shown in fig. 2, the doherty amplifier 1 has a 1 st doherty operation mode, a 2 nd doherty operation mode and a 3 rd doherty operation mode as in-phase operation modes for operating as a doherty amplifier.

As shown in fig. 2, the doherty amplifier 1 has a 1 st outphasing operation mode and a 2 nd outphasing operation mode, and is operated as an outphasing operation mode in which the amplifiers are operated as outphasing amplifiers.

Fig. 2 is an explanatory diagram showing frequencies of a plurality of operation modes of the doherty amplifier 1.

The operation mode of the doherty amplifier 1 is determined by the frequency of the 1 st signal output from the 1 st input signal source 12 and the frequency of the 2 nd signal output from the 2 nd input signal source 13. The 1 st input signal source 12 and the 2 nd input signal source 13 will be described later.

The 1 st Doherty operation mode is such that the frequency of the 1 st signal outputted from the 1 st input signal source 12 and the frequency of the 2 nd signal outputted from the 2 nd input signal source 13 are the 1 st frequency f₁The operational mode of the time. In the example of FIG. 2, at about 2.8[ GHz ]]About 3.7[ GHz ]]Is the 1 st frequency f₁. However, this is merely an example and includes the 1 st frequency f₁May also be in the frequency range of about 2.8 GHz]About 3.7[ GHz ]]Is in a different range.

The 1 st out-of-phase operation mode is such that the frequency of the 1 st signal output from the 1 st input signal source 12 and the frequency of the 2 nd signal output from the 2 nd input signal source 13 are respectively higher than the 1 st frequency f₁Low 2 nd frequency f₂The operational mode of the time. In the example of FIG. 2, about 2.0[ GHz ]]About 2.8[ GHz-]Is the 2 nd frequency f₂. However, this is merely an example, and the 2 nd frequency f is included₂May also be in the frequency range of about 2.0 GHz]About 2.8[ GHz-]Is in a different range.

The 2 nd out-of-phase operation mode is such that the frequency of the 1 st signal output from the 1 st input signal source 12 and the frequency of the 2 nd signal output from the 2 nd input signal source 13 are respectively higher than the 1 st frequency f₁High 3 rd frequency f₃The operational mode of the time. In the example of FIG. 2, at about 3.7[ GHz ]]About 4.5[ GHz-]Is the 3 rd frequency f₃. However, this is merely an example, and the 3 rd frequency f₃The included frequency range may also be about 3.7 GHz]About 4.5[ GHz-]Is in a different range.

The 2 nd Doherty operation mode is such that the frequency of the 1 st signal outputted from the 1 st input signal source 12 and the frequency of the 2 nd signal outputted from the 2 nd input signal source 13 are respectively higher than the 2 nd frequency f₂Low 4 th frequency f₄The operational mode of the time. In the example of FIG. 2, at about 1.2[ GHz ]]About 2.0[ GHz-]Is the 4 th frequency f₄. However, this is merely an example, and the 4 th frequency f is included₄May also be in the frequency range of about 1.2 GHz]About 2.0[ GHz-]Is in a different range.

The 3 rd Doherty operation mode is such that the frequency of the 1 st signal outputted from the 1 st input signal source 12 and the frequency of the 2 nd signal outputted from the 2 nd input signal source 13 are respectively higher than the 3 rd frequency f₃High 5 th frequency f₅The operational mode of the time. In the example of FIG. 2, at about 4.5[ GHz ]]About 5.4[ GHz ]]Is the 5 th frequency f₅. However, this is merely an example, and includes the 5 th frequency f₅May also be in the frequency range of about 4.5 GHz]About 5.4[ GHz ]]Is in a different range.

Each operation mode of the doherty amplifier 1 includes an operation in a saturation output state when the output power of both the 1 st transistor 16 and the 2 nd transistor 20 is a saturation power, and the operation is performed by each of the 1 st transistor 16 and the 2 nd transistor 20. The 1 st transistor 16 and the 2 nd transistor 20 are described later.

Each operation mode of the doherty amplifier 1 includes a back-off operation when the output power of both the 1 st transistor 16 and the 2 nd transistor 20 is equal to or less than the saturation power, and is an operation of each of the 1 st transistor 16 and the 2 nd transistor 20.

In the operation at the time of back-off included in each of the 1 st doherty operation mode, the 2 nd doherty operation mode and the 3 rd doherty operation mode, only one of the 1 st transistor 16 and the 2 nd transistor 20 is operated, and the other is stopped.

In the operation at the time of back-off included in each of the 1 st out-phase operation mode and the 2 nd out-phase operation mode, both the 1 st transistor 16 and the 2 nd transistor 20 operate.

Fig. 2 shows the efficiency of the doherty amplifier 1 in operation at the time of back-off included in each operation mode, in addition to the frequencies of each operation mode of the doherty amplifier 1.

Fig. 3 is a block diagram showing the doherty amplifier 1 of embodiment 1.

In fig. 3, a signal source 11 has a 1 st input signal source 12 and a 2 nd input signal source 13.

The signal source 11 distributes a communication signal input to the signal source 11 into 2 signals.

The signal source 11 outputs one of the 2 signals to the 1 st input signal source 12 and the other signal to the 2 nd input signal source 13.

The 1 st input signal source 12 is realized by, for example, a quadrature modulator, a DAC (Digital Analog converter) and a DDS (Direct Digital synthesis).

The 1 st input signal source 12 determines an amplitude and a phase according to the operation mode of the doherty amplifier 1, and outputs a signal having a voltage of the determined amplitude and phase as a 1 st signal to the 1 st transistor 16 through the 1 st input matching circuit 14. The 1 st signal contains the same information as contained in one signal.

The 2 nd input signal source 13 is realized by, for example, a quadrature modulator, a DAC, and a DDS.

The 2 nd input signal source 13 determines an amplitude and a phase according to the operation mode of the doherty amplifier 1, and outputs a signal having a voltage of the determined amplitude and phase as a 2 nd signal to the 2 nd transistor 20 through the 2 nd input matching circuit 15. The 2 nd signal contains the same information as contained in the other signal.

The 1 st input matching circuit 14 and the 2 nd input matching circuit 15 are respectively realized by, for example, a circuit using lumped constant elements, a circuit using distributed constant lines, a circuit combining lumped constants and distributed constants, an L-C type matching circuit using a coil and a capacitor, or quarter wavelength lines.

One end of the 1 st input matching circuit 14 is connected to the 1 st input signal source 12, and the other end of the 1 st input matching circuit 14 is connected to the input terminal 16a of the 1 st transistor 16.

The 1 st input matching circuit 14 converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal output from the 1 st input signal source 12 to the input terminal 16a of the 1 st transistor 16.

One end of the 2 nd input matching circuit 15 is connected to the 2 nd input signal source 13, and the other end of the 2 nd input matching circuit 15 is connected to the input terminal 20a of the 2 nd transistor 20.

The 2 nd input matching circuit 15 converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal output from the 2 nd input signal source 13 to the input terminal 20a of the 2 nd transistor 20.

The 1 st Transistor 16 is realized by, for example, a FET (Field Effect Transistor), HBT (Heterojunction Bipolar Transistor), or HEMT (High Electron Mobility Transistor).

In the doherty amplifier 1 shown in fig. 3, an example is shown in which the 1 st transistor 16 is a transistor whose source is grounded. The input terminal 16a, i.e., the gate terminal, of the 1 st transistor 16 is connected to the other end of the 1 st input matching circuit 14, and the output terminal 16b, i.e., the drain terminal, of the 1 st transistor 16 is connected to one end of the 1 st transmission line 25 in the 1 st output circuit 24. The 1 st output circuit 24 will be described later.

The 1 st transistor 16 switches the in-phase operating as a doherty amplifier and the out-phase operating as an outphasing amplifier according to frequency.

The 1 st transistor 16 amplifies the 1 st signal output from the 1 st input signal source 12 via the 1 st input matching circuit 14, and outputs the amplified 1 st signal to the 1 st transmission line 25 of the 1 st output circuit 24.

A bias voltage substantially equal to the threshold voltage is applied to the input terminal 16a of the 1 st transistor 16. The 1 st transistor 16 amplifies a signal if the voltage of the input terminal 16a is greater than the threshold voltage, and the 1 st transistor 16 does not amplify a signal if the voltage of the input terminal 16a is equal to or less than the threshold voltage.

Therefore, the operation of the 1 st transistor 16 can be switched according to the presence or absence of the 1 st signal to the input terminal 16a of the 1 st transistor 16.

When the 1 st transistor 16 is represented by an equivalent circuit, the 1 st transistor 16 can be represented by a capacitor 17 having an input capacitance, a current source 18, and a capacitor 19 having an output capacitance.

The 2 nd transistor 20 is implemented by, for example, a FET, HBT, or HEMT.

In the doherty amplifier 1 shown in fig. 3, an example is shown in which the 2 nd transistor 20 is a transistor whose source is grounded. The input terminal 20a, i.e., the gate terminal, of the 2 nd transistor 20 is connected to the other end of the 2 nd input matching circuit 15, and the output terminal 20b, i.e., the drain terminal, of the 2 nd transistor 20 is connected to one end of the 2 nd transmission line 28 in the 2 nd output circuit 27. The 2 nd output circuit 27 will be described later.

The 2 nd transistor 20 switches the in-phase operating as a doherty amplifier and the out-phase operating as an outphasing amplifier according to frequency.

The 2 nd transistor 20 amplifies the 2 nd signal output from the 2 nd input signal source 13 via the 2 nd input matching circuit 15, and outputs the amplified 2 nd signal to the 2 nd transmission line 28 of the 2 nd output circuit 27.

A bias voltage substantially equal to the threshold voltage is applied to the input terminal 20a of the 2 nd transistor 20. The 2 nd transistor 20 amplifies a signal if the voltage of the input terminal 20a is greater than the threshold voltage, and the 2 nd transistor 20 does not amplify a signal if the voltage of the input terminal 20a is equal to or less than the threshold voltage.

Therefore, the operation of the 2 nd transistor 20 can be switched according to the presence or absence of the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

When the 2 nd transistor 20 is represented by an equivalent circuit, the 2 nd transistor 20 can be represented by a capacitor 21 having an input capacitance, a current source 22, and a capacitor 23 having an output capacitance.

The 1 st output circuit 24 has a capacitor 19, a 1 st transmission line 25, and a 1 st capacitor 26.

In the doherty amplifier 1 shown in fig. 3, the 1 st transistor 16 and the 1 st output circuit 24 are depicted in such a manner that the capacitor 19 having the output capacitance of the 1 st transistor 16 is shared. However, this is merely drawn in common for the sake of explanation, and the 1 st output circuit 24 may have only the 1 st transmission line 25 and the 1 st capacitor 26 instead of sharing the capacitor 19 with the 1 st transistor 16.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 1 st output circuit 24 modulates impedance when the synthesizing circuit 31 is viewed from the 1 st transistor 16, in accordance with the frequency of the 1 st signal amplified by the 1 st transistor 16.

The electrical length of the 1 st output circuit 24 varies according to the frequency of the 1 st signal. For example, the frequency of the 1 st signal includes the 1 st frequency f₁Of the frequency range of (3)₀The electrical length of the 1 st output circuit 24 is 90 degrees. The electrical length of the 1 st output circuit 24 is not limited to strictly match the electrical length of 90 degrees, and may be shifted from the electrical length of 90 degrees within a range that does not pose a practical problem.

One end of the 1 st transmission line 25 is connected to the output terminal 16b of the 1 st transistor 16, and the other end of the 1 st transmission line 25 is connected to the input terminal 31a of the combining circuit 31 and one end of the 1 st capacitor 26, respectively.

The 1 st transmission line 25 is, for example, such that the frequency of the 1 st signal is the 1 st frequency f₁A wire having an electrical length of less than 90 degrees.

The characteristic impedance of the 1 st transmission line 25 is higher than the output resistance of the 1 st transistor 16.

The 1 st capacitor 26 is connected in parallel with the 1 st transmission line 25. That is, one end of the 1 st capacitor 26 is connected to the other end of the 1 st transmission line 25 and the input terminal 31a of the combining circuit 31, and the other end of the 1 st capacitor 26 is connected to the ground.

The 1 st capacitor 26 has the same capacitance as the output capacitance of the 1 st transistor 16, i.e., the capacitance of the capacitor 19. However, the capacitance of the 1 st capacitor 26 is not limited to strictly match the capacitance of the capacitor 19, and may be different from the capacitance of the capacitor 19 within a range that does not pose a practical problem.

The 2 nd output circuit 27 has a capacitor 23, a 2 nd transmission line 28, a 3 rd transmission line 29, and a 2 nd capacitor 30.

In the doherty amplifier 1 shown in fig. 3, the 2 nd transistor 20 and the 2 nd output circuit 27 are depicted in such a manner that the capacitor 23 having the output capacitance of the 2 nd transistor 20 is shared. However, this is merely drawn in common for the sake of explanation, and the 2 nd output circuit 27 may have only the 2 nd transmission line 28, the 3 rd transmission line 29, and the 2 nd capacitor 30 instead of sharing the capacitor 23 with the 2 nd transistor 20.

The 2 nd output circuit 27 has an electrical length longer than that of the 1 st transmission line 25, transmits the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the combining circuit 31.

The 2 nd output circuit 27 modulates the impedance when the synthesizing circuit 31 is viewed from the 2 nd transistor 20 in accordance with the frequency of the 2 nd signal amplified by the 2 nd transistor 20.

The electrical length of the 2 nd output circuit 27 varies according to the frequency of the 2 nd signal. For example, the frequency of the 2 nd signal includes the 1 st frequency f₁Of the frequency range of (3)₀The electrical length of the 2 nd output circuit 27 is 180 degrees. However, the electrical length of the 2 nd output circuit 27 is not limited to exactly match the electrical length of 180 degrees, and may be shifted from the electrical length of 180 degrees within a range that has no practical problem.

One end of the 2 nd transmission line 28 is connected to the output terminal 20b of the 2 nd transistor 20, and the other end of the 2 nd transmission line 28 is connected to one end of the 3 rd transmission line 29 and one end of the 2 nd capacitor 30, respectively.

The 2 nd transmission line 28 is, for example, a 1 st frequency f at the frequency of the 2 nd signal₁A wire having an electrical length of less than 90 degrees.

The characteristic impedance of the 2 nd transmission line 28 is higher than the output resistance of the 2 nd transistor 20.

One end of the 3 rd transmission line 29 is connected to the other end of the 2 nd transmission line 28 and one end of the 2 nd capacitor 30, respectively, and the other end of the 3 rd transmission line 29 is connected to an input terminal 31b of the combining circuit 31.

The 3 rd transmission line 29 has a frequency of the 2 nd signal as a center frequency f, for example₀A wire having an electrical length of 90 degrees. However, the electrical length of the 3 rd transmission line 29 is not limited to strictly match the electrical length of 90 degrees, and may be shifted from the electrical length of 90 degrees within a range that has no practical problem.

The characteristic impedance of the 3 rd transmission line 29 is the same as the output resistance of the 2 nd transistor 20. However, the characteristic impedance of the 3 rd transmission line 29 is not limited to be exactly equal to the output resistance of the 2 nd transistor 20, and may be different from the output resistance of the 2 nd transistor 20 within a range that does not pose a practical problem.

The 2 nd capacitor 30 is connected in parallel with the 2 nd transmission line 28. That is, one end of the 2 nd capacitor 30 is connected to the other end of the 2 nd transmission line 28 and one end of the 3 rd transmission line 29, and the other end of the 2 nd capacitor 30 is connected to the ground.

The 2 nd capacitor 30 has the same capacitance as the capacitor 23, which is the output capacitance of the 2 nd transistor 20. However, the capacitance of the 2 nd capacitor 30 is not limited to strictly match the capacitance of the capacitor 23, and may be different from the capacitance of the capacitor 23 within a range that does not pose a practical problem.

The combining circuit 31 has a combining point 32 that combines the 1 st signal transmitted by the 1 st output circuit 24 and the 2 nd signal transmitted by the 2 nd output circuit 27.

The input terminal 31a of the combining circuit 31 is connected to the other end of the 1 st transmission line 25 and one end of the 1 st capacitor 26, respectively.

The input terminal 31b of the combining circuit 31 is connected to the other end of the 3 rd transmission line 29.

The combining circuit 31 combines the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The combining point 32 is a combining point of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27. If a combining point is included, it is referred to as a combining circuit.

Here, the in-phase means that the 1 st signal transmitted from the 1 st output circuit 24 and the 2 nd signal transmitted from the 2 nd output circuit 27 are combined in-phase at the combining point 32. For example, even if the 1 st signal input to the 1 st transistor 16 and the 2 nd signal input to the 2 nd transistor 20 are out of phase at the input terminal, if the 1 st signal transmitted by the 1 st output circuit 24 and having a phase change and the 2 nd signal transmitted by the 2 nd output circuit 27 and having a phase change are in phase at the combining point 32, they are in phase. Out-of-phase refers to out-of-phase combining the 1 st signal delivered by the 1 st output circuit 24 and the 2 nd signal delivered by the 2 nd output circuit 27 at the combining point 32. For example, even if the 1 st signal input to the 1 st transistor 16 and the 2 nd signal input to the 2 nd transistor 20 are in phase at the input terminal face, if the 1 st signal transmitted by the 1 st output circuit 24 and having a phase change and the 2 nd signal transmitted by the 2 nd output circuit 27 and having a phase change are out of phase at the combining point 32.

The output matching circuit 33 is realized by, for example, a circuit using lumped constant elements, a circuit using distributed constant lines, a circuit combining lumped constants and distributed constants, an L-C type matching circuit using a coil and a capacitor, or quarter wavelength lines.

One end of the output matching circuit 33 is connected to the combining point 32, and the other end of the output matching circuit 33 is connected to a load 34 outside the doherty amplifier 1.

The output matching circuit 33 is a circuit for matching the impedance of the combining point 32 with the impedance of the load 34.

The load 34 is a load external to the doherty amplifier 1 connected to the other end of the output matching circuit 33.

The doherty amplifier 1 shown in fig. 3 has an output matching circuit 33. However, this is merely an example, and if the 1 st output circuit 24 and the 2 nd output circuit 27 each have a matching function of impedance matching with the load 34, the doherty amplifier 1 may not have the output matching circuit 33.

Next, the operation of the doherty amplifier 1 shown in fig. 3 will be described.

In embodiment 1, for convenience of explanation, it is assumed that the frequency of the input communication signal is the 1 st frequency f₁Or 2 nd frequency f₂。

Therefore, in embodiment 1, the doherty amplifier shown in fig. 3 is assumed to operate in the 1 st doherty operation mode or the 1 st outphasing operation mode.

First, an outline of the operation of the doherty amplifier 1 will be described.

The signal source 11 distributes a communication signal input to the signal source 11 into 2 signals.

The signal source 11 outputs one of the 2 signals to the 1 st input signal source 12 and the other signal to the 2 nd input signal source 13.

If the frequency of a signal is the 1 st frequency f₁The 1 st input signal source 12 decides the operation mode of the doherty amplifier 1 to be the 1 st doherty operation mode if the frequency of one signal is the 2 nd frequency f₂The 1 st input signal source 12 decides the operation mode of the doherty amplifier 1 as the 1 st out-phase operation mode.

The 1 st input signal source 12 determines the operation mode of the doherty amplifier 1 to be the 1 st doherty operation mode, and then outputs a signal of a voltage having an amplitude and a phase corresponding to the 1 st doherty operation mode as a 1 st signal to the 1 st transistor 16 via the 1 st input matching circuit 14.

The 1 st input signal source 12 determines the operation mode of the doherty amplifier 1 as the 1 st out-phase operation mode, and then outputs a signal of a voltage having an amplitude and a phase corresponding to the 1 st out-phase operation mode as a 1 st signal to the 1 st transistor 16 via the 1 st input matching circuit 14.

In addition, the 1 st signal contains the same information as that contained in one signal.

If the frequency of another signal output from the signal source 11 is the 1 st frequency f₁The 2 nd input signal source 13 decides the operation mode of the doherty amplifier 1 as the 1 st doherty operation mode if the frequency of another signal output from the signal source 11 is the 2 nd frequency f₂The 2 nd input signal source 13 decides the operation mode of the doherty amplifier 1 as the 1 st out-phase operation mode.

The 2 nd input signal source 13 determines the operation mode of the doherty amplifier 1 to the 1 st doherty operation mode, and then outputs a signal of a voltage having an amplitude and a phase corresponding to the 1 st doherty operation mode as a 2 nd signal to the 2 nd transistor 20 via the 2 nd input matching circuit 15.

When the operation mode of the doherty amplifier 1 is determined to be the 1 st out-of-phase operation mode, the 2 nd input signal source 13 outputs a signal of a voltage having an amplitude and a phase corresponding to the 1 st out-of-phase operation mode as a 2 nd signal to the 2 nd transistor 20 via the 2 nd input matching circuit 15.

In addition, the 2 nd signal contains the same information as that contained in the other signal.

The 1 st transistor 16 receives the 1 st signal output from the 1 st input signal source 12 via the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st transmission line 25 in the 1 st output circuit 24.

The 2 nd transistor 20 receives the 2 nd signal output from the 2 nd input signal source 13 via the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd transmission line 28 in the 2 nd output circuit 27.

The 1 st output circuit 24 outputs the 1 st signal from the output terminal 16b of the 1 st transistor 16, transmits the 1 st signal, and outputs the 1 st signal to the combining circuit 31.

The 2 nd output circuit 27 outputs the 2 nd signal from the output terminal 20b of the 2 nd transistor 20, transmits the 2 nd signal, and outputs the 2 nd signal to the combining circuit 31.

The synthesizing circuit 31 synthesizes the 1 st signal transmitted from the 1 st output circuit 24 and the 2 nd signal transmitted from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to an external load 34 via an output matching circuit 33.

Next, the saturated output operation of the doherty amplifier 1 in the 1 st doherty operation mode and the back-off operation of the doherty amplifier 1 in the 1 st doherty operation mode will be specifically described.

Here, for convenience of explanation, the output resistance of the 1 st transistor 16 and the output resistance of the 2 nd transistor 20 are Ropt, respectively.

Further, the characteristic impedance of the 1 st output circuit 24 and the characteristic impedance of the 2 nd output circuit 27 are Ropt, respectively.

Further, the impedance when the load 34 is viewed from the combining point 32 is 0.5 × Ropt.

In the 1 st Doherty operation mode, the frequency of the 1 st signal and the frequency of the 2 nd signal are the 1 st frequency f₁. The frequency of the 1 st signal and the frequency of the 2 nd signal respectively comprise the 1 st frequencyRate f₁Of the frequency range of (3)₀In this case, the electrical length of the 1 st output circuit 24 is about 90 degrees, and the electrical length of the 2 nd output circuit 27 is about 180 degrees.

Next, for the 1 st frequency f₁Is the center frequency f₀The examples of (a) are illustrated.

Fig. 4 is an explanatory diagram showing the 1 st signal and the 2 nd signal in the 1 st doherty operation mode.

Fig. 4A shows the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 4B shows the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 4C shows a phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13. The phase difference is a value obtained by subtracting the phase of the 2 nd signal output from the 2 nd input signal source 13 from the phase of the 1 st signal output from the 1 st input signal source 12.

Each horizontal axis in fig. 4A, 4B, and 4C shows the voltage of the synthesized signal output from the synthesizing circuit 31. The voltage is a normalized voltage.

[ operation at the time of saturated output of the Doherty amplifier 1 in the 1 st Doherty operation mode ]

The operation at the time of saturation output of the doherty amplifier 1 in the 1 st doherty operation mode will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 4A and 4B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about 90 degrees to the 1 st input matching circuit 14.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 4A and 4B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the operation at the time of saturation output, both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation, and the phase of the 1 st signal output from the 1 st input signal source 12 leads the phase of the 2 nd signal output from the 2 nd input signal source 13 by 90 degrees. Further, the electrical length of the 2 nd output circuit 27 is 90 degrees longer than that of the 1 st output circuit 24.

Therefore, the phase of the 1 st signal output from the 1 st output circuit 24 to the combining circuit 31 and the phase of the 2 nd signal output from the 2 nd output circuit 27 to the combining circuit 31 are in phase.

The combining circuit 31 performs in-phase combining of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to the output matching circuit 33.

The output matching circuit 33 receives the synthesized signal from the synthesizing circuit 31, converts the impedance of the synthesizing point 32 into the impedance of the external load 34, and outputs the synthesized signal to the load 34.

In the saturation output operation, the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27 have the same amplitude at the combining point 32, and the 1 st signal and the 2 nd signal are combined in phase by the combining circuit 31. At this time, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

At this time, the characteristic impedance of the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 1 st output circuit 24 coincide with each other at Ropt, and therefore the 1 st output circuit 24 does not modulate the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 in accordance with Ropt.

Further, since the characteristic impedance of the 2 nd output circuit 27 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 coincide with each other at Ropt, the 2 nd output circuit 27 does not modulate the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 in accordance with Ropt.

The impedance seen from the current source 18 of the 1 st transistor 16 and the impedance seen from the current source 22 of the 2 nd transistor 20 both become Ropt, and saturated power is obtained from the doherty amplifier 1.

[ operation at the time of back-off of the Doherty amplifier 1 in the 1 st Doherty operation mode ]

Next, the operation of the doherty amplifier 1 in the 1 st doherty operation mode in the back-off period will be described.

Fig. 5 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 1 st doherty operation mode.

Fig. 6 is an explanatory diagram showing a load change in the operation at the time of back-off of the doherty amplifier 1 in the 1 st doherty operation mode.

In the operation at the time of back-off, only the 1 st transistor 16 performs the signal amplification operation, and the 2 nd transistor 20 stops the signal amplification operation.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes approximately half the saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 4A and 4B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude of "0.5" of the voltage of the synthesized signal output from the synthesizing circuit 31 and having a phase of about 90 degrees to the 1 st input matching circuit 14.

The amplitude of the 1 st signal whose voltage of the synthesized signal outputted from the synthesis circuit 31 becomes "0.5" is larger than zero and smaller than the maximum value of the amplitude.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes zero to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 4A and 4B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude of "0.5" of the voltage of the synthesized signal output from the synthesizing circuit 31 and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The amplitude of the 2 nd signal at which the voltage of the synthesized signal output from the synthesis circuit 31 becomes "0.5" is zero.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

Even if the 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, the amplitude of the 2 nd signal is zero, and therefore the 2 nd transistor 20 stops and does not perform the signal amplification operation.

Since the 2 nd transistor 20 is stopped, the current source 22 of the 2 nd transistor 20 is in an open state as shown in fig. 5.

In the operation at the time of back-off, since the electrical length of the 2 nd output circuit 27 is 180 degrees, the impedance when the 2 nd transistor 20 is viewed from the combining point 32 becomes infinite.

Since the impedance when the 2 nd transistor 20 is viewed from the combining point 32 is infinite, the impedance when the combining circuit 31 is viewed from the 1 st output circuit 24 becomes 0.5 × Ropt.

Since the characteristic impedance of the 1 st output circuit 24 itself is Ropt and the impedance when the combining circuit 31 is viewed from the 1 st output circuit 24 is 0.5 × Ropt, the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 is modulated from Ropt to 2 × Ropt as shown in fig. 6.

The 1 st output circuit 24 modulates the impedance of the combining point 32 viewed from the current source 18 of the 1 st transistor 16 from Ropt to 2 × Ropt, and thereby, when the output power of the 1 st transistor 16 is lower than the saturation power, a high-resistance load is connected to the 1 st transistor 16. That is, when the output power of the 1 st transistor 16 is lower than the saturation power, the load resistance of the 1 st transistor 16 becomes 2 × Ropt larger than Ropt.

The 1 st transistor 16 is connected to a load having a high resistance, and thus can perform an efficient amplification operation.

Next, the doherty amplifier 1 operating in the 1 st outphasing operation mode will be described.

As shown in FIG. 2, the 1 st out-phasing operation mode is such that the frequency of the 1 st signal and the frequency of the 2 nd signal are each higher than the 1 st frequency f₁Low 2 nd frequency f₂The operational mode of the time.

Fig. 7 is an explanatory diagram showing the 1 st signal and the 2 nd signal in the 1 st out-of-phase operation mode.

Fig. 7A shows the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 7B shows the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 7C shows a phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13. The phase difference is a value obtained by subtracting the phase of the 2 nd signal output from the 2 nd input signal source 13 from the phase of the 1 st signal output from the 1 st input signal source 12.

Each horizontal axis in fig. 7A, 7B, and 7C shows a current of the synthesized signal output from the synthesizing circuit 31. The current is a normalized current.

In the 1 st out-of-phase operation mode, as shown in fig. 7A, the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13 monotonically increase as the current of the synthesized signal output from the synthesizing circuit 31 increases.

The amplitude of the 1 st signal output from the 1 st input signal source 12 is the same value as the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

The output power of the 1 st transistor 16 becomes a saturation power when the amplitude of the 1 st signal is maximum, and the output power of the 2 nd transistor 20 becomes a saturation power when the amplitude of the 2 nd signal is maximum.

The phase of the 1 st signal output from the 1 st input signal source 12 monotonically decreases as the current of the synthesized signal output from the synthesis circuit 31 increases.

The phase of the 2 nd signal output from the 2 nd input signal source 13 monotonically increases with an increase in the current of the synthesized signal output from the synthesis circuit 31.

The absolute values of the phase of the 1 st signal and the phase of the 2 nd signal are equal, and the signs of the phase of the 1 st signal and the phase of the 2 nd signal are different from each other. The sign of the phase of the 1 st signal is a positive sign and the sign of the phase of the 2 nd signal is a negative sign.

Therefore, the larger the current of the synthesized signal output from the synthesis circuit 31, the smaller the phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

For example, if the current of the synthesized signal output from the synthesizing circuit 31 is "0", the phase difference is 240 degrees, and if the current of the synthesized signal output from the synthesizing circuit 31 is "1", the phase difference is 60 degrees.

The 1 st out-phase operation mode includes a saturation output operation and a back-off operation.

In the operation at the time of back-off included in the 1 st out-of-phase operation mode, the 2 nd transistor 20 is not stopped, and both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation.

In the 1 st out-of-phase operation mode, the frequency of the 1 st signal and the frequency of the 2 nd signal are the 2 nd frequency f₂. If the 2 nd frequency f₂For example, 0.67 xf₀The electrical length of the 1 st output circuit 24 becomes about 60 degrees, and the electrical length of the 2 nd output circuit 27 becomes about 120 degrees.

Next, for the 2 nd frequency f₂Is 0.67 xf₀The examples of (a) are illustrated.

[ operation at the time of saturated output of the Doherty amplifier 1 in the 1 st outphasing operation mode ]

The operation at the time of the saturated output of the doherty amplifier 1 in the 1 st outphasing operation mode will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 7A and 7B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude at which the current of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about 30 degrees to the 1 st input matching circuit 14.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 7A and 7B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude at which the current of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about-30 degrees to the 2 nd input matching circuit 15.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the saturated output operation, both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation, and the phase of the 1 st signal output from the 1 st input signal source 12 leads the phase of the 2 nd signal output from the 2 nd input signal source 13 by 60 degrees. Further, the electrical length of the 2 nd output circuit 27 is 60 degrees longer than that of the 1 st output circuit 24.

Therefore, the phase of the 1 st signal output from the 1 st output circuit 24 to the combining circuit 31 and the phase of the 2 nd signal output from the 2 nd output circuit 27 to the combining circuit 31 are in phase.

The combining circuit 31 performs in-phase combining of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to the output matching circuit 33.

The output matching circuit 33 receives the synthesized signal from the synthesizing circuit 31, converts the impedance of the synthesizing point 32 into the impedance of the external load 34, and outputs the synthesized signal to the load 34.

In the saturation output operation, the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27 have the same amplitude at the combining point 32, and the 1 st signal and the 2 nd signal are combined in phase by the combining circuit 31. At this time, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

At this time, the characteristic impedance of the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 1 st output circuit 24 coincide with each other at Ropt, and therefore the 1 st output circuit 24 does not modulate the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 in accordance with Ropt.

Further, since the characteristic impedance of the 2 nd output circuit 27 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 coincide with each other at Ropt, the 2 nd output circuit 27 does not modulate the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 in accordance with Ropt.

The impedance seen from the current source 18 of the 1 st transistor 16 and the impedance seen from the current source 22 of the 2 nd transistor 20 both become Ropt, and saturated power is obtained from the doherty amplifier 1.

[ operation at the time of back-off of the Doherty amplifier 1 in the out-of-phase operation mode 1]

The operation of the doherty amplifier 1 in the 1 st outphasing operation mode at the time of back-off will be described.

Fig. 8 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 1 st outphasing operation mode.

Fig. 9 is an explanatory diagram showing a load change in the operation at the time of back-off of the doherty amplifier 1 in the 1 st out-phase operation mode.

Here, as the operation in the back-off operation, for example, an operation when the output power of each of the 1 st transistor 16 and the 2 nd transistor 20 becomes approximately one-third of the saturation power will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes about one third of the saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, the 1 st input signal source 12 outputs the 1 st signal having a phase of about 60 degrees different from a phase of about 30 degrees when the output power of the 1 st transistor 16 becomes the saturation power by +30 degrees to the 1 st input matching circuit 14. The amplitude of the 1 st signal at this time corresponds to the current of the synthesized signal corresponding to the 1 st signal having a phase of about 60 degrees.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes about one third of the saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, the 2 nd input signal source 13 outputs the 2 nd signal having a phase of about-60 degrees different from a phase of about-30 degrees when the output power of the 2 nd transistor 20 becomes the saturation power by-30 degrees to the 2 nd input matching circuit 15. The amplitude of the 2 nd signal at this time corresponds to the current of the synthesized signal corresponding to the 2 nd signal having a phase of about-60 degrees.

The phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13 is 120 degrees.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the back-off operation included in the 1 st out-phase operation mode, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

Since the phase of the 1 st signal output from the 1 st output circuit 24 is a phase that is different by about 60 degrees by +30 degrees from the phase during operation in the saturated output, the impedance Ropt when the combining point 32 is observed from the 1 st output circuit 24 becomes an inductive region. In fig. 9, the impedance when the 2 nd transistor 20 is viewed from the combining point 32 becomes the point X.

The characteristic impedance of the 1 st output circuit 24 itself is Ropt, and the electrical length of the 1 st output circuit 24 is about 60 degrees.

Therefore, as shown in fig. 9, the 1 st output circuit 24 modulates the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 from the X point to 3 × Ropt according to an electrical length of about 60 degrees.

Since the phase of the 2 nd signal output from the 2 nd output circuit 27 is a phase different from the phase during operation at the time of saturation output by about-30 degrees, the impedance Ropt when the combining point 32 is viewed from the 2 nd output circuit 27 becomes a capacitive region. In fig. 9, the impedance when the 2 nd transistor 20 is viewed from the combining point 32 becomes the Y point.

The characteristic impedance of the 2 nd output circuit 27 itself is Ropt, and the electrical length of the 2 nd output circuit 27 is about 120 degrees.

Therefore, as shown in fig. 9, the 2 nd output circuit 27 modulates the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 from the Y point to 3 × Ropt according to an electrical length of about 120 degrees.

The 1 st output circuit 24 modulates the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 to 3 × Ropt, and thereby, when the output power of the 1 st transistor 16 is lower than the saturation power, a high resistance load is connected to the 1 st transistor 16. That is, when the output power of the 1 st transistor 16 is lower than the saturation power, the load resistance of the 1 st transistor 16 becomes 3 × Ropt larger than Ropt.

The 1 st transistor 16 is connected to a load having a high resistance, and thus can perform an efficient amplification operation.

The 2 nd output circuit 27 modulates the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 to 3 × Ropt, and thereby, when the output power of the 2 nd transistor 20 is lower than the saturation power, a high resistance load is connected to the 2 nd transistor 20. That is, when the output power of the 2 nd transistor 20 is lower than the saturation power, the load resistance of the 2 nd transistor 20 becomes 3 × Ropt larger than Ropt.

Since the 2 nd transistor 20 is in a state in which a load having a high resistance is connected, an efficient amplification operation can be performed.

In the above embodiment 1, the doherty amplifier 1 is configured as follows: the signal mode in which the 1 st signal amplified by the 1 st transistor 16 and the 2 nd signal amplified by the 2 nd transistor 20 are synthesized in an in-phase manner and the signal mode in which the 1 st signal amplified by the 1 st transistor 16 and the 2 nd signal amplified by the 2 nd transistor 20 are synthesized in an out-of-phase manner are switched in accordance with the frequency, and the operation mode is switched to the doherty operation mode or the out-of-phase operation mode in accordance with the signal mode after the switching. Therefore, even if the frequency of the 1 st signal amplified by the 1 st transistor 16 and the frequency of the 2 nd signal amplified by the 2 nd transistor 20 change, the doherty amplifier 1 can make the efficiency characteristic in the back-off wider.

Embodiment mode 2

In embodiment 2, the doherty amplifier 1 operating in the 2 nd out-phase operation mode will be described.

The configuration of the doherty amplifier 1 of embodiment 2 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 shows a configuration diagram of the doherty amplifier 1 of embodiment 2.

As shown in FIG. 2, the 2 nd out-phasing operation mode is such that the frequency of the 1 st signal and the frequency of the 2 nd signal are respectively higher than the 1 st frequency f₁High 3 rd frequency f₃The operational mode of the time.

Fig. 10 is an explanatory diagram showing the 1 st signal and the 2 nd signal in the 2 nd out-of-phase operation mode.

Fig. 10A shows the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 10B shows the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 10C shows a phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13. The phase difference is a value obtained by subtracting the phase of the 2 nd signal output from the 2 nd input signal source 13 from the phase of the 1 st signal output from the 1 st input signal source 12.

Each horizontal axis in fig. 10A, 10B, and 10C shows a current of the synthesized signal output from the synthesizing circuit 31. The current is a normalized current.

In the 2 nd out-of-phase operation mode, as shown in fig. 10A, the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13 each monotonically increase as the current of the synthesized signal output from the synthesizing circuit 31 increases.

The amplitude of the 1 st signal output from the 1 st input signal source 12 is the same value as the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

The output power of the 1 st transistor 16 becomes a saturation power when the amplitude of the 1 st signal is maximum, and the output power of the 2 nd transistor 20 becomes a saturation power when the amplitude of the 2 nd signal is maximum.

The phase of the 1 st signal output from the 1 st input signal source 12 monotonically decreases as the current of the synthesized signal output from the synthesis circuit 31 increases.

The phase of the 2 nd signal output from the 2 nd input signal source 13 monotonically increases with an increase in the current of the synthesized signal output from the synthesis circuit 31.

The absolute values of the phase of the 1 st signal and the phase of the 2 nd signal are equal, and the signs of the phase of the 1 st signal and the phase of the 2 nd signal are different from each other.

For example, if the current of the synthesized signal output from the synthesizing circuit 31 is "0", the phase difference is 60 degrees, and if the current of the synthesized signal output from the synthesizing circuit 31 is "1", the phase difference is 120 degrees.

In the doherty amplifier 1 of embodiment 2, the output resistance of each of the 1 st transistor 16 and the 2 nd transistor 20 is Ropt, and the impedance when the load 34 is viewed from the combining point 32 is 0.5 × Ropt.

The 2 nd out-phase operation mode includes a saturation output operation and a back-off operation.

In the operation at the time of back-off included in the 2 nd out-of-phase operation mode, the 2 nd transistor 20 is not stopped, and both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation.

In the 2 nd out-of-phase operation mode, the frequency of the 1 st signal and the frequency of the 2 nd signal are the 3 rd frequency f₃. If the 3 rd frequency f₃For example, 1.33 xf₀The electrical length of the 1 st output circuit 24 becomes about 120 degrees, and the electrical length of the 2 nd output circuit 27 becomes about 240 degrees.

Next, for the 3 rd frequency f₃Is 1.33 xf₀The examples of (a) are illustrated.

[ operation at the time of saturated output of the Doherty amplifier 1 in the 2 nd out-of-phase operation mode ]

The operation at the time of the saturated output of the doherty amplifier 1 in the 2 nd out-phasing operation mode will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 10A and 10B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude at which the current of the signal output from the combining circuit 31 becomes "1" and having a phase of about 60 degrees to the 1 st input matching circuit 14.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 10A and 10B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude at which the current of the signal output from the combining circuit 31 becomes "1" and having a phase of about-60 degrees to the 2 nd input matching circuit 15.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the saturated output operation, both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation, and the phase of the 1 st signal output from the 1 st input signal source 12 is advanced by 120 degrees from the phase of the 2 nd signal output from the 2 nd input signal source 13. Further, the electrical length of the 2 nd output circuit 27 is 120 degrees longer than that of the 1 st output circuit 24.

Therefore, the phase of the 1 st signal output from the 1 st output circuit 24 to the combining circuit 31 and the phase of the 2 nd signal output from the 2 nd output circuit 27 to the combining circuit 31 are in phase.

The combining circuit 31 performs in-phase combining of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to the output matching circuit 33.

The output matching circuit 33 receives the synthesized signal from the synthesizing circuit 31, converts the impedance of the synthesizing point 32 into the impedance of the external load 34, and outputs the synthesized signal to the load 34.

In the saturation output operation, the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27 have the same amplitude at the combining point 32, and the 1 st signal and the 2 nd signal are combined in phase by the combining circuit 31. At this time, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

At this time, the characteristic impedance of the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 1 st output circuit 24 coincide with each other at Ropt, and therefore the 1 st output circuit 24 does not modulate the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 in accordance with Ropt.

Further, since the characteristic impedance of the 2 nd output circuit 27 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 coincide with each other at Ropt, the 2 nd output circuit 27 does not modulate the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 in accordance with Ropt.

The impedance seen from the current source 18 of the 1 st transistor 16 and the impedance seen from the current source 22 of the 2 nd transistor 20 both become Ropt, and saturated power is obtained from the doherty amplifier 1.

[ operation at the time of back-off of the Doherty amplifier 1 in the out-of-phase operation mode 2]

The operation of the doherty amplifier 1 in the 2 nd out-phasing operation mode at the time of back-off will be described.

Fig. 11 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 2 nd out-phase operation mode.

Here, as the operation in the back-off operation, for example, an operation when the output power of each of the 1 st transistor 16 and the 2 nd transistor 20 becomes approximately one-third of the saturation power will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes about one third of the saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, the 1 st input signal source 12 outputs the 1 st signal having a phase that is about 30 degrees different from a phase of about 60 degrees when the output power of the 1 st transistor 16 becomes the saturation power by-30 degrees to the 1 st input matching circuit 14. The amplitude of the 1 st signal at this time corresponds to the current of the synthesized signal corresponding to the 1 st signal having a phase of about 30 degrees.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes about one third of the saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, the 2 nd input signal source 13 outputs the 2 nd signal having a phase of about-30 degrees different from a phase of about-60 degrees when the output power of the 2 nd transistor 20 becomes the saturation power by +30 degrees to the 2 nd input matching circuit 15. The amplitude of the 2 nd signal at this time corresponds to the current of the synthesized signal corresponding to the 2 nd signal having a phase of about-30 degrees.

The phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13 is 120 degrees.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the back-off operation included in the 2 nd out-phase operation mode, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

Since the phase of the 1 st signal output from the 1 st output circuit 24 is different from the phase during operation at the time of saturated output by about 30 degrees, Ropt, which is the impedance when the combining point 32 is observed from the 1 st output circuit 24, becomes an inductive region.

The characteristic impedance of the 1 st output circuit 24 itself is Ropt, and the electrical length of the 1 st output circuit 24 is about 120 degrees.

Therefore, the 1 st output circuit 24 modulates the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 to 3 × Ropt according to an electrical length of about 120 degrees.

Since the phase of the 2 nd signal output from the 2 nd output circuit 27 is a phase different from the phase during operation at the time of saturated output by about-30 degrees by +30 degrees, Ropt, which is the impedance when the combining point 32 is viewed from the 2 nd output circuit 27, becomes a capacitive region.

The characteristic impedance of the 2 nd output circuit 27 itself is Ropt, and the electrical length of the 2 nd output circuit 27 is about 240 degrees.

Therefore, the 2 nd output circuit 27 modulates the impedance when the combining point 32 is observed from the current source 22 of the 2 nd transistor 20 into 3 × Ropt according to an electrical length of about 240 degrees.

The 1 st output circuit 24 modulates the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 to 3 × Ropt, and thereby, when the output power of the 1 st transistor 16 is lower than the saturation power, a high resistance load is connected to the 1 st transistor 16. That is, when the output power of the 1 st transistor 16 is lower than the saturation power, the load resistance of the 1 st transistor 16 becomes 3 × Ropt larger than Ropt.

The 1 st transistor 16 is connected to a load having a high resistance, and thus can perform an efficient amplification operation.

The 2 nd output circuit 27 modulates the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 to 3 × Ropt, and thereby, when the output power of the 2 nd transistor 20 is lower than the saturation power, a high resistance load is connected to the 2 nd transistor 20. That is, when the output power of the 2 nd output circuit 27 is lower than the saturation power, the load resistance of the 2 nd output circuit 27 becomes 3 × Ropt larger than Ropt.

Since the 2 nd transistor 20 is in a state in which a load having a high resistance is connected, an efficient amplification operation can be performed.

As described above, in the doherty amplifier 1 operating in the 2 nd out-of-phase operation mode, the efficiency characteristic in the back-off can be made wide as in the doherty amplifier 1 operating in the 1 st doherty operation mode.

Embodiment 3

In embodiment 3, a description will be given of the doherty amplifier 1 which operates in the 2 nd doherty operation mode.

The configuration of the doherty amplifier 1 of embodiment 3 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 is a diagram showing the configuration of the doherty amplifier 1 of embodiment 3.

As shown in FIG. 2, the 2 nd Doherty operation mode is such that the frequency of the 1 st signal and the frequency of the 2 nd signal are respectively higher than the 2 nd frequency f₂Low 4 th frequency f₄The operational mode of the time.

Fig. 12 is an explanatory diagram showing the 1 st signal and the 2 nd signal in the 2 nd doherty operation mode.

Fig. 12A shows the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 12B shows the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 12C shows a phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13. The phase difference is a value obtained by subtracting the phase of the 2 nd signal output from the 2 nd input signal source 13 from the phase of the 1 st signal output from the 1 st input signal source 12.

Each horizontal axis in fig. 12A, 12B, and 12C shows the voltage of the synthesized signal output from the synthesizing circuit 31. The voltage is a normalized voltage.

In the 2 nd doherty operation mode, as shown in fig. 12A, the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13 are monotonically increased as the voltage of the composite signal output from the composite circuit 31 increases. The amplitude of the 2 nd signal when the amplitude of the 1 st signal is zero is greater than zero.

The output power of the 1 st transistor 16 becomes a saturation power when the amplitude of the 1 st signal is maximum, and the output power of the 2 nd transistor 20 becomes a saturation power when the amplitude of the 2 nd signal is maximum.

As shown in fig. 12B, the phase of the 1 st signal output from the 1 st input signal source 12 is about 45 degrees, the phase of the 2 nd signal output from the 2 nd input signal source 13 is about 0 degree, and the phase of the 1 st signal is advanced by about 45 degrees from the phase of the 2 nd signal.

In the doherty amplifier 1 of embodiment 3, the output resistance of each of the 1 st transistor 16 and the 2 nd transistor 20 is Ropt, and the impedance when the load 34 is viewed from the combining point 32 is 0.5 × Ropt.

The 2 nd doherty operation mode includes an operation at the time of saturated output and an operation at the time of backoff.

In the operation at the time of back-off included in the 2 nd doherty operation mode, the 1 st transistor 16 is stopped, and only the 2 nd transistor 20 performs an amplification operation of a signal.

The frequency of the 1 st signal and the frequency of the 2 nd signal are respectively the 4 th frequency f₄. If the 4 th frequency f₄For example, 0.5 xf₀The electrical length of the 1 st output circuit 24 becomes about 45 degrees, and the electrical length of the 2 nd output circuit 27 becomes about 90 degrees.

Next, for the 4 th frequency f₄Is 0.5 xf₀The examples of (a) are illustrated.

[ operation at the time of saturated output of the Doherty amplifier 1 in the 2 nd Doherty operation mode ]

The operation at the time of saturation output of the doherty amplifier 1 in the 2 nd doherty operation mode will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 12A and 12B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude at which the voltage of the signal output from the combining circuit 31 becomes "1" and having a phase of about 45 degrees to the 1 st input matching circuit 14.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 12A and 12B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude at which the voltage of the signal output from the combining circuit 31 becomes "1" and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the saturated output operation, both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation, and the phase of the 1 st signal output from the 1 st input signal source 12 is advanced by 45 degrees from the phase of the 2 nd signal output from the 2 nd input signal source 13. Further, the electrical length of the 2 nd output circuit 27 is longer than that of the 1 st output circuit 24 by 45 degrees.

Therefore, the phase of the 1 st signal output from the 1 st output circuit 24 to the combining circuit 31 and the phase of the 2 nd signal output from the 2 nd output circuit 27 to the combining circuit 31 are in phase.

The combining circuit 31 performs in-phase combining of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to the output matching circuit 33.

The output matching circuit 33 receives the synthesized signal from the synthesizing circuit 31, converts the impedance of the synthesizing point 32 into the impedance of the external load 34, and outputs the synthesized signal to the load 34.

In the saturation output operation, the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27 have the same amplitude at the combining point 32, and the 1 st signal and the 2 nd signal are combined in phase by the combining circuit 31. At this time, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

At this time, the characteristic impedance of the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 1 st output circuit 24 coincide with each other at Ropt, and therefore the 1 st output circuit 24 does not modulate the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 in accordance with Ropt.

Further, since the characteristic impedance of the 2 nd output circuit 27 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 coincide with each other at Ropt, the 2 nd output circuit 27 does not modulate the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 in accordance with Ropt.

The impedance seen from the current source 18 of the 1 st transistor 16 and the impedance seen from the current source 22 of the 2 nd transistor 20 both become Ropt, and saturated power is obtained from the doherty amplifier 1.

[ operation at the time of back-off of the Doherty amplifier 1 in the 2 nd Doherty operation mode ]

The operation of the doherty amplifier 1 in the 2 nd doherty operation mode in the back-off period will be described.

Fig. 13 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 2 nd doherty operation mode.

In the operation at the time of back-off, only the 2 nd transistor 20 performs the signal amplification operation, and the 1 st transistor 16 stops the signal amplification operation.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes zero as a 1 st signal to the 1 st input matching circuit 14.

Specifically, as shown in fig. 12A and 12B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude of "0.5" of the voltage of the signal output from the combining circuit 31 and having a phase of about 45 degrees to the 1 st input matching circuit 14.

The amplitude of the 1 st signal at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "0.5" is zero.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes, for example, approximately half the saturation power to the 1 st input matching circuit 14 as a 2 nd signal.

Specifically, as shown in fig. 12A and 12B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude of "0.5" of the voltage of the signal output from the combining circuit 31 and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The amplitude of the 2 nd signal whose voltage of the signal outputted from the combining circuit 31 becomes "0.5" is larger than zero and smaller than the maximum value of the amplitude.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

Even if the 1 st signal is received from the 1 st input matching circuit 14, the amplitude of the 1 st signal is zero, and therefore, the 1 st transistor 16 stops and does not perform the signal amplification operation.

Since the 1 st transistor 16 is stopped, the current source 18 of the 1 st transistor 16 is in an open state as shown in fig. 13.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the operation at the time of back-off, since the impedance when the 1 st transistor 16 is viewed from the combining point 32 is infinite, the impedance when the combining circuit 31 is viewed from the 2 nd output circuit 27 becomes 0.5 × Ropt.

Since the characteristic impedance of the 2 nd output circuit 27 itself is Ropt and the impedance when the combining circuit 31 is viewed from the 2 nd output circuit 27 is 0.5 × Ropt, the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 is modulated from Ropt to 2 × Ropt.

The 2 nd output circuit 27 modulates the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 from Ropt to 2 × Ropt, and thereby, when the output power of the 2 nd transistor 20 is lower than the saturation power, a high-resistance load is connected to the 2 nd transistor 20. That is, when the output power of the 2 nd output circuit 27 is lower than the saturation power, the load resistance of the 2 nd output circuit 27 becomes 2 × Ropt larger than Ropt.

Since the 2 nd transistor 20 is in a state in which a load having a high resistance is connected, an efficient amplification operation can be performed.

As described above, in the doherty amplifier 1 operating in the 2 nd doherty operation mode, the efficiency characteristic in the back-off can be made wide as in the doherty amplifier 1 operating in the 1 st doherty operation mode.

Embodiment 4

In embodiment 4, a description will be given of the doherty amplifier 1 which operates in the 3 rd doherty operation mode.

The configuration of the doherty amplifier 1 of embodiment 4 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 shows a configuration diagram of the doherty amplifier 1 of embodiment 4.

As shown in FIG. 2, the 3 rd Doherty operation mode is such that the frequency of the 1 st signal and the frequency of the 2 nd signal are respectively higher than the 3 rd frequency f₃High 5 th frequency f₅The operational mode of the time.

Fig. 14 is an explanatory diagram showing the 1 st signal and the 2 nd signal in the 3 rd doherty operation mode.

Fig. 14A shows the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 14B shows the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13.

Fig. 14C shows a phase difference between the phase of the 1 st signal output from the 1 st input signal source 12 and the phase of the 2 nd signal output from the 2 nd input signal source 13. The phase difference is a value obtained by subtracting the phase of the 2 nd signal output from the 2 nd input signal source 13 from the phase of the 1 st signal output from the 1 st input signal source 12.

Each horizontal axis in fig. 14A, 14B, and 14C shows the voltage of the synthesized signal output from the synthesizing circuit 31. The voltage is a normalized voltage.

In the 3 rd doherty operation mode, as shown in fig. 14A, the amplitude of the 1 st signal output from the 1 st input signal source 12 and the amplitude of the 2 nd signal output from the 2 nd input signal source 13 are monotonically increased as the voltage of the composite signal output from the composite circuit 31 increases. The amplitude of the 2 nd signal when the amplitude of the 1 st signal is zero is greater than zero.

The output power of the 1 st transistor 16 becomes a saturation power when the amplitude of the 1 st signal is maximum, and the output power of the 2 nd transistor 20 becomes a saturation power when the amplitude of the 2 nd signal is maximum.

As shown in fig. 14B, the phase of the 1 st signal output from the 1 st input signal source 12 is about 135 degrees, the phase of the 2 nd signal output from the 2 nd input signal source 13 is about 0 degree, and the phase of the 1 st signal is advanced by about 135 degrees from the phase of the 2 nd signal.

In the doherty amplifier 1 of embodiment 4, the output resistance of each of the 1 st transistor 16 and the 2 nd transistor 20 is Ropt, and the impedance when the load 34 is viewed from the combining point 32 is 0.5 × Ropt.

The 3 rd doherty operation mode includes an operation at the time of saturated output and an operation at the time of backoff.

In the operation at the time of back-off included in the 3 rd doherty operation mode, the 1 st transistor 16 is stopped and only the 2 nd transistor 20 amplifies a signal.

The frequency of the 1 st signal and the frequency of the 2 nd signal are respectively the 5 th frequency f₅. If the 5 th frequency f₅For example, 1.5 xf₀Then, the electrical length of the 1 st output circuit 24 becomes about 135 degrees, and the electrical length of the 2 nd output circuit 27 becomes about 270 degrees.

Next, for the 5 th frequency f₅Is 1.5 xf₀The examples of (a) are illustrated.

[ operation at the time of saturated output of the Doherty amplifier 1 in the 3 rd Doherty operation mode ]

The saturated output operation of the doherty amplifier 1 in the 3 rd doherty operation mode will be described.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes saturation power to the 1 st input matching circuit 14 as a 1 st signal.

Specifically, as shown in fig. 14A and 14B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about 135 degrees to the 1 st input matching circuit 14.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes saturation power to the 2 nd input matching circuit 15 as a 2 nd signal.

Specifically, as shown in fig. 14A and 14B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "1" and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 1 st transistor 16 receives the 1 st signal from the 1 st input matching circuit 14, amplifies the 1 st signal, and outputs the amplified 1 st signal to the 1 st output circuit 24.

The 1 st output circuit 24 transmits the 1 st signal output from the 1 st transistor 16, and outputs the 1 st signal to the synthesizing circuit 31.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transfers the 2 nd signal output from the 2 nd transistor 20, and outputs the 2 nd signal to the synthesizing circuit 31.

In the saturated output operation, both the 1 st transistor 16 and the 2 nd transistor 20 perform the signal amplification operation, and the phase of the 1 st signal output from the 1 st input signal source 12 leads the phase of the 2 nd signal output from the 2 nd input signal source 13 by 135 degrees. Further, the electrical length of the 2 nd output circuit 27 is 135 degrees longer than that of the 1 st output circuit 24.

Therefore, the phase of the 1 st signal output from the 1 st output circuit 24 to the combining circuit 31 and the phase of the 2 nd signal output from the 2 nd output circuit 27 to the combining circuit 31 are in phase.

The combining circuit 31 performs in-phase combining of the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27.

The synthesizing circuit 31 outputs a synthesized signal of the 1 st signal and the 2 nd signal to the output matching circuit 33.

The output matching circuit 33 receives the synthesized signal from the synthesizing circuit 31, converts the impedance of the synthesizing point 32 into the impedance of the external load 34, and outputs the synthesized signal to the load 34.

In the saturation output operation, the 1 st signal output from the 1 st output circuit 24 and the 2 nd signal output from the 2 nd output circuit 27 have the same amplitude at the combining point 32, and the 1 st signal and the 2 nd signal are combined in phase by the combining circuit 31. At this time, the output load of the 1 st transistor 16 and the output load of the 2 nd transistor 20 are in the form of sharing the impedance of the combining point 32.

Therefore, the impedance when the combining point 32 is viewed from the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 both become Ropt.

At this time, the characteristic impedance of the 1 st output circuit 24 and the impedance when the combining point 32 is viewed from the 1 st output circuit 24 coincide with each other at Ropt, and therefore the 1 st output circuit 24 does not modulate the impedance when the combining point 32 is viewed from the current source 18 of the 1 st transistor 16 in accordance with Ropt.

Further, since the characteristic impedance of the 2 nd output circuit 27 and the impedance when the combining point 32 is viewed from the 2 nd output circuit 27 coincide with each other at Ropt, the 2 nd output circuit 27 does not modulate the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 in accordance with Ropt.

The impedance seen from the current source 18 of the 1 st transistor 16 and the impedance seen from the current source 22 of the 2 nd transistor 20 both become Ropt, and saturated power is obtained from the doherty amplifier 1.

[ operation at the time of back-off of the Doherty amplifier 1 in the 3 rd Doherty operation mode ]

The operation of the doherty amplifier 1 in the 3 rd doherty operation mode in the back-off period will be described.

Fig. 15 is an explanatory diagram showing an operation at the time of back-off of the doherty amplifier 1 in the 3 rd doherty operation mode.

In the operation at the time of back-off, only the 2 nd transistor 20 performs the signal amplification operation, and the 1 st transistor 16 stops the signal amplification operation.

The 1 st input signal source 12 outputs a signal in which the output power of the 1 st transistor 16 becomes zero as a 1 st signal to the 1 st input matching circuit 14.

Specifically, as shown in fig. 14A and 14B, the 1 st input signal source 12 outputs a 1 st signal having an amplitude of "0.5" of the voltage of the signal output from the combining circuit 31 and having a phase of about 135 degrees to the 1 st input matching circuit 14.

The amplitude of the 1 st signal at which the voltage of the synthesized signal output from the synthesizing circuit 31 becomes "0.5" is zero.

The 2 nd input signal source 13 outputs a signal in which the output power of the 2 nd transistor 20 becomes, for example, approximately half the saturation power to the 1 st input matching circuit 14 as a 2 nd signal.

Specifically, as shown in fig. 14A and 14B, the 2 nd input signal source 13 outputs the 2 nd signal having an amplitude of "0.5" of the voltage of the synthesized signal output from the synthesizing circuit 31 and having a phase of about 0 degree to the 2 nd input matching circuit 15.

The amplitude of the 2 nd signal whose voltage of the synthesized signal outputted from the synthesis circuit 31 becomes "0.5" is larger than zero and smaller than the maximum value of the amplitude.

The 1 st input matching circuit 14 receives the 1 st signal from the 1 st input signal source 12, converts the impedance of the 1 st input signal source 12 into the input impedance of the 1 st transistor 16, and outputs the 1 st signal to the input terminal 16a of the 1 st transistor 16.

Even if the 1 st signal is received from the 1 st input matching circuit 14, the amplitude of the 1 st signal is zero, and therefore, the 1 st transistor 16 stops and does not perform the signal amplification operation.

Since the 1 st transistor 16 is stopped, the current source 18 of the 1 st transistor 16 is in an open state as shown in fig. 15.

The 2 nd input matching circuit 15 receives the 2 nd signal from the 2 nd input signal source 13, converts the impedance of the 2 nd input signal source 13 into the input impedance of the 2 nd transistor 20, and outputs the 2 nd signal to the input terminal 20a of the 2 nd transistor 20.

The 2 nd transistor 20 receives the 2 nd signal from the 2 nd input matching circuit 15, amplifies the 2 nd signal, and outputs the amplified 2 nd signal to the 2 nd output circuit 27.

The 2 nd output circuit 27 transmits the 2 nd signal output from the 2 nd transistor 20 to the synthesizing circuit 31.

In the operation at the time of back-off, since the impedance when the 1 st transistor 16 is viewed from the combining point 32 is infinite, the impedance when the combining circuit 31 is viewed from the 2 nd output circuit 27 becomes 0.5 × Ropt.

Since the characteristic impedance of the 2 nd output circuit 27 itself is Ropt and the impedance when the combining circuit 31 is viewed from the 2 nd output circuit 27 is 0.5 × Ropt, the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 is modulated from Ropt to 2 × Ropt.

The 2 nd output circuit 27 modulates the impedance when the combining point 32 is viewed from the current source 22 of the 2 nd transistor 20 from Ropt to 2 × Ropt, and thereby, when the output power of the 2 nd transistor 20 is lower than the saturation power, a high-resistance load is connected to the 2 nd transistor 20. That is, when the output power of the 2 nd output circuit 27 is lower than the saturation power, the load resistance of the 2 nd output circuit 27 becomes 2 × Ropt larger than Ropt.

Since the 2 nd transistor 20 is in a state in which a load having a high resistance is connected, an efficient amplification operation can be performed.

As described above, in the doherty amplifier 1 operating in the 3 rd doherty operation mode, the efficiency characteristic in the back-off can be made wide as in the doherty amplifier 1 operating in the 1 st doherty operation mode.

Embodiment 5

In the doherty amplifier 1 shown in fig. 3, the 1 st output circuit 24 has a capacitor 19, a 1 st transmission line 25, and a 1 st capacitor 26.

In addition, in the doherty amplifier 1 shown in fig. 3, the 2 nd output circuit 27 has a capacitor 23, a 2 nd transmission line 28, a 3 rd transmission line 29, and a 2 nd capacitor 30.

In embodiment 5, a description will be given of the doherty amplifier 1 in which the 1 st output circuit 24 has the capacitor 19, the inductor 41, and the 1 st transmission line 42, and the 2 nd output circuit 27 has the capacitor 23, the inductor 43, the 2 nd transmission line 44, and the 3 rd transmission line 45.

The configuration of the doherty amplifier 1 of embodiment 5 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 shows a configuration diagram of the doherty amplifier 1 of embodiment 5.

Fig. 16 is a configuration diagram showing the 1 st output circuit 24 of the doherty amplifier 1 of embodiment 5. In fig. 16, the same reference numerals as in fig. 3 denote the same or corresponding parts, and thus, the description thereof will be omitted.

The 1 st output circuit 24 shown in fig. 16 transmits the 1 st signal output from the 1 st transistor 16 to the combining circuit 31, similarly to the 1 st output circuit 24 shown in fig. 3.

The 1 st output circuit 24 shown in fig. 16 modulates the impedance when the synthesizing circuit 31 is viewed from the 1 st transistor 16 in accordance with the frequency of the 1 st signal amplified by the 1 st transistor 16.

Like the 1 st output circuit 24 shown in fig. 3, the electrical length of the 1 st output circuit 24 shown in fig. 16 changes according to the frequency of the 1 st signal. For example, at the frequency of the 1 st signal is a packetContaining the 1 st frequency f₁Of the frequency range of (3)₀The electrical length of the 1 st output circuit 24 is 90 degrees. However, the electrical length of the 1 st output circuit 24 is not limited to exactly match the electrical length of 90 degrees, and may be shifted from the electrical length of 90 degrees within a range that has no practical problem.

The inductor 41 is realized, for example, by a wire.

One end of the inductor 41 is connected to the output terminal 16b of the 1 st transistor 16, and the other end of the inductor 41 is connected to one end of the 1 st transmission line 42.

One end of the 1 st transmission line 42 is connected to the other end of the inductor 41, and the other end of the 1 st transmission line 42 is connected to the input terminal 31a of the synthesis circuit 31.

For example, the 1 st transmission line 42 is set such that the frequency of the 1 st signal is the 1 st frequency f₁A wire having an electrical length of less than 90 degrees.

Fig. 17 is a block diagram showing the 2 nd output circuit 27 of the doherty amplifier 1 of embodiment 5. In fig. 17, the same reference numerals as in fig. 3 denote the same or corresponding parts, and thus, the description thereof will be omitted.

The 2 nd output circuit 27 shown in fig. 17 transmits the 2 nd signal output from the 2 nd transistor 20 to the combining circuit 31, similarly to the 2 nd output circuit 27 shown in fig. 3.

The 2 nd output circuit 27 shown in fig. 17 modulates the impedance when the synthesizing circuit 31 is viewed from the 2 nd transistor 20 in accordance with the frequency of the 2 nd signal amplified by the 2 nd transistor 20.

Like the 2 nd output circuit 27 shown in fig. 3, the electrical length of the 2 nd output circuit 27 shown in fig. 17 changes according to the frequency of the 2 nd signal. For example, the frequency of the 2 nd signal is the center frequency f₀The electrical length of the 2 nd output circuit 27 is 180 degrees. However, the electrical length of the 2 nd output circuit 27 is not limited to exactly match the electrical length of 180 degrees, and may be shifted from the electrical length of 180 degrees within a range that has no practical problem.

The inductor 43 is realized, for example, by a wire.

One end of the inductor 43 is connected to the output terminal 20b of the 2 nd transistor 20, and the other end of the inductor 43 is connected to one end of the 2 nd transmission line 44.

One end of the 2 nd transmission line 44 is connected to the other end of the inductor 43, and the other end of the 2 nd transmission line 44 is connected to one end of the 3 rd transmission line 45.

The 2 nd transmission line 44 is, for example, a 1 st frequency f at the frequency of the 2 nd signal₁A wire having an electrical length of less than 90 degrees.

One end of the 3 rd transmission line 45 is connected to the other end of the 2 nd transmission line 44, and the other end of the 3 rd transmission line 45 is connected to the input terminal 31b of the combining circuit 31.

For example, the 3 rd transmission line 45 is set such that the frequency of the 2 nd signal is the 1 st frequency f₁A wire having an electrical length of 90 degrees. However, the electrical length of the 3 rd transmission line 45 is not limited to strictly match the electrical length of 90 degrees, and may be shifted from the electrical length of 90 degrees within a range that has no practical problem.

When the 1 st output circuit 24 includes the capacitor 19, the inductor 41, and the 1 st transmission line 42, the impedance when the combining circuit 31 is viewed from the 1 st transistor 16 can be modulated in accordance with the frequency of the 1 st signal, as in the 1 st output circuit 24 shown in fig. 3.

When the 2 nd output circuit 27 includes the capacitor 23, the inductor 43, the 2 nd transmission line 44, and the 3 rd transmission line 45, the impedance when the synthesizing circuit 31 is viewed from the 2 nd transistor 20 can be modulated in accordance with the frequency of the 2 nd signal, as in the 2 nd output circuit 27 shown in fig. 3.

Therefore, the doherty amplifier 1 of embodiment 5 can also widen the efficiency characteristic at the time of back-off, as with the doherty amplifiers 1 of embodiments 1 to 4.

Embodiment 6

In the doherty amplifier 1 shown in fig. 3, the 1 st output circuit 24 has a capacitor 19, a 1 st transmission line 25, and a 1 st capacitor 26.

In addition, in the doherty amplifier 1 shown in fig. 3, the 2 nd output circuit 27 has a capacitor 23, a 2 nd transmission line 28, a 3 rd transmission line 29, and a 2 nd capacitor 30.

In embodiment 6, a description will be given of the doherty amplifier 1 in which the 1 st output circuit 24 includes the capacitor 19, the transmission line 51, the transmission line 52, the capacitor 53, and the capacitor 54, and the 2 nd output circuit 27 includes the capacitor 23, the transmission line 61, the transmission line 62, the transmission line 63, the capacitor 64, and the capacitor 65.

The configuration of the doherty amplifier 1 of embodiment 6 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 shows a configuration diagram of the doherty amplifier 1 of embodiment 6.

Fig. 18 is a configuration diagram showing the 1 st output circuit 24 of the doherty amplifier 1 of embodiment 6. In fig. 18, the same reference numerals as in fig. 3 denote the same or corresponding parts, and thus, the description thereof will be omitted.

Like the 1 st output circuit 24 shown in fig. 3, the 1 st output circuit 24 shown in fig. 18 transmits the 1 st signal output from the 1 st transistor 16 and outputs the 1 st signal to the combining circuit 31.

The 1 st output circuit 24 shown in fig. 18 modulates the impedance when the synthesizing circuit 31 is viewed from the 1 st transistor 16 in accordance with the frequency of the 1 st signal amplified by the 1 st transistor 16.

Like the 1 st output circuit 24 shown in fig. 3, the electrical length of the 1 st output circuit 24 shown in fig. 18 changes according to the frequency of the 1 st signal. For example, the frequency of the 1 st signal includes the 1 st frequency f₁Of the frequency range of (3)₀The electrical length of the 1 st output circuit 24 is 90 degrees. However, the electrical length of the 1 st output circuit 24 is not limited to exactly match the electrical length of 90 degrees, and may be shifted from the electrical length of 90 degrees within a range that has no practical problem.

One end of the transmission line 51 is connected to the output terminal 16b of the 1 st transistor 16, and the other end of the transmission line 51 is connected to one end of the transmission line 52 and one end of the capacitor 53.

One end of the transmission line 52 is connected to the other end of the transmission line 51 and one end of the capacitor 53, respectively, and the other end of the transmission line 52 is connected to the input terminal 31a of the synthesis circuit 31 and one end of the capacitor 54, respectively.

For example, when the frequency of the 1 st signal is the 1 st frequency f₁Time of flight, transmissionThe sum of the electrical length of the line 51 and the electrical length of the transmission line 52 is an electrical length of less than 90 degrees.

The capacitor 53 is connected in parallel with the transmission line 51. That is, one end of the capacitor 53 is connected to the other end of the transmission line 51 and one end of the transmission line 52, respectively, and the other end of the capacitor 53 is connected to the ground.

The capacitor 54 is connected in parallel with the transmission line 52. That is, one end of the capacitor 54 is connected to the other end of the transmission line 52 and the input terminal 31a of the combining circuit 31, and the other end of the capacitor 54 is connected to the ground.

Fig. 19 is a configuration diagram showing the 2 nd output circuit 27 of the doherty amplifier 1 of embodiment 7. In fig. 19, the same reference numerals as in fig. 3 denote the same or corresponding parts, and thus, the description thereof will be omitted.

Similarly to the 2 nd output circuit 27 shown in fig. 3, the 2 nd output circuit 27 shown in fig. 19 transfers the 2 nd signal output from the 2 nd transistor 20 and outputs the 2 nd signal to the synthesizing circuit 31.

The 2 nd output circuit 27 shown in fig. 19 modulates the impedance when the synthesizing circuit 31 is viewed from the 2 nd transistor 20 in accordance with the frequency of the 2 nd signal amplified by the 2 nd transistor 20.

Like the 2 nd output circuit 27 shown in fig. 3, the electrical length of the 2 nd output circuit 27 shown in fig. 19 changes according to the frequency of the 2 nd signal. For example, the frequency of the 2 nd signal is the center frequency f₀The electrical length of the 2 nd output circuit 27 is 180 degrees. However, the electrical length of the 1 st output circuit 24 is not limited to exactly match the electrical length of 180 degrees, and may be shifted from the electrical length of 180 degrees within a range that has no practical problem.

One end of the transmission line 61 is connected to the output terminal 20b of the 2 nd transistor 20, and the other end of the transmission line 61 is connected to one end of the transmission line 62 and one end of the capacitor 64.

One end of the transmission line 62 is connected to the other end of the transmission line 61 and one end of the capacitor 64, respectively, and the other end of the transmission line 62 is connected to one end of the transmission line 63 and one end of the capacitor 65, respectively.

One end of the transmission line 63 is connected to the other end of the transmission line 62 and one end of the capacitor 65, respectively, and the other end of the transmission line 63 is connected to the input terminal 31b of the synthesis circuit 31.

For example, when the frequency of the 1 st signal is the 1 st frequency f₁In this case, the sum of the electrical length of the transmission line 61, the electrical length of the transmission line 62, and the electrical length of the transmission line 63 is an electrical length smaller than 180 degrees.

The capacitor 64 is connected in parallel with the transmission line 61. That is, one end of the capacitor 64 is connected to the other end of the transmission line 61 and one end of the transmission line 62, respectively, and the other end of the capacitor 64 is connected to the ground.

The capacitor 65 is connected in parallel with the transmission line 62. That is, one end of the capacitor 65 is connected to the other end of the transmission line 62 and one end of the transmission line 63, and the other end of the capacitor 65 is connected to the ground.

When the 1 st output circuit 24 includes the capacitor 19, the transmission line 51, the transmission line 52, the capacitor 53, and the capacitor 54, the impedance when the synthesizing circuit 31 is viewed from the 1 st transistor 16 can be modulated in accordance with the frequency of the 1 st signal, as in the 1 st output circuit 24 shown in fig. 3.

When the 2 nd output circuit 27 includes the capacitor 23, the transmission line 61, the transmission line 62, the transmission line 63, the capacitor 64, and the capacitor 65, the impedance when the synthesizing circuit 31 is viewed from the 2 nd transistor 20 can be modulated in accordance with the frequency of the 2 nd signal, as in the 2 nd output circuit 27 shown in fig. 3.

Therefore, the doherty amplifier 1 of embodiment 6 can also widen the efficiency characteristic at the time of back-off, as with the doherty amplifiers 1 of embodiments 1 to 4.

Embodiment 7

In the doherty amplifier 1 shown in fig. 3, a bias voltage substantially equal to the threshold voltage is applied to each of the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20.

The input terminal 16a of the 1 st transistor 16 may be applied with a specific threshold voltage V_thrHigh and 1 st threshold voltage V₁Low bias voltage (hereinafter referred to as "1 st bias voltage V)_{b 1}”)。V_thr<V_{b 1}<V₁。

In addition, the input terminal 20a of the 2 nd transistor 20 may be applied with the specific threshold voltage V_thrHigh and 1 st threshold voltage V₁Low 1 st bias voltage V_{b 1}。

As the 1 st threshold voltage V₁For example, consider the critical voltage V_thrAbout 1.1 times higher.

The configuration of the doherty amplifier 1 of embodiment 7 is the same as that of the doherty amplifier 1 of embodiment 1, and fig. 3 shows a configuration diagram of the doherty amplifier 1 of embodiment 7.

A 1 st bias voltage V is applied to an input terminal 16a of the 1 st transistor 16_{b 1}Is applied with a threshold voltage V_thrThe gain of the 1 st transistor 16 becomes higher than that in the case of the same bias voltage.

Further, a 1 st bias voltage V is applied to the input terminal 20a of the 2 nd transistor 20_{b 1}Under the condition of being applied with the threshold voltage_thrThe gain of the 2 nd transistor 20 becomes higher than that in the case of the same bias voltage.

The input terminal 16a of the 1 st transistor 16 may be applied with a specific threshold voltage V_thrLow and specific 2 nd threshold voltage V₂High bias voltage (hereinafter referred to as "2 nd bias voltage V_{b 2}”)。V₂<V_{b 2}<V_thr。

In addition, the input terminal 20a of the 2 nd transistor 20 may be applied with the specific threshold voltage V_thrLow and specific 2 nd threshold voltage V₂High 2 nd bias voltage V_{b 2}。

As the 2 nd threshold voltage V₂For example, consider the critical voltage V_thrAbout 0.9 times higher.

A 2 nd bias voltage V is applied to an input terminal 16a of the 1 st transistor 16_{b 2}Is applied with a threshold voltage V_thrThe 1 st transistor 16 has higher efficiency than the case of the same bias voltage.

Further, a 2 nd bias is applied to the input terminal 20a of the 2 nd transistor 20Set voltage V_{b 2}Is applied with a threshold voltage V_thrThe efficiency of the 2 nd transistor 20 is higher than that in the case of the same bias voltage.

For example, when the 1 st doherty operation mode is performed, the 1 st bias voltage V is applied to the input terminal 16a of the 1 st transistor 16_{b 1}And the 2 nd bias voltage V is applied to the input terminal 20a of the 2 nd transistor 20_{b 2}In the case of (3), both the gain and the efficiency of the doherty amplifier 1 can be improved.

For example, when the 1 st transistor 16 is in the 2 nd or 3 rd doherty operation mode, the 2 nd bias voltage V is applied to the input terminal 16a thereof_{b 2}And the 1 st bias voltage V is applied to the input terminal 20a of the 2 nd transistor 20_{b 1}In the case of (3), both the gain and the efficiency of the doherty amplifier 1 can be improved.

Embodiment 8

In embodiment 8, a description will be given of a doherty amplifier 1 having a control circuit 71, in which the control circuit 71 controls bias voltages applied to an input terminal 16a of a 1 st transistor 16 and an input terminal 20a of a 2 nd transistor 20, respectively.

Fig. 20 is a block diagram showing the doherty amplifier 1 of embodiment 8. In fig. 20, the same reference numerals as in fig. 3 denote the same or corresponding parts, and thus, the description thereof will be omitted.

The control circuit 71 has a variable power supply 72, a gate bias circuit 73, and a gate bias circuit 74.

The control circuit 71 controls bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively.

The variable power supply 72 is a power supply capable of varying the voltage output to the gate bias circuit 73 and the voltage output to the gate bias circuit 74.

The gate bias circuit 73 is implemented by an inductor, for example.

One end of the gate bias circuit 73 is connected to the variable power supply 72, and the other end of the gate bias circuit 73 is connected to the input terminal 16a of the 1 st transistor 16 and the other end of the 1 st input matching circuit 14b, respectively.

The gate bias circuit 73 increases the bias voltage applied to the input terminal 16a of the 1 st transistor 16 if the output voltage of the variable power supply 72 becomes high, and the gate bias circuit 73 decreases the bias voltage applied to the input terminal 16a of the 1 st transistor 16 if the output voltage of the variable power supply 72 becomes low.

The gate bias circuit 74 is implemented by an inductor, for example.

One end of the gate bias circuit 74 is connected to the variable power supply 72, and the other end of the gate bias circuit 74 is connected to the input terminal 20a of the 2 nd transistor 20 and the other end of the 2 nd input matching circuit 15b, respectively.

The gate bias circuit 74 increases the bias voltage applied to the input terminal 20a of the 2 nd transistor 20 if the output voltage of the variable power supply 72 becomes high, and decreases the bias voltage applied to the input terminal 20a of the 2 nd transistor 20 if the output voltage of the variable power supply 72 becomes low.

Next, the operation of the doherty amplifier 1 shown in fig. 20 will be described. However, since the portions other than the control circuit 71 are the same as those of the doherty amplifier 1 shown in fig. 3, only the operation of the control circuit 71 will be described here.

The control circuit 71 controls the bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively, according to the respective frequencies of the 1 st signal and the 2 nd signal.

Specifically, if the frequency of the 1 st signal and the frequency of the 2 nd signal are the 1 st frequency f₁And the operation mode of the doherty amplifier 1 is the 1 st doherty operation mode, the control circuit 71 applies the 1 st bias voltage V to the input terminal 16a of the 1 st transistor 16_{b 1}. In addition, the control circuit 71 applies the 2 nd bias voltage V to the input terminal 20a of the 2 nd transistor 20_{b 2}。

If the frequency of the 1 st signal and the frequency of the 2 nd signal are the 4 th frequency f₄And the operation mode of the doherty amplifier 1 is the 2 nd doherty operation mode, the control circuit 71 applies the 2 nd bias voltage V to the input terminal 16a of the 1 st transistor 16_{b 2}. Further, the pair of control circuits 71The 1 st bias voltage V is applied to the input terminal 20a of the 2 nd transistor 20_{b 1}。

If the frequency of the 1 st signal and the frequency of the 2 nd signal are the 5 th frequency f₅And the operation mode of the doherty amplifier 1 is the 3 rd doherty operation mode, the control circuit 71 applies the 2 nd bias voltage V to the input terminal 16a of the 1 st transistor 16_{b 2}. In addition, the control circuit 71 applies the 1 st bias voltage V to the input terminal 20a of the 2 nd transistor 20_{b 1}。

If the frequency of the 1 st signal and the frequency of the 2 nd signal are the 2 nd frequency f₂And the operation mode of the doherty amplifier 1 is the 1 st out-phase operation mode, the control circuit 71 applies the 1 st bias voltage V to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively_{b 1}。

If the frequency of the 1 st signal and the frequency of the 2 nd signal are the 3 rd frequency f₃And the operation mode of the doherty amplifier 1 is the 2 nd out-phase operation mode, the control circuit 71 applies the 1 st bias voltage V to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively_{b 1}。

The control circuit 71 controls the bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively, based on the respective frequencies of the 1 st signal and the 2 nd signal, thereby improving both the gain and the efficiency of the doherty amplifier 1.

In the doherty amplifier 1 shown in fig. 20, the control circuit 71 controls the bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively, in accordance with the respective frequencies of the 1 st signal and the 2 nd signal.

However, this is merely an example, and the control circuit 71 may control the bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively, based on the power of the 1 st signal and the power of the 2 nd signal output from the signal source 11.

The control circuit 71 increases the bias voltage applied to the input terminal 16a of the 1 st transistor 16 if the power of the 1 st signal output from the 1 st input signal source 12 becomes large, and the control circuit 71 decreases the bias voltage applied to the input terminal 16a of the 1 st transistor 16 if the power of the 1 st signal output from the 1 st input signal source 12 becomes small.

The control circuit 71 increases the bias voltage applied to the input terminal 20a of the 2 nd transistor 20 if the power of the 2 nd signal output from the 2 nd input signal source 13 becomes large, and the control circuit 71 decreases the bias voltage applied to the input terminal 20a of the 2 nd transistor 20 if the power of the 2 nd signal output from the 2 nd input signal source 13 becomes small.

The control circuit 71 controls the bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively, based on the respective powers of the 1 st signal and the 2 nd signal output from the signal source 11, thereby suppressing the variation of the gain of the 1 st transistor 16 and the 2 nd transistor 20 with respect to the input power.

Embodiment 9

In embodiment 9, a description will be given of a doherty amplifier 1 having a control circuit 81, in which the control circuit 81 controls bias voltages applied to the output terminal 16b of the 1 st transistor 16 and the output terminal 20b of the 2 nd transistor 20, respectively.

Fig. 21 is a block diagram showing the doherty amplifier 1 of embodiment 9. In fig. 21, the same reference numerals as those in fig. 3 and 20 denote the same or corresponding parts, and thus, the description thereof will be omitted.

The control circuit 81 has a variable power supply 82, a gate bias circuit 73, a gate bias circuit 74, a drain bias circuit 83, and a drain bias circuit 84.

In the doherty amplifier 1 shown in fig. 21, the control circuit 81 has a gate bias circuit 73 and a gate bias circuit 74. However, this is merely an example, and the control circuit 81 may have only the variable power supply 82, the drain bias circuit 83, and the drain bias circuit 84 without having the gate bias circuit 73 and the gate bias circuit 74.

Similarly to the control circuit 71 shown in fig. 20, the control circuit 81 controls bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively.

Further, the control circuit 81 controls bias voltages applied to the output terminal 16b of the 1 st transistor 16 and the output terminal 20b of the 2 nd transistor 20, respectively.

The variable power supply 82 is a power supply as follows: the voltage output to the gate bias circuit 73 and the voltage output to the gate bias circuit 74 can be made variable, and the voltage output to the drain bias circuit 83 and the voltage output to the drain bias circuit 84 can be made variable.

The drain bias circuit 83 is implemented by an inductor, for example.

One end of the drain bias circuit 83 is connected to the variable power supply 82, and the other end of the drain bias circuit 83 is connected to the output terminal 16b of the 1 st transistor 16 and one end of the 1 st transmission line 25, respectively.

The drain bias circuit 83 increases the bias voltage applied to the output terminal 16b of the 1 st transistor 16 if the output voltage of the variable power supply 82 becomes high, and decreases the bias voltage applied to the output terminal 16b of the 1 st transistor 16 if the output voltage of the variable power supply 82 becomes low.

The drain bias circuit 84 is implemented, for example, by an inductor.

One end of the drain bias circuit 84 is connected to the variable power supply 82, and the other end of the drain bias circuit 84 is connected to the output terminal 20b of the 2 nd transistor 20 and one end of the 2 nd transmission line 28, respectively.

The drain bias circuit 84 increases the bias voltage applied to the output terminal 20b of the 2 nd transistor 20 if the output voltage of the variable power supply 82 becomes high, and decreases the bias voltage applied to the output terminal 20b of the 2 nd transistor 20 if the output voltage of the variable power supply 82 becomes low.

Next, the operation of the doherty amplifier 1 shown in fig. 21 will be described. However, since the portions other than the control circuit 81 are the same as those of the doherty amplifier 1 shown in fig. 3 and 20, only the operation of the control circuit 81 will be described here.

Similarly to the control circuit 71 shown in fig. 20, the control circuit 81 controls bias voltages applied to the input terminal 16a of the 1 st transistor 16 and the input terminal 20a of the 2 nd transistor 20, respectively.

The control circuit 81 increases the bias voltage applied to the output terminal 16b of the 1 st transistor 16 if the power of the 1 st signal output from the 1 st input signal source 12 becomes large, and decreases the bias voltage applied to the output terminal 16b of the 1 st transistor 16 if the power of the 1 st signal output from the 1 st input signal source 12 becomes small.

The control circuit 81 increases the bias voltage applied to the output terminal 20b of the 2 nd transistor 20 if the power of the 2 nd signal output from the 2 nd input signal source 13 becomes large, and decreases the bias voltage applied to the output terminal 20b of the 2 nd transistor 20 if the power of the 2 nd signal output from the 2 nd input signal source 13 becomes small.

The control circuit 81 controls the bias voltages applied to the output terminal 16b of the 1 st transistor 16 and the output terminal 20b of the 2 nd transistor 20, respectively, based on the respective powers of the 1 st signal and the 2 nd signal output from the signal source 11, thereby improving both the gain and the efficiency of the doherty amplifier 1 based on the respective input powers of the 1 st transistor 16 and the 2 nd transistor 20.

In the present application, it is possible to freely combine the respective embodiments, to modify any of the components of the respective embodiments, or to omit any of the components of the respective embodiments within the scope of the invention.

Industrial applicability

The present invention is applicable to a doherty amplifier and a communication apparatus that combine an amplified 1 st signal and an amplified 2 nd signal.

Description of the reference symbols

1: a Doherty amplifier; 11: a signal source; 12: 1, inputting a signal source; 13: a 2 nd input signal source; 14: a 1 st input matching circuit; 15: a 2 nd input matching circuit; 16: a 1 st transistor; 16 a: an input terminal; 16 b: an output terminal; 17: a capacitor; 18: a current source; 19: a capacitor; 20: a 2 nd transistor; 20 a: an input terminal; 20 b: an output terminal; 21: a capacitor; 22: a current source; 23: a capacitor; 24: a 1 st output circuit; 25: 1 st transmission line; 26: a 1 st capacitor; 27: a 2 nd output circuit; 28: a 2 nd transmission line; 29: a 3 rd transmission line; 30: a 2 nd capacitor; 31: a synthesizing circuit; 31 a: an input terminal; 31 b: an input terminal; 32: synthesizing points; 33: an output matching circuit; 34: a load; 41: an inductor; 42: 1 st transmission line; 43: an inductor; 44: a 2 nd transmission line; 45: a 3 rd transmission line; 51. 52: a transmission line; 53. 54: a capacitor; 61. 62, 63: a transmission line; 64. 65: a capacitor; 71: a control circuit; 72: a variable power supply; 73. 74: a gate bias circuit; 81: a control circuit; 82: a variable power supply; 83. 84: a drain bias circuit.