阅读说明：本技术 电压测量电路、蓄电装置 (Voltage measurement circuit and power storage device ) 是由 松田祐树 富士松将克 于 2020-05-25 设计创作，主要内容包括：电压测量电路(4)具备：各分压电路(5A)、分压电路(5B)及分压电路(5C),对串联连接的各级蓄电元件(1A)、蓄电元件(1B)及蓄电元件(1C)的电压进行分压；各开关(6A)、开关(6B)及开关(6C),切断各级分压电路(5A)、分压电路(5B)及分压电路(5C)的电流；测量部(7),基于各级分压电路(5A)、分压电路(5B)及分压电路(5C)的输出来测量各级所述蓄电元件(1A)、蓄电元件(1B)及蓄电元件(1C)的电压,各级所述分压电路(5A)、分压电路(5B)及分压电路(5C)具备：第1电阻(R1),与接地连接；第2电阻(R2),与对应的所述蓄电元件的正极连接,各级所述开关(6A)、开关(6B)及开关(6C)之中给定级数的开关(6B)是将源极与所述第1电阻(R1)连接且将漏极与所述第2电阻(R2)连接的N沟道的FET(6B),所述FET(6B)的源极是相对于所述测量部(7)的电压输出端子。(A voltage measurement circuit (4) is provided with: each voltage dividing circuit (5A), voltage dividing circuit (5B), and voltage dividing circuit (5C) that divide the voltage of each of the stages of the power storage elements (1A), power storage elements (1B), and power storage elements (1C) connected in series; each switch (6A), each switch (6B), and each switch (6C) cuts off the current of each stage of the voltage dividing circuit (5A), each stage of the voltage dividing circuit (5B), and each stage of the voltage dividing circuit (5C); a measurement unit (7) that measures the voltage of each of the power storage elements (1A, 1B, and 1C) based on the output of each of the voltage divider circuits (5A, 5B, and 5C), wherein each of the voltage divider circuits (5A, 5B, and 5C) includes: a 1 st resistor (R1) connected to ground; and a 2 nd resistor (R2) connected to the positive electrode of the corresponding power storage element, wherein the switches (6B) of a given number of stages among the switches (6A), switches (6B) and switches (6C) of each stage are N-channel FETs (6B) having a source connected to the 1 st resistor (R1) and a drain connected to the 2 nd resistor (R2), and wherein the source of the FET (6B) is a voltage output terminal to the measurement unit (7).)

1. A voltage measurement circuit is characterized by comprising:

each voltage dividing circuit that divides a voltage of each stage of the power storage elements connected in series;

each switch for cutting off the current of the voltage dividing circuit; and

a measurement unit that measures a voltage of the storage element in each stage based on an output of the voltage division circuit in each stage,

each of the voltage dividing circuits includes:

the 1 st resistor is connected with the ground; and

a 2 nd resistor connected to a positive electrode of the corresponding power storage element,

the switches of a given number of the switches of each number are N-channel FETs having a source connected to the 1 st resistor and a drain connected to the 2 nd resistor, and the source of the FET is a voltage output terminal to the measurement unit.

2. Voltage measurement circuit according to claim 1,

the switches of the stages higher than the given stage among the switches of each stage are P-channel FETs located on the high potential side of the voltage dividing circuit.

3. Voltage measurement circuit according to claim 2,

the switches of the stages lower than the given stage among the switches of each stage are N-channel FETs connecting the source with the ground.

4. Voltage measurement circuit according to claim 3,

the voltage measurement circuit has:

a 1 st drive line driving the FET of P channel; and

a 2 nd drive line, the FET driving an N-channel,

the 1 st drive line is connected to ground via a 1 st switch,

the 2 nd drive line is connected with the positive electrode of the highest-level electric storage element through the 2 nd switch.

5. Voltage measurement circuit according to any one of claims 1 to 4,

the maximum voltage of the positive electrodes of the given number of stages of the electric storage elements is higher than the allowable value of the measurement unit, and the minimum voltage of the positive electrodes is lower than the threshold voltage of the FET.

6. A voltage measurement circuit is characterized by comprising:

a voltage dividing circuit that divides a voltage of the electric storage element;

a switch for cutting off the current of the voltage dividing circuit; and

a measurement unit that measures a voltage of the electric storage element based on an output of the voltage division circuit,

the voltage divider circuit includes:

the 1 st resistor is connected with the ground; and

a 2 nd resistor connected to a positive electrode of the electric storage element,

the switch is an N-channel FET having a source connected to the 1 st resistor and a drain connected to the 2 nd resistor, and the source of the FET is a voltage output terminal to the measurement unit.

7. An electricity storage device is characterized by comprising:

one or a plurality of storage elements connected in series; and

a voltage measurement circuit as claimed in any one of claims 1 to 6.

Technical Field

The present invention relates to a voltage measuring circuit for an electric storage device.

Background

A voltage divider circuit may be used for measuring the voltage of the storage element. Patent document 1 discloses that a switching element is provided to cut off the current of the voltage dividing circuit when not being measured.

Prior art documents

Patent document

Patent document 1: japanese patent laid-open No. 2000-195566

Disclosure of Invention

The present technology eliminates both the problem of overvoltage for the measurement section and the problem of malfunction of the FET.

Means for solving the problems

The voltage measurement circuit includes: each voltage dividing circuit that divides a voltage of each stage of the power storage elements connected in series; each switch cuts off the current of each stage of voltage division circuit; a measurement unit that measures a voltage of the power storage element in each stage based on an output of a voltage division circuit in each stage, the voltage division circuit in each stage including: the 1 st resistor is connected with the ground; and a 2 nd resistor connected to a positive electrode of the corresponding power storage element, wherein a given number of switches among the switches in each stage are N-channel FETs having a source connected to the 1 st resistor and a drain connected to the 2 nd resistor, and the source of the FET is a voltage output terminal to the measurement unit.

The present technology can be applied to an electric storage device.

Effects of the invention

According to the present technology, both the problem of overvoltage to the measurement unit and the problem of operation failure of the FET can be eliminated.

Drawings

Fig. 1 is a circuit diagram of a voltage measurement circuit.

Fig. 2 is a circuit diagram of a voltage measurement circuit.

Fig. 3 is a circuit diagram of a voltage measurement circuit.

Fig. 4 is an exploded perspective view of the battery.

Fig. 5 is a plan view of the secondary battery.

Fig. 6 is a sectional view taken along line a-a of fig. 5.

Fig. 7 is a side view of an automobile.

Fig. 8 is a block diagram of a battery.

Fig. 9 is a circuit diagram of an analog processing circuit.

Detailed Description

Fig. 1 is a circuit diagram of a voltage measurement circuit 2. The voltage measurement circuit 2 is used for measuring the voltage of 3 power storage elements 1A, 1B, and 1C connected in series, and includes a 1 st voltage division circuit 5A, a 1 st FET 6A, a 2 nd voltage division circuit 5B, a 2 nd FET 6B, a 3 rd voltage division circuit 5C, a 3 rd FET 6C, and a measurement unit 7. The FET is a Field effect transistor (Field effect transistor).

The 1 st voltage divider circuit 5A is a circuit that divides the voltage of the positive electrode of the 1 st-stage power storage element 1A having the lowest potential (voltage of P1). The 2 nd voltage divider circuit 5B is a circuit that divides the voltage of the positive electrode of the 2 nd-stage power storage element 1B (the voltage of P2). The 3 rd voltage dividing circuit 5C is a circuit that divides the voltage of the positive electrode of the 3 rd-stage power storage element 1C having the highest potential (voltage of P3).

The 1 st voltage divider circuit 5A includes a 1 st resistor R1a and a 2 nd resistor R2a, and a connection point D1 of the two resistors is connected to the 1 st input port 8A of the measurement unit 7 via a signal line. The 2 nd voltage divider circuit 5B includes a 1 st resistor R1B and a 2 nd resistor R2B, and a connection point D2 of the two resistors is connected to the 2 nd input port 8B of the measurement unit 7 via a signal line. The 3 rd voltage divider circuit 5C includes a 1 st resistor R1C and a 2 nd resistor R2C, and a connection point D3 of the two resistors is connected to the 3 rd input port 8C of the measurement unit 7 via a signal line.

The measurement unit 7 is a CPU or MPU that detects the voltage of the positive electrode of the 1 st-stage power storage element 1A based on the voltage at the 1 st input port 8A, detects the voltage of the positive electrode of the 2 nd-stage power storage element 1B based on the voltage at the 2 nd input port 8B, and detects the voltage of the positive electrode of the 3 rd-stage power storage element 1C based on the voltage at the 3 rd input port 8C.

The voltage measuring circuit 2 is provided with a 1 st FET 6A of an N channel on the low potential side of the 1 st voltage dividing circuit 5A. The voltage measuring circuit 2 is provided with a 2 nd FET 6B of an N channel on the low potential side of the 2 nd voltage dividing circuit 5B. The voltage measuring circuit 2 is provided with a 3 rd FET 6C of an N channel on the low potential side of the 3 rd voltage dividing circuit 5C. In the non-measurement state, the 1 st FET 6A, the 2 nd FET 6B, and the 3 rd FET 6C are turned off, whereby the current of the 1 st voltage divider circuit 5A, the current of the 2 nd voltage divider circuit 5B, and the current of the 3 rd voltage divider circuit 5C can be cut off.

When the FET 6 is disposed on the low potential side of the voltage divider circuit 5, if the FET 6 is turned off, the measurement unit 7 is turned on with the positive electrode of the power storage element 1. Therefore, as shown in fig. 1, during the current interruption period (when the FET is turned off), the voltage of the positive electrode of the corresponding power storage element 1 is applied to the input port 8 of the measurement unit 7.

Since the voltage of the positive electrode of the power storage element 1 increases by the number of stages, the input port 8 for measuring the power storage element 1 of the higher order may exceed the allowable voltage.

For example, when the allowable voltage of the input ports 8A to 8C is 5V and the cell voltage Vs of the power storage elements 1A to 1C is 3.6V, the voltage of the positive electrode of the 1 st-stage power storage element 1A is 3.6V and the voltage of the positive electrode of the 2 nd-stage power storage element 1B is 7.2V. Since the voltage of the positive electrode of the 2 nd stage power storage element 1B is higher than the allowable voltage, an overvoltage higher than the allowable value is applied to the 2 nd input port 8B when the 2 nd FET 6B is turned off.

Since the voltage of the positive electrode of the 3 rd stage power storage element 1C is higher than the voltage of the positive electrode of the 2 nd stage power storage element 1B, when the 3 rd FET 6C is turned off, an overvoltage higher than the allowable value is applied to the 3 rd input port 8C, as in the case of the 2 nd stage.

The voltage measurement circuit 3 of fig. 2 is different from the voltage measurement circuit 2 in the 2 nd FET 6B and the 3 rd FET 6C. The 2 nd FET 6B and the 3 rd FET 6C are P-channels, and are located on the high potential side of the 2 nd voltage dividing circuit 5B and the 3 rd voltage dividing circuit 5C.

By providing the 2 nd FET 6B and the 3 rd FET 6C on the high potential side, the 2 nd power storage element 1B and the 3 rd power storage element 1C can be disconnected from the 2 nd input port 8B and the 3 rd input port 8C when the FET 6 is turned off, and thus application of an overvoltage to the 2 nd input port 8B and the 3 rd input port 8C can be suppressed.

However, since the P-channel FET 6 disposed on the high potential side of the voltage divider circuit 5 operates with the positive electrode of the corresponding power storage element 1 as a reference potential, if the positive electrode of the corresponding power storage element 1 is low in voltage, Vgs > Vth is not achieved even if SW is turned on and the gate and the ground are turned on, and the FET 6 may not be switched from off to on. That is, even if the FET 6 is turned on to measure the voltage, the FET 6 is not switched from off, and the voltage of the positive electrode of the power storage element 1 may not be measured.

For example, when the cell voltage Vs of each stage of the power storage elements 1A to 1C is 1.2V and Vth is 2.5V, the voltage of the positive electrode of the 2 nd stage power storage element 1B is 2.4V. Therefore, Vgs when SW is turned on is 2.4V, which is less than Vth of 2.5V. In the case where Vgs < Vth, the 2 nd FET 6B is not turned on, resulting in poor measurement. Vgs is the gate-source voltage of the FET 6, and Vth is the threshold voltage (voltage at which the FET switches from off to on).

On the other hand, when the voltage of the positive electrode of the 3 rd stage power storage element 1C is 3.6V, and SW is turned on and the gate and the ground are turned on, Vgs > Vth, and therefore the 3 rd FET 6C operates normally.

As illustrated in the 2 nd-stage power storage element 1B, when the maximum voltage of the positive electrode of the power storage element 1 is higher than the allowable voltage of the measurement unit 7 and the minimum voltage of the positive electrode is lower than the threshold voltage Vth of the FET, the problem of the overvoltage and the problem of the malfunction of the FET cannot be solved regardless of whether the FET 6 is disposed on the low potential side or the high potential side of the voltage dividing circuit 5.

That is, when the N-channel FET 6 is selected to be arranged on the low potential side of the voltage dividing circuit 5, the problem of overvoltage cannot be solved, and when the P-channel FET 6 is selected to be arranged on the high potential side of the voltage dividing circuit 5, the problem of operation failure of the FET cannot be solved. The high potential side is an upstream side (power supply side) in the current flowing direction, and the low potential side is a downstream side (ground side) in the current flowing direction.

Further, if measures are taken to cope with both overvoltage and operation failure of the FET in advance regardless of the magnitude relation between the voltage of the positive electrode of the storage element and the allowable voltage of the measurement unit and the magnitude relation between the voltage of the positive electrode of the storage element and the threshold voltage of the FET, the reliability of the voltage measurement circuit is improved.

The inventors investigated whether or not it is possible to suppress an operation failure of the FET and suppress an overvoltage to the measurement unit by reconsidering the positional relationship between the channel of the FET, and the voltage divider circuit.

Fig. 3 is a circuit diagram of the voltage measuring circuit 4. The voltage measuring circuit 4 is different from the voltage measuring circuit 3 of fig. 2 in that the channel of the 2 nd stage FET 6B is changed and the positional relationship with respect to the voltage dividing circuit 5B is changed.

The FET 6B is an N-channel. The FET 6B is located between the 1 st resistor R1B and the 2 nd resistor R2B of the voltage divider circuit 5B, and has a source connected to the 1 st resistor R1B and a drain connected to the 2 nd resistor R2B. Since FET 6B operates with the ground reference, switching can be performed without depending on the voltage of the positive electrode of the 2 nd-stage power storage element 1B (the voltage of P2). Therefore, the operation failure of the FET 6B can be suppressed.

The FET 6B has a source connected to the 2 nd input port 8B of the measurement unit 7 via a signal line, and is a voltage output terminal for the measurement unit 7. When the FET 6B is off, the 2 nd input port 8B is turned on to the ground via the 1 st resistor R1B, and therefore the voltage of the positive electrode of the 2 nd-stage power storage element 1B is not applied. Thus, it is recognized that both the problem of the overvoltage and the problem of the malfunction of the FET can be solved by reconsidering the positional relationship between the channel of the FET 6 and the voltage dividing circuit 5.

The outline of the present invention will be described below.

The voltage measurement circuit includes: each voltage dividing circuit that divides a voltage of each stage of the power storage elements connected in series; each switch cuts off the current of each stage of voltage division circuit; and a measurement unit that measures a voltage of the power storage element in each stage based on an output of the voltage division circuit in each stage, wherein each of the voltage division circuits includes: the 1 st resistor is connected with the ground; and a 2 nd resistor connected to a positive electrode of the corresponding power storage element, wherein a given number of switches among the switches in each stage are N-channel FETs having a source connected to the 1 st resistor and a drain connected to the 2 nd resistor, and the source of the FET is a voltage output terminal to the measurement unit.

Since the N-channel FET operates as a ground reference, the switches of a given number of stages can be switched independently of the voltage of the positive electrode of the storage element. Therefore, the operation failure of the FET can be suppressed.

The FET is located between the 1 st resistor and the 2 nd resistor, and the source is a voltage output terminal for the measurement section. When the FET is turned off, the measuring unit is electrically connected to the ground via the 1 st resistor and is not electrically connected to the positive electrode of the storage element. Therefore, in the non-measurement state, the voltage of the positive electrode of the electric storage element can be suppressed from being applied to the measurement unit to become an overvoltage at a predetermined number of stages. It is possible to suppress a failure of the measurement unit and prevent the voltage monitoring of the power storage element from being disabled.

The switches of the stages higher than the given stage among the switches of each stage may also be P-channel FETs located on the high potential side of the voltage dividing circuit. In the non-measurement state, the voltage of the positive electrode of the electric storage element can be suppressed from being applied to the measurement unit to become an overvoltage at a number of steps higher than the predetermined number of steps. It is possible to suppress a failure of the measurement unit and prevent the voltage monitoring of the power storage element from being disabled.

The switches of the stages lower than the given stage among the switches of each stage may also be N-channel FETs connecting the source with the ground. Since the operation is performed on the ground reference, the occurrence of the operation failure of the FET can be suppressed at a number of stages lower than a predetermined number of stages.

The voltage measurement circuit may also have: a 1 st drive line driving the FET of P channel; and a 2 nd drive line that drives the N-channel FET, the 1 st drive line being connected to ground via a 1 st switch, the 2 nd drive line being connected to a positive electrode of the highest-order power storage element via a 2 nd switch.

If the 1 st switch is turned on, the 1 st drive line is turned on to the ground, thereby lowering the voltage of the gate, and thus the P-channel FET can be switched from off to on. When the 2 nd switch is turned on, the 2 nd drive line is turned on with the positive electrode of the highest power storage element, and the voltage of the gate is increased, so that the N-channel FET can be switched from off to on. The 2 nd drive line is connected to the positive electrode of the highest power storage element, and thus the drive voltage of the FET is easily ensured. That is, even when the cell voltage of each power storage element is low, the voltage of the positive electrode of the highest-order power storage element is the sum of the cell voltages, and therefore, the driving voltage of the FET is easily ensured.

The maximum voltage of the positive electrodes of the power storage elements of the given number of stages may be higher than the allowable value of the measurement unit, and the minimum voltage of the positive electrodes may be lower than the threshold voltage of the FET. When the positive electrode of the electric storage element is at the highest voltage, overvoltage becomes a problem, and when the positive electrode of the electric storage element is at the lowest voltage, malfunction of the FET becomes a problem.

< embodiment 1>

1. Description of the construction of the battery 50

As shown in fig. 4, the battery 50 includes a battery pack 60, a control board 65, and a housing 71.

The housing 71 includes a main body 73 made of a synthetic resin material and a lid 74. The main body 73 has a bottomed cylindrical shape. The main body 73 includes a bottom surface 75 and 4 side surfaces 76. An upper opening 77 is formed at the upper end by 4 side surface parts 76.

The housing 71 houses the battery pack 60 and the control board 65. The battery pack 60 has 12 secondary batteries 62. The 12 secondary batteries 62 are connected in 3 parallel and 4 series. The control board 65 includes a circuit board CP and electronic components mounted on the circuit board CP, and is disposed above the battery pack 60.

The lid 74 closes the upper opening 77 of the main body 73. An outer peripheral wall 78 is provided around the lid 74. The lid 74 has a substantially T-shaped projection 79 in a plan view. The 1 st external terminal 51 of the positive electrode is fixed to one corner portion of the front portion of the lid 74, and the 2 nd external terminal 52 of the negative electrode is fixed to the other corner portion.

As shown in fig. 5 and 6, the secondary battery 62 has an electrode body 83 housed together with a nonaqueous electrolyte in a rectangular parallelepiped case 82. As an example, the secondary battery 62 is a lithium ion secondary battery. The housing 82 includes a housing main body 84 and a cover 85 for closing an upper opening thereof.

The electrode body 83 is not shown in detail, and a separator made of a porous resin film is disposed between a negative electrode element in which an active material is applied to a base material made of a copper foil and a positive electrode element in which an active material is applied to a base material made of an aluminum foil. Both of them are strip-shaped, and are wound in a flat shape so as to be able to be housed in the case main body 84 in a state where the negative electrode element and the positive electrode element are shifted in position with respect to the separator on opposite sides in the width direction.

A positive electrode terminal 87 is connected to the positive electrode element via a positive electrode current collector 86, and a negative electrode terminal 89 is connected to the negative electrode element via a negative electrode current collector 88. The positive electrode current collector 86 and the negative electrode current collector 88 are each composed of a flat base portion 90 and a leg portion 91 extending from the base portion 90. The base portion 90 has a through hole. The leg 91 is connected to the positive electrode element or the negative electrode element. The positive electrode terminal 87 and the negative electrode terminal 89 are composed of a terminal body 92 and a shaft 93 projecting downward from the center of the lower surface thereof. The terminal main body 92 and the shaft 93 of the positive electrode terminal 87 are integrally formed of aluminum (a single material). In the negative electrode terminal 89, the terminal main body portion 92 is made of aluminum, and the shaft portion 93 is made of copper, and these are assembled. The terminal main body portions 92 of the positive electrode terminal 87 and the negative electrode terminal 89 are disposed at both ends of the cover 85 with spacers 94 made of an insulating material interposed therebetween, and are exposed outward from the spacers 94.

The cap 85 has a pressure relief valve 95. As shown in fig. 5, the pressure relief valve 95 is located between the positive terminal 87 and the negative terminal 89. The pressure relief valve 95 opens when the internal pressure of the housing 82 exceeds a limit value, thereby reducing the internal pressure of the housing 82.

As shown in fig. 7, the battery 50 can be mounted on the automobile 10 and used. The battery 50 may also be used for starting the engine 20 as a drive device of the automobile 10.

2. Electrical structure of the battery 50

Fig. 8 is a block diagram of the battery 50. The battery 50 is an "electric storage device". The battery 50 includes a battery pack 60, a current sensor 53, a current cut-off device 55, an analog processing circuit 130, a management unit 100, and a temperature sensor (not shown) for detecting the temperature of the battery pack 60.

The battery pack 60 is composed of 4 secondary batteries 62A, 62B, 62C, and 62D connected in series. The secondary battery 62 is an "electric storage element". The battery 50 is rated at 12V.

Battery pack 60, current sensor 53, and current cut-off device 55 are connected in series via power supply line 66 and power supply line 67. The power supply lines 66 and 67 are examples of current paths.

The power supply line 66 is a power supply line connecting the 1 st external terminal 51 and the positive electrode of the battery pack 60. The power supply line 67 is a power supply line connecting the 2 nd external terminal 52 and the negative electrode of the battery pack 60.

The current sensor 53 is provided in a power supply line 67 of the negative electrode of the battery pack 60. The current sensor 53 is capable of measuring the current I of the battery pack 60.

The current cut-off device 55 is provided in the power supply line 67 of the negative electrode of the battery pack 60. The current cut-off device 55 can use a FET (Field effect transistor). The current cutoff device 55 is normally controlled to be closed. The battery 50 can be protected by disconnection at the time of abnormality.

The analog processing circuit 130 divides the voltage of the positive electrode of the 1 st secondary battery 62A, the voltage of the positive electrode of the 2 nd secondary battery 62B, the voltage of the positive electrode of the 3 rd secondary battery 62C, and the voltage of the positive electrode of the 4 th secondary battery 62D, respectively, and outputs the divided voltages to the management unit 100. The reason why the voltage is divided to be lowered is to make the allowable voltage of the CPU 110 not be exceeded.

The management unit 100 includes a CPU 110 and a memory 120. The CPU 110 is a measurement unit that measures the voltage of the secondary battery 62, and has 4 input ports 111A to 111D for voltage measurement. The allowable voltage of the input port 111 is 5V.

The management unit 100 performs a monitoring process of the battery 50 based on the outputs of the analog processing circuit 130, the current sensor 53, and the temperature sensor. The monitoring process of the battery 50 may be a process of monitoring an abnormality of the current I of the battery 50, an abnormality of the cell voltage Vs of each secondary battery 62, and an abnormality of the temperature of the battery 50.

As shown in fig. 8, the battery 50 is connected to a battery motor 21 as an engine starter, an alternator 23 as a vehicle generator, and a general electric load 25. The electrical load 25 is rated at 12V in general, and examples thereof include a vehicle ECU mounted on the vehicle 10, an air conditioner, an audio system, a car navigation system, and an auxiliary device.

3. Analog processing circuit

Fig. 9 is a circuit diagram of the analog processing circuit 130. The analog processing circuit 130 has a 1 st voltage dividing circuit 131A, a 1 st FET 133A, a 2 nd voltage dividing circuit 131B, a 2 nd FET 133B, a 3 rd voltage dividing circuit 131C, a 3 rd FET 133C, a 4 th voltage dividing circuit 131D, a 4 th FET 133D, a 1 st drive line L5, and a 2 nd drive line L6. The FET is a field effect transistor.

The 1 st voltage divider circuit 131A is a circuit that divides the voltage of the positive electrode of the 1 st-stage secondary battery 62A having the lowest potential (voltage of P1). The 1 st voltage dividing circuit 131A includes a 1 st resistor R1A and a 2 nd resistor R2a, and a connection point D1 of the two resistors is connected to the 1 st input port 111A of the CPU 110 via a signal line L1. LH is a low pass filter.

The 1 st FET 133A is an N-channel and is located on the high potential side of the 1 st voltage dividing circuit 131A. The 1 st FET 133A has a source connected to the 1 st voltage dividing circuit 131A and a drain connected to the positive electrode of the 1 st secondary battery 62A. The gate of the 1 st FET 133A is connected to a 2 nd drive line L6 via a gate resistance Rg.

The 2 nd voltage divider circuit 131B is a circuit that divides the voltage of the positive electrode of the 2 nd-stage secondary battery 62B (the voltage of P2). The 2 nd voltage divider circuit 131B includes a 1 st resistor R1B and a 2 nd resistor R2B, and a connection point D2 of the two resistors is connected to the 2 nd input port 111B of the CPU 110 via a signal line L2. LH is a low pass filter.

The 2 nd FET 133B is an N-channel and is located between the 1 st resistor R1B and the 2 nd resistor R2B. The 2 nd FET 133B has a source connected to the 1 st resistor R1B and a drain connected to the 2 nd resistor R2B. The gate of the 2 nd FET 133B is connected to a 2 nd drive line L6 via a gate resistance Rg.

The 3 rd voltage dividing circuit 131C is a circuit that divides the voltage of the positive electrode of the 3 rd-stage secondary battery 62C (voltage of P3). The 3 rd voltage divider circuit 131C includes a 1 st resistor R1C and a 2 nd resistor R2C, and a connection point D3 of the two resistors is connected to the 3 rd input port 111C of the CPU 110 via a signal line L3. LH is a low pass filter.

The 3 rd FET 133C is a P-channel and is located on the high potential side of the 3 rd voltage dividing circuit 131C. The 3 rd FET 133C has a source connected to the positive electrode (P3) of the 3 rd secondary battery 62C and a drain connected to the 3 rd voltage dividing circuit 131C. The gate of the 3 rd FET 133C is connected to the 1 st drive line L5 via a gate resistance Rg.

The 4 th voltage divider circuit 131D is a circuit that divides the voltage of the positive electrode of the 4 th-stage secondary battery 62D having the highest potential (voltage of P4). The 4 th voltage divider circuit 131D includes a 1 st resistor R1D and a 2 nd resistor R2D, and a connection point D4 of the two resistors is connected to the 4 th input port 111D of the CPU 110 via a signal line L4. LH is a low pass filter.

The 4 th FET 133D is a P-channel and is located on the high potential side of the 4 th voltage dividing circuit 131D. The 4 th FET 133D has a source connected to the positive electrode (P4) of the 4 th secondary battery 62D and a drain connected to the 4 th voltage dividing circuit 131D. The gate of the 4 th FET 133D is connected to the 1 st drive line L5 via a gate resistance Rg.

The analog processing circuit 130 has a 1 st switch 141 and a 2 nd switch 143. The 1 st switch 141 is an N-channel FET. The 1 st switch 141 connects the source with ground and the drain with a 1 st drive line L5. The gate of the 1 st switch 141 is connected to the output port 113 of the CPU 110. The 1 st driving line L5 may be turned on with a given high potential when the 1 st switch 141 is turned off. The given high potential may be the positive electrode (P4) of the 4 th-stage secondary battery 62D.

The 2 nd switch 143 is a P-channel FET. The 2 nd switch 143 connects the source with the positive electrode (P4) of the highest-level (4 th-level) secondary battery 62D and the drain with the 2 nd driving line L6. The 2 nd driving line L6 is connected to ground via a resistor R3.

If the measurement instruction Sr of the H level is output from the output port 113 of the CPU 110, the 1 st switch 141 is turned on.

If the 1 st switch 141 is turned on, the 1 st driving line L5 is turned on with the ground. If the 1 st driving line L5 is turned on to the ground, the gates of the 3 rd FET 133C and the 4 th FET 133D become low, and thus the 3 rd FET 133C and the 4 th FET 133D are switched from off to on.

The 3 rd input port 111C of the CPU 110 receives a voltage obtained by dividing the voltage of the positive electrode of the 3 rd secondary battery 62C (the voltage of P3) by the 3 rd voltage dividing circuit 131C by switching the 3 rd FET 133C to on.

The 4 th FET 133D is switched on, and a voltage obtained by dividing the voltage of the positive electrode of the 4 th secondary battery 62D (the voltage of P4) by the 4 th voltage dividing circuit 131D is input to the 4 th input port 111D of the CPU 110.

If the 1 st switch 141 is turned on, the 2 nd switch 143 is turned on, and the 2 nd driving line L6 is turned on with the positive electrode of the 4 th secondary battery 62D. If the 2 nd drive line L6 is turned on with the positive electrode of the 4 th secondary battery 62D, the gates of the 1 st FET 133A and the 2 nd FET 133B become high, and the 1 st FET 133A and the 2 nd FET 133B are switched from off to on.

The voltage obtained by dividing the voltage of the positive electrode of the 1 st-stage secondary battery 62A (the voltage of P1) by the 1 st voltage dividing circuit 131A by switching the 1 st FET 133A on is input to the 1 st input port 111A of the CPU 110.

The 2 nd input port 111B of the CPU 110 receives a voltage obtained by dividing the voltage of the positive electrode of the 2 nd secondary battery 62B (the voltage of P2) by the 2 nd voltage dividing circuit 131B by switching the 2 nd FET 133B to on.

In this way, if the measurement command Sr is output, voltages obtained by dividing the voltages of the positive electrodes of the 1 st to 4 th secondary batteries 62A, 62B, 62C, and 62D are input to the 4 input ports 111A, 111B, 111C, and 111D of the CPU 110 by the 1 st voltage dividing circuit 131A, the 2 nd voltage dividing circuit 131B, the 3 rd voltage dividing circuit 131C, and the 4 th voltage dividing circuit 131D, respectively.

Therefore, the CPU 110 can obtain the cell voltage Vs of each of the secondary battery 62A, the secondary battery 62B, the secondary battery 62C, and the secondary battery 62D from the input voltages of the 1 st input port 111A, the 2 nd input port 111B, the 3 rd input port 111C, and the 4 th input port 111D.

That is, the cell voltage Vs of the 2 nd-order secondary battery 62B can be obtained by subtracting the voltage of the positive electrode of the 1 st-order secondary battery 62A from the voltage of the positive electrode of the 2 nd-order secondary battery 62B. Similarly, the cell voltage Vs of the 3 rd-order secondary battery 62C can be obtained by subtracting the voltage of the positive electrode of the 2 nd-order secondary battery 62B from the voltage of the positive electrode of the 3 rd-order secondary battery 62C. The cell voltage Vs of the 4 th-stage secondary battery 62D can be obtained by subtracting the voltage of the positive electrode of the 3 rd-stage secondary battery 62C from the voltage of the positive electrode of the 4 th-stage secondary battery 62D.

4. Description of the effects

When the maximum voltage of the positive electrode of the secondary battery 62 is higher than the allowable voltage (V is 5V) of the CPU 110 and the minimum voltage of the positive electrode is lower than the threshold voltage (Vth is 2.5V) of the FET 133, the problem of the overvoltage and the problem of the malfunction of the FET cannot be solved regardless of whether the FET 133 is disposed on the low potential side or the high potential side of the voltage dividing circuit 131.

For example, when the usage range (cell voltage Vs) of the secondary batteries 62A to 62D is 1.2V to 3.8V, the lowest voltage of the positive electrode of the 2 nd-stage secondary battery 62B is 2.4V, the highest voltage of the positive electrode is 7.6V, the highest voltage of the positive electrode is higher than the allowable voltage (5V) of the CPU 110, and the lowest voltage of the positive electrode is lower than the threshold voltage (Vth of 2.5V) of the FET 133.

The analog processing circuit 130 uses an N-channel FET in the 2 nd FET 133B corresponding to the 2 nd-stage secondary battery 62B. The 2 nd FET 133B is located between the 1 st resistor R1B and the 2 nd resistor R2B, with the source being the voltage output terminal with respect to the CPU 110.

Since the 2 nd FET 133B is an N-channel and operates on the ground reference, it can be switched without depending on the voltage of the positive electrode of the 2 nd-stage secondary battery 62B. Therefore, the malfunction of the 2 nd FET 133B can be suppressed.

When the 2 nd FET 133B is turned off, the 2 nd input port 111B of the CPU 110 is turned on to the ground via the 1 st resistor R1B, and the positive electrode of the 2 nd-stage secondary battery 62B is turned off. Therefore, in the non-measurement time, an overvoltage exceeding the allowable voltage is not input to the 2 nd input port 111B of the CPU 110.

As is apparent from the above description, with respect to the 2 nd-stage secondary battery 62B, both the problem of the overvoltage with respect to the CPU 110 and the problem of the malfunction of the 2 nd FET 133B can be solved.

The 3 rd stage 3 rd FET 133C is a P-channel FET located on the high potential side of the 3 rd voltage dividing circuit 131C, and the 4 th stage 4 th FET 133D is a P-channel FET located on the high potential side of the 4 th voltage dividing circuit 131D.

If the 3 rd FET 133C is turned off, the 3 rd input port 111C of the CPU 110 is made non-conductive with respect to the positive electrode of the 3 rd-stage secondary battery 62C, and if the 4 th FET 133D is turned off, the 4 th input port 111D of the CPU 110 is made non-conductive with respect to the positive electrode of the 4 th-stage secondary battery 62D. Therefore, during non-measurement, the 3 rd input port 111C for measuring the voltage of the 3 rd-order secondary battery 62C and the 4 th input port 111D for measuring the voltage of the 4 th-order secondary battery 62C can be suppressed from becoming overvoltage.

The 1 st stage 1 st FET 133A is an N-channel FET located on the high potential side of the 1 st voltage dividing circuit 131A. The source of the 1 st FET 133A is connected to ground via the 1 st voltage dividing circuit 131A. Since the 1 st FET 133A operates with the ground reference, switching can be performed without depending on the voltage of the positive electrode of the 1 st-stage secondary battery 62 a. Therefore, the 1 st FET 133A can be suppressed from operating improperly.

< other embodiment >

The present invention is not limited to the embodiments described above and illustrated in the drawings, and for example, the following embodiments are also included in the technical scope of the present invention.

(1) In embodiment 1, the secondary battery 62 is illustrated as an example of the electric storage element. The electric storage element is not limited to the secondary battery 62, and may be a capacitor. The secondary battery 62 is not limited to a lithium-ion secondary battery, and may be another nonaqueous electrolyte secondary battery. Lead storage batteries and the like can also be used.

(2) In embodiment 1 described above, the battery 50 is mounted on the automobile 10. Or may be mounted on a motorcycle. The battery 50 may be used for purposes other than engine starting. The battery 50 can be used for various purposes such as for a mobile object (for a vehicle, a ship, an AGV, etc.), for an industrial purpose (for an uninterruptible power supply system, a power storage device of a solar power generation system), and the like.

(3) In embodiment 1, the CPU 110 is provided with 4 input ports 111A, 111B, 111C, and 111D for voltage measurement. There may be one input port 111. In this case, the connection terminal of the input port 111 may be switched between the voltage dividing circuits 131A to 131D of each stage using a multiplexer or the like.

(4) In embodiment 1, the 2 nd-stage 2 nd FET 133B among the 4 FETs 133A, FET 133B, FET 133C and 133D of the 1 st to 4 th stages is an N-channel, and is disposed between the 1 st resistor R1B and the 2 nd resistor R2B of the 2 nd voltage dividing circuit 131B. Not limited to the 2 nd stage, N-channel FETs of a given number of stages may be arranged between the 1 st resistor R1 and the 2 nd resistor R2 of the voltage divider circuit 131. For example, the problem of overvoltage is likely to occur in a measurement line for measuring a higher-order secondary battery, and the problem of malfunction of the FET is likely to occur in a measurement line for measuring a lower-order secondary battery. That is, in a measurement line for measuring an intermediate secondary battery, a problem of overvoltage and a problem of operation failure of the FET are likely to occur. Therefore, the FET in the intermediate stage, such as the 2 nd stage and the 3 rd stage, may be disposed between the 1 st resistor R1 and the 2 nd resistor R2 of the voltage divider circuit 131 as an N-channel regardless of the relationship between the voltage of the positive electrode of the secondary battery and the allowable voltage of the CPU or the relationship between the voltage and the threshold voltage of the FET. In addition, in the 1 st stage, the 4 th stage, or the like, corresponding to only either a case where the maximum voltage of the positive electrode is higher than the allowable voltage of the CPU 110 or a case where the minimum voltage of the positive electrode is lower than the threshold voltage of the FET 133, the FET 133 may be disposed between the 1 st resistor R1 and the 2 nd resistor R2 of the voltage divider circuit 131 as an N-channel.

(5) In embodiment 1 described above, a voltage measuring circuit for the battery pack 60 is shown. The voltage measuring circuit may be a voltage measuring circuit for a single cell. That is, in the case of a single cell, the same problem occurs even when the maximum voltage of the positive electrode is higher than the allowable voltage of the measurement unit and the minimum voltage of the positive electrode is lower than the threshold voltage Vth of the FET.

Description of the symbols

10 automobiles;

50 batteries (electric storage devices);

62 secondary batteries (power storage elements);

100 a management unit;

110 CPU (measurement unit);

130 analog processing circuit

The 1 st to 4 th voltage division circuits of 131A to 131D;

133A to 133D 1 st FET to 4 th FET;

141, switch 1;

143 a 2 nd switch;

l5 drive line 1;

l6 drive line 2.