阅读说明：本技术 图像传感器 (Image sensor with a plurality of pixels ) 是由 金殷俊 于 2021-06-08 设计创作，主要内容包括：本公开涉及一种图像传感器,该图像传感器包括：像素阵列,该像素阵列包括布置有多个列和多个行的多个像素；读出电路,该读出电路使用从与从多个行当中选择的行相对应的像素输出的像素信号来生成图像数据；以及多条增益调整线,分别针对多个列提供多条增益调整线,并且调整它们各自对应列的像素的增益。(The present disclosure relates to an image sensor, including: a pixel array including a plurality of pixels arranged with a plurality of columns and a plurality of rows; a readout circuit that generates image data using pixel signals output from pixels corresponding to a row selected from among the plurality of rows; and a plurality of gain adjustment lines that are provided for the plurality of columns, respectively, and that adjust the gains of the pixels of their respective corresponding columns.)

1. An image sensor, comprising:

a pixel array including a plurality of pixels arranged in a plurality of columns and a plurality of rows;

a readout circuit that generates image data using pixel signals output from pixels corresponding to a row selected from among the plurality of rows; and

and a plurality of gain adjustment lines provided for the plurality of columns, respectively, each gain adjustment line adjusting the gain of the pixels of the corresponding column.

2. The image sensor of claim 1, further comprising:

a plurality of reset signal lines provided for the plurality of rows, respectively, each reset signal line controlling a reset operation of the pixels of the corresponding row;

a plurality of transmission signal lines provided for the plurality of rows, respectively, each transmission signal line controlling a transmission operation of pixels of a corresponding row;

a plurality of selection signal lines provided for the plurality of rows, respectively, each of the selection signal lines controlling an output operation of the pixels of the corresponding row; and

a plurality of pixel output lines provided for the plurality of columns, respectively, each pixel output line transmitting a pixel signal of a pixel of a corresponding column to the readout circuit.

3. The image sensor of claim 2, further comprising a control circuit for generating signals transmitted to the plurality of gain adjustment lines, the plurality of reset signal lines, the plurality of transmission signal lines, and the plurality of selection signal lines.

4. The image sensor as set forth in claim 1,

wherein each of the plurality of pixels includes:

a photodetector;

a floating diffusion node;

a reset transistor for resetting the floating diffusion node in response to a corresponding reset signal line among a plurality of reset signal lines;

a transfer transistor for transferring charge from the photodetector to the floating diffusion node in response to a corresponding transfer signal line among a plurality of transfer signal lines;

a driving transistor for amplifying a voltage of the floating diffusion node;

a selection transistor for transmitting a voltage amplified by the driving transistor to a corresponding pixel output line among a plurality of pixel output lines in response to the corresponding selection signal line among the plurality of selection signal lines; and

a capacitor connected to the floating diffusion, wherein a capacitance of the capacitor is adjusted in response to a corresponding gain adjustment line among the plurality of gain adjustment lines.

5. The image sensor as set forth in claim 1,

wherein each of the plurality of pixels includes:

a floating diffusion node; and

a capacitor connected to the floating diffusion, wherein a capacitance of the capacitor is adjusted in response to a corresponding gain adjustment line among the plurality of gain adjustment lines.

6. The image sensor as set forth in claim 4,

wherein the capacitor comprises a metal oxide semiconductor transistor.

7. An image sensor, comprising:

a pixel array comprising a plurality of pixels;

a readout circuit that generates image data using a pixel signal output from a pixel selected from among the plurality of pixels; and

a plurality of gain adjustment lines separated from each other to adjust a gain of each selected pixel.

8. The image sensor as set forth in claim 7,

wherein each of the plurality of pixels includes:

a floating diffusion node; and

a capacitor connected to the floating diffusion, wherein a capacitance of the capacitor is adjusted in response to a corresponding gain adjustment line among the plurality of gain adjustment lines.

9. The image sensor as set forth in claim 7,

wherein each of the plurality of pixels includes:

a photodetector;

a floating diffusion node;

a reset transistor for resetting the floating diffusion node in response to a reset signal;

a transfer transistor for transferring charge from the photodetector to the floating diffusion node in response to a transfer signal;

a driving transistor for amplifying a voltage of the floating diffusion node;

a selection transistor for transmitting the voltage amplified by the driving transistor to the readout circuit in response to a selection signal; and

a capacitor connected to the floating diffusion, wherein a capacitance of the capacitor is adjusted in response to a corresponding gain adjustment line among the plurality of gain adjustment lines.

10. The image sensor as set forth in claim 9,

wherein the capacitor comprises a metal oxide semiconductor transistor.

11. An image sensor, comprising:

a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel comprising at least one transistor and a capacitor coupled to a floating diffusion node;

a plurality of signal lines, each signal line coupled to a pixel in a corresponding row and providing one or more signals to transistors of the pixels in the corresponding row;

a plurality of gain adjustment lines, each gain adjustment line coupled to a pixel in a corresponding column and controlling a capacitor of the pixel in the corresponding column; and

a readout circuit that receives pixel signals from pixels in a selected row among the plurality of rows and converts the pixel signals to generate image data.

Technical Field

The present disclosure relates to an image sensor.

Background

Unlike a solid-state image sensing device, a Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) needs to convert analog signals (i.e., pixel signals) output from a pixel array into digital signals. For such analog-to-digital signal conversion, the CMOS image sensor includes a high resolution analog-to-digital converter (ADC).

Depending on the implementation of the ADC, there are two types of CIS: one uses a single ADC and the other uses a column ADC.

The single ADC type CIS converts analog signals output from pixels of all columns into digital signals within a set time. This type of CIS may advantageously reduce the chip area for the CIS, but may consume a large amount of power due to the need for the ADC to operate at high speed.

The column ADC type has a simplified ADC (e.g., a single slope ADC) placed at each column, and thus has a disadvantage of increasing a chip area of the CIS. However, since each ADC can operate at a low speed, power consumption can be reduced.

Currently, most CIS employ a column analog-to-digital conversion scheme that operates to achieve the best tradeoff between speed and power. If a column analog-to-digital conversion scheme is used, several columns of the selected row are read out simultaneously, and therefore, pixel signals from adjacent columns may affect each other, causing stripe noise.

Disclosure of Invention

Embodiments of the present disclosure provide techniques for reducing banding noise in an image sensor.

According to an embodiment, an image sensor includes: a pixel array including a plurality of pixels arranged in a plurality of columns and a plurality of rows; a readout circuit that generates image data using pixel signals output from pixels corresponding to a row selected from among the plurality of rows; and a plurality of gain adjustment lines, which are respectively provided for the plurality of columns, and each of which adjusts the gain of the pixels of the corresponding column.

According to an embodiment, an image sensor includes: a pixel array including a plurality of pixels; a readout circuit that generates image data using a pixel signal output from a pixel selected from among the plurality of pixels; and a plurality of gain adjustment lines separated from each other to adjust a gain of each selected pixel.

According to an embodiment, a pixel array includes: a plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel comprising at least one transistor and a capacitor coupled to a floating diffusion node; a plurality of signal lines, each signal line coupled to a pixel in a corresponding row and configured to provide one or more signals to transistors of the pixels in the corresponding row; a plurality of gain adjustment lines, each gain adjustment line coupled to a pixel in a corresponding column and configured to control a capacitor of a pixel in the corresponding column; and a readout circuit configured to receive pixel signals from pixels in a row selected from among the plurality of rows and convert the pixel signals to generate image data.

According to various embodiments of the present disclosure, band noise in an image sensor may be reduced.

Drawings

Fig. 1 is a diagram illustrating a pixel array according to one embodiment of the present disclosure;

fig. 2 is a diagram illustrating a phenomenon in which band noise occurs in a pixel array such as that of fig. 1;

fig. 3 is a diagram illustrating a pixel array according to one embodiment of the present disclosure; and

fig. 4 is a diagram illustrating a configuration of an image sensor including a pixel array such as that of fig. 3.

Detailed Description

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings to enable those skilled in the art to practice the invention. For the sake of clarity, well-known materials that are not directly related to the subject matter of the present disclosure may be omitted. Like reference numerals are used to identify like elements throughout the specification and drawings. Moreover, references to "one embodiment" or the like throughout this specification are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment. The term "embodiments" as used herein does not necessarily refer to all embodiments.

Fig. 1 is a diagram illustrating a pixel array 100 according to one embodiment of the present disclosure.

Referring to fig. 1, the pixel array 100 may include a plurality of pixels P _00 to P _ NM arranged in a plurality of rows and a plurality of columns. In order to control the operation of the plurality of pixels P _00 to P _ NM and output pixel signals, the lines RX _0 to RX _ N, TX _0 to TX _ N, SX _0 to SX _ N and DCG _0 to DCG _ N are arranged in a row direction, and the lines OUT _0 to OUT _ M are arranged in a column direction.

The reset signal lines RX _0 to RX _ N may be separately formed for each row, and may control reset operations of the pixels of their respective corresponding rows. For example, the reset signal line RX _1 may control a reset operation of the pixels P _10 to P _1M in the first row.

The transmission signal lines TX _0 to TX _ N may be formed separately for each row, and may control transmission operations of the pixels of their respective corresponding rows. For example, the transmission signal line TX _0 may control a transmission operation of the pixels P _00 to P _0M in the 0 th row.

The selection signal lines SX _0 to SX _ N may be individually formed for each row, and may control output operations of the pixels of their respective corresponding rows. For example, the selection signal line SX _2 may control an output operation of the pixels P _20 to P _2M in the second row.

The gain adjustment lines DCG _0 to DCG _ N may be separately formed for each row, and may control the gains of the pixels of their respective corresponding rows. For example, the gain adjustment line DCG _ N may adjust the gains of the pixels P _ N0 to P _ NM in the nth row.

The pixel output lines OUT _0 to OUT _ M may be formed separately for each column, and are used to output pixel signals of pixels of their respective corresponding columns. For example, a pixel signal of a pixel selected from among the pixels P _30 to P _3N in the third column may be output through the pixel output line OUT _ 3.

Each of the pixels P _00 to P _ NM may include photodetectors PD _00 to PD _ NM, floating diffusion nodes FD _00 to FD _ NM, reset transistors 101_00 to 101_ NM, transfer transistors 103_00 to 103_ NM, driving transistors 105_00 to 105_ NM, selection transistors 107_00 to 107_ NM, and capacitors C _00 to C _ NM.

The photodetectors PD _00 to PD _ NM may perform a photoelectric conversion function. The photodetectors PD _00 to PD _ NM may be connected between the ground voltage terminal vsspx and the transfer transistors 103_00 to 103_ NM. The photodetectors PD _00 to PD _ NM may receive light from the outside and generate optical charges based on the received light. The photodetectors PD _00 to PD _ NM may be implemented using at least any one of a photodiode, a phototransistor, a photogate, a pinned photodiode, and a combination thereof.

The reset transistors 101_00 to 101_ NM may transmit the source voltages vddpx to the floating diffusions FD _00 to FD _ NM in response to the reset signals transmitted to their corresponding reset signal lines among the reset signal lines RX _0 to RX _ N. In other words, the reset transistors 101_00 to 101_ NM may reset the photocharges stored in the floating diffusion nodes FD _00 to FD _ NM in response to the voltages of their corresponding reset signal lines.

The transfer transistors 103_00 to 103_ NM may transfer the photo-charges of the photo-detectors PD _00 to PD _ NM to the floating diffusions FD _00 to FD _ NM in response to a transfer signal transferred to their corresponding transfer signal line among the transfer signal lines TX _0 to TX _ N. The floating diffusion nodes FD _00 to FD _ NM are diffusion regions connected to the transfer transistors 103_00 to 103_ NM and the reset transistors 101_00 to 101_ NM, and are nodes that accumulate charges corresponding to image signals or charges corresponding to initialization voltages.

The driving transistors 105_00 to 105_ NM may have gates connected to the floating diffusion nodes FD _00 to FD _ NM and drains and sources connected between the source voltage terminal vddpx and the selection transistors 107_00 to 107_ NM. The driving transistors 105_00 to 105_ NM may amplify the voltages of the floating diffusion nodes FD _00 to FD _ NM.

The selection transistors 107_00 to 107_ NM may transmit voltages (i.e., pixel signals) amplified by the driving transistors 105_00 to 105_ NM to their corresponding pixel output lines OUT _0 to OUT _ M in response to selection signals transmitted to their corresponding selection signal lines among the selection signal lines SX _0 to SX _ N.

The capacitors C _00 to C _ NM may be connected to the floating diffusions FD _00 to FD _ NM, and their capacitances may be adjusted in response to voltages of their corresponding gain adjustment lines among the gain adjustment lines DCG _0 to DCG _ N. The capacitors C _00 to C _ NM may be configured as Metal Oxide Semiconductor (MOS) transistors, and their capacitances may increase as the voltage of their corresponding gain adjustment lines increases. Since the capacitances of the floating diffusions FD _00 to FD _ NM are adjusted according to the capacitances of the capacitors C _00 to C _ NM, the pixel conversion gain can be adjusted. This gain adjustment function is referred to as a Dual Conversion Gain (DCG) function.

A readout operation of generating image data by analog-to-digital converting pixel signals from the pixel array 100 may be performed for each row. For example, the readout operations of the pixels P _00 to P _0M in the zeroth row may be performed simultaneously, and the readout operations of the pixels P _10 to P _1M in the first row may be performed simultaneously.

Fig. 2 is a diagram illustrating a phenomenon in which band noise occurs in the pixel array 100 of fig. 1. It is assumed that the readout operation of the pixels P _70 to P _7M at the seventh row is being performed. For example, only three pixels P _74, P _75, and P _76 of the 7 th row are illustrated in fig. 2. Assume that pixel P _76 detects bright light and pixels P _74 and P _75 detect dark light.

When the charges of the photodetectors PD _74, PD _75, and PD _76 are transferred to the floating diffusions FD _74, FD _75, and FD _76, the floating diffusion FD _76 of the pixel P _76 that detects bright light may experience more voltage level changes than the floating diffusions FD _74 and FD _75 of the other pixels P _74 and P _ 75. A significant change in the voltage level of the floating diffusion FD _76 may affect the floating diffusions FD _74 and FD _75 via the capacitor C _76, the gain adjustment line DCG _7, and the capacitors C _74 and C _75, thereby changing the voltage levels of the floating diffusions FD _74 and FD _ 75. In other words, the signal of the pixel P _76 detecting bright light may affect the signals of the pixels P _74 and P _75 detecting dark light. As a result, band noise may occur, resulting in generation of an image as if brighter light has been detected than the actual light detected by the pixels P _74 and P _ 75.

Fig. 3 is a diagram illustrating a pixel array 300 according to one embodiment of the present disclosure.

Referring to fig. 3, the pixel array 300 may include a plurality of pixels P _00 to P _ NM arranged in a plurality of rows and a plurality of columns. In order to control the operation of the plurality of pixels P _00 to P _ NM and output pixel signals, the lines RX _0 to RX _ N, TX _0 to TX _ N and SX _0 to SX _ N are arranged in the row direction, and the lines DCG _0 to DCG _ M and OUT _0 to OUT _ M are arranged in the column direction.

Unlike the pixel array 100 of fig. 1, in the pixel array 300, the gain adjustment lines DCG _0 to DCG _ M may be arranged in the column direction. The gain adjustment lines DCG _0 to DCG _ M may be provided for each column, and the gains of the pixels of their respective corresponding columns are adjusted. For example, the gain adjustment line DCG _9 may adjust the gains of the pixels P _09 to P _ N9 in the ninth column.

When the gain adjustment lines DCG _0 to DCG _ M are independently provided for each column, this means that the gain adjustment lines corresponding to the pixels read out simultaneously are independent of each other. For example, when the pixels P _30 to P _3M in the third row are simultaneously read out, the pixels P _30 to P _3M may all be connected to DCG _0 to DCG _ M separated from each other. Since the gain adjustment lines corresponding to the pixels read out simultaneously are independent of each other, it is possible to prevent band noise that would otherwise occur as the floating diffusions FD _74, FD _75, and FD _76 affect each other via the gain adjustment line DCG _7 as shown in fig. 2.

In the case where the gain adjustment lines DCG _0 to DCG _ M are formed in the column direction, pixels of the same column may share the same gain adjustment line. Since the pixels of the same column are read out at different times rather than simultaneously, the stripe noise can be avoided in this case via the gain adjustment lines DCG _0 to DCG _ M.

Fig. 4 is a diagram illustrating a configuration of an image sensor including the pixel array 300 of fig. 3.

Referring to fig. 4, the image sensor may include a pixel array 300, lines RX _0 to RX _ N, TX _0 to TX _ N, SX _0 to SX _ N in a row direction, lines DCG _0 to DCG _ M, OUT _0 to OUT _ M in a column direction, a control circuit 410, and a readout circuit 420.

The pixel array 300 may include a plurality of pixels P _00 to P _ NM arranged in a plurality of rows and a plurality of columns.

The reset signal lines RX _0 to RX _ N arranged along the row direction may control the reset operation of the pixels of their respective corresponding rows. The transmission signal lines TX _0 to TX _ N may control transmission operations of the pixels of their respective corresponding rows. The selection signal lines SX _0 to SX _ N may control output operations of the pixels of their respective corresponding rows.

The gain adjustment lines DCG _0 to DCG _ M arranged in the column direction may control the gains of the pixels of their respective corresponding columns. The pixel output lines OUT _0 to OUT _ M may be used to output pixel signals of pixels of their respective corresponding columns. Since the gain adjustment lines DCG _0 to DCG _ M can be provided independently for each column, the band noise can be suppressed.

The control circuit 410 may generate signals transmitted to the lines RX _0 to RX _ N, TX _0 to TX _ N, SX _0 to SX _ N, DCG _0 to DCG _ M for controlling the pixels P _00 to P _ NM. Specifically, the control circuit 410 may independently control the voltages of the gain adjustment lines DCG _0 to DCG _ M provided for each column. In other words, at the time of the readout operation, the gains of the pixels of different columns may be different from each other. All columns may be controlled to have the same gain.

The readout circuit 420 may generate image DATA IMG _ DATA using pixel signals output from pixels corresponding to a row selected from among a plurality of rows of the pixel array via the pixel output lines OUT _0 to OUT _ M. The readout circuit 420 may include a circuit for generating image DATA IMG _ DATA by analog-to-digital conversion of pixel signals.

It should be noted that while embodiments of the invention have been illustrated and described, this is for purposes of example only and is not intended to limit the scope of the invention. In view of the present disclosure, those skilled in the art will appreciate that various changes can be made to any of the disclosed embodiments without departing from the technical spirit of the present disclosure. The invention includes all such variations as fall within the scope of the claims.

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2020-0077677, filed on 25.6.2020, which is incorporated herein by reference in its entirety.