阅读说明：本技术 一种离子栅双模树突器件及其在神经网络加速器中的应用 (Ion grid dual-mode dendritic device and application thereof in neural network accelerator ) 是由 杨玉超 荆兆坤 黄如 于 2021-09-07 设计创作，主要内容包括：本发明公开了一种离子栅双模树突器件及其在神经网络加速器中的应用,首次提出利用离子栅介质的有机离子漂移过程受控于栅电压幅值与脉宽的特性制备双模树突器件,通过对离子栅器件的栅极输入不同模式的电压信号,使器件具备类似于生物树突的超线性或亚线性两种不同响应模式,从而令人工树突器件具备多模式的非线性信号整合能力。同一个器件对电压脉冲输入具有超线性和亚线性两种整合模式,使得单一器件能够完成复杂的仿生功能,简化了电路设计复杂度；树突的非线性信号整合功能增强了单层神经网络的信号处理能力,使多层神经网络运算简化为单层神经网络运算,降低了神经网络加速器对面积、延时、功耗的需求；器件结构简单,易于集成。(The invention discloses an ion gate dual-mode dendritic device and application thereof in a neural network accelerator, and firstly proposes that the dual-mode dendritic device is prepared by controlling the organic ion drift process of an ion gate medium by the characteristics of gate voltage amplitude and pulse width, and the device has two different response modes of super linearity and sub-linearity similar to biological dendritic by inputting voltage signals of different modes to the gate of the ion gate device, so that the artificial dendritic device has the nonlinear signal integration capability of multiple modes. The same device has two integration modes of super-linearity and sub-linearity for voltage pulse input, so that a single device can complete a complex bionic function, and the complexity of circuit design is simplified; the signal processing capability of the single-layer neural network is enhanced by the dendritic nonlinear signal integration function, so that the multilayer neural network operation is simplified into the single-layer neural network operation, and the requirements of a neural network accelerator on area, time delay and power consumption are reduced; the device has simple structure and is easy to integrate.)

1. An ion gate dual-mode dendritic device comprises a substrate, a channel layer, a gate electrode, a source electrode, a drain electrode and a gate medium layer, wherein the channel layer and the source electrode are sequentially stacked on the substrate; the gate electrode is positioned on the side edge of the channel layer and is not in direct contact with the channel layer; the gate dielectric layer covers the gate electrode, the source and drain electrodes and the channel layer between the source and drain electrodes; the gate dielectric layer is an ionic glue material prepared by mixing ionic liquid and organic polymer.

2. The ion-gate dual-mode dendritic device of claim 1, wherein the channel layer is an n-type inorganic semiconductor material and has a thickness of 6 to 100 nm.

3. The dual-mode ion-gate dendritic device of claim 1, wherein the gate dielectric layer is an ionic glue material prepared by mixing 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) imide with poly (4-vinylphenol).

4. The ion-gated bimodal dendritic device of claim 1, wherein said ionic liquid is a room temperature ionic liquid and both anions and cations thereof are organic ions; the organic polymer is one or more selected from PVP, PEO, PSSH, P (VPA-AA), P (VDF-TrFE) and PAH-PSS.

5. The ion-gated dual-mode dendritic device of claim 1, wherein the gate dielectric layer has a thickness of 10nm to 2 μm.

6. The ion-gated dual-mode dendritic device of claim 1, wherein said substrate is a silicon substrate or a flexible substrate; the source electrode, the drain electrode and the gate electrode are made of metal materials, metal nitride materials, flexible conductive materials and two-dimensional atomic crystal materials, and the thickness of the electrode is 0.3-300 nm.

7. A method for preparing an ion-grid dual-mode dendritic device as claimed in any one of claims 1 to 6, comprising the steps of:

1) photoetching and defining a pattern of a channel layer on a substrate, and then preparing the channel layer;

2) photoetching and defining a pattern of a source electrode and a drain electrode above the channel layer, photoetching and defining a pattern of a gate electrode on the side surface of the channel layer, and then preparing the source electrode, the drain electrode and the gate electrode;

3) preparing an ion glue material, and then coating the ion glue material on the channel layer and the gate electrode to be used as a gate dielectric layer;

4) and heating and drying the device to volatilize the solvent in the gate dielectric layer and solidify the gate dielectric layer.

8. The manufacturing method according to claim 7, wherein in step 1), the pattern of the channel layer is defined by using an ultraviolet lithography or an electron beam lithography, and then the channel layer is manufactured by using a magnetron sputtering or reactive sputtering method; in the step 2), patterns of a source electrode, a drain electrode and a gate electrode are defined by adopting an ultraviolet lithography or electron beam lithography method, and then electrodes are prepared by adopting an electron beam evaporation or magnetron sputtering method; coating the ionic glue material by adopting a dripping or spin coating method in the step 3); and 4) heating the drying device by adopting a vacuum drying or hot plate heating method in the step 4).

9. The method for regulating and controlling the working mode of the ion gate dual-mode dendritic device as claimed in any one of claims 1 to 6, comprising the following steps:

1) inputting pulse signals with different pulse widths and fixed periods and quantity into a gate electrode of the ion gate dual-mode dendritic device, inputting direct-current reading voltage into a drain electrode, grounding a source electrode, and reading the source and drain currents of the device, wherein the maximum value of the source and drain currents of the device is rapidly increased along with the increase of the pulse widths; the ion grid dual-mode dendritic device in the state is adopted to simulate a super-linear integration mode of biological dendritic on an input signal;

2) inputting different numbers of pulse signals with fixed pulse width and period into a gate electrode of the ion gate dual-mode dendritic device, inputting direct current reading voltage into a drain electrode, grounding a source electrode, and reading the source and drain current of the device, wherein the maximum value of the source and drain current of the device presents a saturation trend along with the increase of the number of pulses; the ion grid dual-mode dendritic device in the state is adopted to simulate a sub-linear integration mode of biological dendritic on an input signal;

3) converting the multiplication and addition operation output of a neural network accelerator into a pulse width modulation signal, connecting the pulse width modulation signal to a gate electrode of the ion gate dual-mode dendritic device, inputting direct current reading voltage to a drain electrode, grounding a source electrode, and reading the source-drain current of the device, so that the ion gate dual-mode dendritic device works in a super-linear integration mode; in the mode, the ion grid dual-mode dendritic device carries out super-linear integration processing on the multiplication and addition operation result of the neural network, and outputs source and drain currents to a nonlinear neuron to carry out activation function operation;

4) converting the multiplication and addition operation output of a neural network accelerator into a pulse number signal, connecting the pulse number signal to a gate electrode of the ion gate dual-mode dendritic device, inputting direct-current reading voltage to a drain electrode, grounding a source electrode, and reading the source-drain current of the device, so that the ion gate dual-mode dendritic device works in a sub-linear integration mode; in the mode, the ion grid dual-mode dendritic device carries out sub-linear integration processing on the multiplication and addition operation result of the neural network, and outputs source and drain currents to the nonlinear neuron to carry out activating function operation.

10. The application of the ion grid dual-mode dendritic device in the neural network accelerator as claimed in any one of claims 1 to 6, wherein the ion grid dual-mode dendritic device is introduced between a matrix vector multiplication and addition operation module and a nonlinear neuron operation module of the neural network accelerator, so that a single-layer neural network has the signal processing capacity equivalent to that of a multi-layer neural network.

Technical Field

The invention belongs to the technical field of brain-like computing, and particularly relates to an ion grid dual-mode dendritic device and an application method thereof in a neural network accelerator.

Background

At present, the mainstream processors adopt a von Neumann architecture, and the architecture separates a memory from an arithmetic unit, so that a large amount of data needs to be frequently transmitted through a bus, huge arithmetic delay and energy consumption are caused, and further improvement of arithmetic efficiency is limited. In order to break through the bottleneck of von neumann, new computing paradigms including brain-like computing, memory computing and the like are proposed. A large number of neurons in the human brain store and process information in parallel, and the human brain has strong information processing capacity and extremely low power consumption. The core idea of brain-like computing is to construct an efficient computing system by simulating the structure of the human brain, and the core of the brain-like computing is to simulate synapses and neurons of the human brain.

The study of neural network accelerators has made a number of important advances in recent years. Memory computing systems based on resistive random access memories, phase change memories, static random access memories and the like are proposed, and high-energy-efficiency neural network computing is achieved. It is worth noting that most neural network accelerators adopt a point neuron model which is extremely simplified, neural network calculation is divided into two parts, namely linear multiplication and addition operation and nonlinear activation function operation, and nonlinear operation still needs to transmit data to an operation unit outside a memory for operation, so that operation efficiency of a multilayer neural network is difficult to improve. Biological neurons have complex dendritic structures, however, the design of neural network computing hardware by utilizing the structure and function of dendrites is rarely studied at present. Dendrites play an important role in signal processing of neurons, and are characterized in that the dendrites can perform different modes of nonlinear integration on a large number of synaptic inputs on different branches of the dendrites, so that a single neuron has strong signal processing capacity. This is necessary for many neural functions, such as simultaneous detection, direction selection, etc. Therefore, the dendritic structure is significant to be introduced into the design of the neural network accelerator, and the artificial dendritic device can provide a new idea for the design of the high-energy-efficiency neural network accelerator.

Disclosure of Invention

In order to solve the above defects or improvement requirements of the prior art, the invention firstly proposes a thought of realizing the dual-mode artificial dendrite by utilizing different response modes of the ion gate device to different input signals, and provides an ion gate dual-mode dendrite device and a realization method thereof. The ion grid dual-mode dendritic device is introduced between a matrix vector multiplication and addition operation module and a nonlinear neuron operation module of a neural network accelerator, so that the single-layer neural network has the signal processing capacity equivalent to that of a multi-layer neural network.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows: an ion gate dual-mode dendritic device comprises a substrate, a channel layer, a gate electrode, a source electrode, a drain electrode and a gate medium layer, wherein the channel layer and the source electrode are sequentially stacked on the substrate; the gate electrode is positioned on the side edge of the channel layer and is not in direct contact with the channel layer; the gate dielectric layer covers the gate electrode, the source and drain electrodes and the channel layer between the source and drain electrodes; the gate dielectric layer is an ionic glue material prepared by mixing ionic liquid and organic polymer.

In the above-mentioned ion-gate dual-mode dendrite device, the channel layer is preferably an n-type inorganic semiconductor material, such as ZnO, InO_x、SnS₂、MoS₂、Bi₂Se₃CdSe, etc. with a thickness of 6-100 nm.

The gate dielectric layer is preferably made of an ionic glue material prepared by mixing 1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) imide (EMIM-TFSI) and poly (4-vinylphenol) (PVP) in a certain proportion, or an ionic glue material prepared by mixing other ionic liquid and an organic polymer. The mixing ratio of the ionic liquid to the organic polymer is usually 1:1 to 1:50 by mass.

The ionic liquid is room temperature ionic liquid, namely an organic ionic compound consisting of anions and cations, the cations comprise 1-butyl-3-methylimidazolium (BMIM), 1-ethyl-3-methylimidazolium (EMIM), N, N-diethyl-N-methyl (2-methoxyethyl) ammonium (DEME), N, N, N-trimethyl-N-propylammonium (TMPA) and the like, and the anions comprise bis (pentafluoroethanesulfonyl) imide (BETI) and tetrafluoroborate (BF)₄) Hexafluorophosphate radical (PF)₆) Dicyanamide (DCA), bis (fluorosulfonyl) imide (FSI), bis (trifluoromethylsulfonyl) imide (TFSI), and the like.

The organic polymer is selected from one or more of PVP, polyethylene oxide (PEO), polystyrene sulfonic acid (PSSH), poly (vinyl phosphate-acrylic acid) (P (VPA-AA)), poly (vinylidene fluoride-trifluoroethylene) (P (VDF-TrFE)), and polyallylamine-polystyrene sulfonic acid (PAH-PSS).

The thickness of the gate dielectric layer is preferably 10 nm-2 μm.

The substrate is a silicon substrate or a flexible substrate; the source electrode, the drain electrode and the gate electrode are made of metal materials, metal nitride materials, flexible conductive materials and two-dimensional atomic crystal materials, and the thickness of the electrode is 0.3-300 nm.

Generally, the metal material for forming the source/drain electrode and the gate electrode is one or more selected from Ti, Cr, Sc, Pd, Au, Pt, Wu, and Al; the metal nitride material is TiN; the flexible conductive material is ITO; the two-dimensional atomic crystal material is graphene.

The invention also provides a preparation method of the ion gate dual-mode dendritic device, which comprises the following steps:

1) photoetching and defining a pattern of a channel layer on a substrate, and then preparing the channel layer;

2) photoetching and defining a pattern of a source electrode and a drain electrode above the channel layer, photoetching and defining a pattern of a gate electrode on the side surface of the channel layer, and then preparing the source electrode, the drain electrode and the gate electrode;

3) preparing an ion glue material, and then coating the ion glue material on the channel layer and the gate electrode to be used as a gate dielectric layer;

4) and heating and drying the device to volatilize the solvent in the gate dielectric layer and solidify the gate dielectric layer.

In the step 1), a channel layer pattern is defined by adopting an ultraviolet lithography or electron beam lithography method, and then a channel layer is prepared by adopting a magnetron sputtering or reactive sputtering method.

In the step 2), patterns of the source electrode, the drain electrode and the gate electrode are defined by adopting an ultraviolet lithography method or an electron beam lithography method, and then the electrode is prepared by adopting an electron beam evaporation method or a magnetron sputtering method.

In the step 3), the ionic glue material is coated by adopting a dropping coating or spin coating method.

In the step 4), the drying device is heated by adopting a vacuum drying or hot plate heating method.

The invention also provides a regulation and control method of the ion gate dual-mode dendritic device. The ion gate dual-mode dendritic device provided by the invention is used as a device capable of being input from three ends, has the electrical characteristics of an ion gate transistor device, and can increase the source-drain current of the device along with the increase of gate voltage and show a saturation trend along with the increase of source-drain voltage under the excitation of a gate voltage direct current signal; under the excitation of continuous pulse signals of gate voltage, source-drain current of the device presents a super-linear integrated response mode for pulse signals with different pulse widths, and presents a sub-linear integrated response mode for pulse signals with different quantities, so that the function of dual-mode dendrite is realized; the ion grid dual-mode dendritic device is introduced between the multiply-add operation and the neuron nonlinear activation operation of a neural network accelerator, so that the nonlinear signal integration function of the dendrites in biological neurons can be simulated, and the single-layer neural network has the signal processing capacity equivalent to that of a multi-layer neural network.

The invention provides a method for regulating and controlling the working mode of an ion grid dual-mode device, which comprises the following aspects:

(1) inputting pulse signals with different pulse widths and fixed periods and quantity into a gate electrode of the ion gate dual-mode dendritic device, inputting direct-current reading voltage into a drain electrode, grounding a source electrode, and reading the source and drain currents of the device, wherein the maximum value of the source and drain currents of the device is rapidly increased along with the increase of the pulse widths; the ion grid dual-mode dendritic device in the state is adopted to simulate a super-linear integration mode of biological dendritic on an input signal;

(2) inputting different numbers of pulse signals with fixed pulse width and period into a gate electrode of the ion gate dual-mode dendritic device, inputting direct current reading voltage into a drain electrode, grounding a source electrode, and reading the source and drain current of the device, wherein the maximum value of the source and drain current of the device presents a saturation trend along with the increase of the number of pulses; the ion grid dual-mode dendritic device in the state is adopted to simulate a sub-linear integration mode of biological dendritic on an input signal;

(3) converting the multiplication and addition operation output of a neural network accelerator into a pulse width modulation signal, connecting the pulse width modulation signal to a gate electrode of the ion gate dual-mode dendritic device, inputting direct current reading voltage to a drain electrode, grounding a source electrode, and reading the source-drain current of the device, so that the ion gate dual-mode dendritic device works in a super-linear integration mode; in the mode, the ion grid dual-mode dendritic device carries out super-linear integration processing on the multiplication and addition operation result of the neural network, and outputs source and drain currents to a nonlinear neuron to carry out activation function operation;

(4) converting the multiplication and addition operation output of a neural network accelerator into a pulse number signal, connecting the pulse number signal to a gate electrode of the ion gate dual-mode dendritic device, inputting direct-current reading voltage to a drain electrode, grounding a source electrode, and reading the source-drain current of the device, so that the ion gate dual-mode dendritic device works in a sub-linear integration mode; in the mode, the ion grid dual-mode dendritic device carries out sub-linear integration processing on the multiplication and addition operation result of the neural network, and outputs source and drain currents to the nonlinear neuron to carry out activating function operation.

The ion grid dual-mode dendritic device provided by the invention has the following advantages:

the invention firstly proposes that an ion gate device is adopted as an artificial dendritic device, and the nonlinear integration of an input pulse signal is realized by utilizing the regulation and control effect of gate voltage on the drift of organic ions in an ion gate medium, so that the invention has a vital significance for realizing a multi-mode artificial dendritic device; the same device has two integration modes of super-linearity and sub-linearity for voltage pulse input, so that a single device can complete a complex bionic function, and the complexity of circuit design is simplified; the signal processing capability of the single-layer neural network is enhanced by the dendritic nonlinear signal integration function, so that the multilayer neural network operation is simplified into the single-layer neural network operation, and the requirements of a neural network accelerator on area, time delay and power consumption are reduced; the device has simple structure and is easy to integrate.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of an ion-gated dual-mode dendritic device of the present invention, wherein: 1-substrate, 2-channel layer, 3-gate electrode, 4-source electrode, 5-drain electrode and 6-gate dielectric layer.

FIG. 2 is a schematic diagram of the excitation signal input for one embodiment of the ion-gated dual-mode dendritic device of the present invention.

FIG. 3 is a schematic diagram of a dual-mode dendritic super linear mode of operation of an embodiment of the ion-gated dual-mode dendritic device of the present invention.

FIG. 4 is a schematic diagram of a dual-mode dendritic sub-linear mode of operation of one embodiment of the ion-gated dual-mode dendritic device of the present invention.

FIG. 5 is a schematic diagram of an application of an embodiment of the ion-gated dual-mode dendritic device of the present invention in a neural network accelerator, wherein: 7-a multiplication and addition operation unit, 8-a pulse width modulation signal output unit, 9-a pulse number signal output unit, 10-an ion grid dual-mode dendritic device working in a sub-linear mode, 11-an ion grid dual-mode dendritic device working in a super-linear mode and 12-an artificial neuron.

Detailed Description

The invention will be further elucidated by means of specific embodiments in the following description, in conjunction with the appended drawings.

As shown in fig. 1, the ion-gate dual-mode dendritic device of the present embodiment includes: the structure comprises a substrate 1, a channel layer 2, a gate electrode 3, a source electrode 4, a drain electrode 5 and a gate medium layer 6, wherein the channel layer 2 is positioned on the substrate 1, and the source electrode 4 and the drain electrode 5 are positioned on the channel layer 2; the gate electrode 3 is positioned at the side of the channel layer 2 without directly contacting the channel layer 2; the gate dielectric layer 6 covers the gate electrode 3, the source electrode 4, the drain electrode 5 and the channel layer 2 between the source and the drain;

referring to fig. 1, the steps of manufacturing an ion-gate dual-mode dendritic device according to this embodiment are as follows:

1) by ultraviolet lithography or electron beam lithography on SiO₂Defining the pattern of the channel layer 2 on the substrate;

2) preparing a channel layer 2 by adopting methods such as reactive sputtering or magnetron sputtering and the like, and stripping by using acetone, wherein the channel layer 2 is made of ZnO and has the thickness of 50 nm;

3) defining the patterns of the gate electrode 3, the source electrode 4 and the drain electrode 5 by adopting methods such as ultraviolet lithography or electron beam lithography;

4) preparing Ti with the thickness of 5nm by adopting an electron beam evaporation method, then preparing Au with the thickness of 50nm, preparing a gate electrode 3, a source electrode 4 and a drain electrode 5, and stripping by using acetone;

5) mixing EMIM-TFSI and PVP according to the mass ratio of 1:10 to prepare an ionic glue material, and coating the ionic glue material on the surfaces of the channel layer 2, the gate electrode 3, the source electrode 4 and the drain electrode 5 by adopting a dropping coating or spin coating mode and the like to form a gate dielectric layer 6 with the thickness of 300 nm-1 mu m;

6) and heating the drying device by adopting methods such as vacuum drying or hot plate heating.

The schematic diagram of the input of the excitation signal when the ion-gate dual-mode dendritic device provided by the embodiment operates is shown in fig. 2, wherein the electrical input I is connected with the gate electrode 3 of the ion-gate dual-mode dendritic device, the electrical input II is connected with the drain electrode 4 of the ion-gate dual-mode dendritic device, and the electrical input III is connected with the source electrode 5 of the ion-gate dual-mode dendritic device.

Fig. 5 shows a schematic diagram of an application method of the ion-grid dual-mode dendritic device in the neural network accelerator, wherein an output of the neural network accelerator multiply-add operation unit 7 is connected to the pulse width modulation signal output unit 8 and the pulse number signal output unit 9; the pulse width modulation signal output unit 8 is connected with an ion grid dual-mode dendritic device 11 working in a super-linear mode, and the pulse number signal output unit 9 is connected with an ion grid dual-mode dendritic device 10 working in a sub-linear mode; the ion grid dual-mode dendritic device 10 working in the sub-linear mode and the ion grid dual-mode dendritic device 11 working in the super-linear mode are connected with an artificial neuron 12.

The following specifically describes the method for controlling an ion-gate dual-mode dendritic device provided by the present invention with reference to the present embodiment:

(1) inputting pulse signals with different pulse widths and fixed periods and quantity into a gate electrode 3 of the ion gate dual-mode dendritic device, inputting direct current reading voltage into a drain electrode 4, grounding a source electrode 5, and reading device source-drain current Ids from the drain electrode 4, wherein the maximum value of the device source-drain current Ids is rapidly increased along with the increase of the pulse width, as shown in FIG. 3; the ion grid dual-mode dendritic device in the state is adopted to simulate a super-linear integration mode of biological dendritic on an input signal;

(2) inputting different numbers of pulse signals with fixed pulse width and period into the gate electrode 3 of the ion-gate dual-mode dendritic device, inputting direct-current reading voltage into the drain electrode 4, grounding the source electrode 5, and reading the source-drain current Ids of the device from the drain electrode 4, wherein the maximum value of the source-drain current Ids of the device presents a saturation trend along with the increase of the number of pulses, as shown in fig. 4; the ion-grid dual-mode dendritic device in the state is adopted to simulate the sub-linear integration mode of biological dendritic on the input signal.

(3) Converting the output of a multiplication and addition operation unit 7 of the neural network accelerator into a pulse width modulation signal through a pulse width modulation signal output unit 8, connecting the pulse width modulation signal to the ion grid dual-mode dendritic device 11 working in the super-linear mode, and reading the source-drain current Ids of the device; in the mode, the ion grid dual-mode dendritic device carries out super-linear integration on the multiplication and addition operation result of the neural network, and outputs source-drain current Ids to the artificial neuron 12 for carrying out nonlinear activation function operation;

(4) converting the output of the multiplication and addition operation unit 7 of the neural network accelerator into a pulse number signal through a pulse number signal output unit 9, connecting the pulse number signal to the ion gate dual-mode dendritic device 10 working in the sub-linear mode, and reading the source-drain current Ids of the device; in the mode, the ion grid dual-mode dendritic device performs sub-linear integration on the multiplication and addition operation result of the neural network, and outputs the source-drain current Ids to the artificial neuron 12 for nonlinear activation function operation.

Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.