阅读说明：本技术 具有步进控制的多模式振荡电路系统 (Multi-mode oscillating circuit system with step control ) 是由 井口俊太 I·德里格兹 M·N·菲利亚斯 于 2020-05-21 设计创作，主要内容包括：公开了一种用于实现具有步进控制的多模式振荡电路系统的装置。在一个示例方面中,多模式振荡电路系统包括谐振器,该谐振器耦合到第一振荡器和第二振荡器。多模式振荡电路系统被配置为选择性地处于第一配置或第二配置,在第一配置中,第一振荡器处于活动状态而第二振荡器处于非活动状态,在第二配置中,第一振荡器处于非活动状态而第二振荡器处于活动状态。该装置还包括步进控制电路,该步进控制电路耦合到多模式振荡电路系统。步进控制电路被配置为使得第一振荡器从非活动状态切换到活动状态,并且基于第一振荡器处于活动状态来以增量地增加第一振荡器的第一增益,以使得多模式振荡电路系统能够从第二配置过渡到第一配置。(An apparatus for implementing multi-mode oscillating circuitry with step control is disclosed. In one example aspect, a multi-mode oscillation circuit system includes a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to be selectively in a first configuration in which the first oscillator is in an active state and the second oscillator is in an inactive state or a second configuration in which the first oscillator is in an inactive state and the second oscillator is in an active state. The apparatus also includes a step control circuit coupled to the multi-mode oscillation circuitry. The step control circuit is configured to cause the first oscillator to switch from an inactive state to an active state and to incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillating circuitry to transition from the second configuration to the first configuration.)

1. An apparatus, comprising:

multi-mode oscillating circuitry configured to be selectively in a first configuration or a second configuration, the multi-mode oscillating circuitry comprising:

a resonator;

a first oscillator coupled to the resonator, the first oscillator configured to be selectively in:

an active state based on the first configuration; and

an inactive state based on the second configuration; and

a second oscillator coupled to the resonator, the second oscillator configured to be selectively in:

the inactive state based on the first configuration; and

the active state based on the second configuration; and

a step control circuit coupled to the multi-mode oscillation circuitry, the step control circuit configured to:

causing the first oscillator to switch from the inactive state to the active state; and

incrementally increasing a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

2. The apparatus of claim 1, wherein:

the resonator is coupled between a first resonator node and a second resonator node;

the first oscillator comprises a first amplification circuit coupled to the first resonator node and the second resonator node; and

the second oscillator includes a second amplification circuit coupled to the first resonator node and the second resonator node.

3. The apparatus of claim 1, wherein:

the step control circuit is configured to incrementally increase the first gain of the first oscillator in two or more steps; and

the second oscillator is configured to be in the active state while the step control circuit incrementally increases the first gain of the first oscillator.

4. The apparatus of claim 1, wherein the step control circuit is configured to:

incrementally increasing the first gain of the first oscillator to a target gain; and

causing the second oscillator to switch from the active state to the inactive state in response to the first gain of the first oscillator being at the target gain.

5. The apparatus of claim 4, wherein:

the step control circuit is configured to incrementally decrease a second gain of the second oscillator prior to causing the second oscillator to switch from the active state to the inactive state.

6. The apparatus of claim 1, wherein:

the step control circuit is configured to:

causing the second oscillator to switch from the inactive state to the active state; and

incrementally increasing a second gain of the second oscillator based on the second oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the first configuration to the second configuration; and

the first oscillator is configured to be in the active state while the step control circuit incrementally increases the second gain of the second oscillator.

7. The apparatus of claim 6, wherein:

the first oscillator is configured to generate a first oscillating signal in response to being in the active state;

the step control circuit is configured to incrementally increase a first peak-to-peak voltage of the first oscillating signal to cause the multi-mode oscillating circuitry to transition from the second configuration to the first configuration;

the second oscillator is configured to generate a second oscillating signal in response to being in the active state; and

the step control circuit is configured to incrementally increase a second peak-to-peak voltage of the second oscillating signal to enable the multi-mode oscillating circuitry to transition from the first configuration to the second configuration.

8. The apparatus of claim 7, wherein the resonator is configured to selectively:

generating a clock signal based on the first oscillation signal;

generating the clock signal based on the second oscillation signal; or

Generating the clock signal based on both the first oscillation signal and the second oscillation signal.

9. The apparatus of claim 6, wherein:

the first oscillator comprises a voltage mode oscillator; and

the second oscillator comprises a current mode oscillator.

10. The apparatus of claim 9, wherein:

the voltage mode oscillator includes:

an amplification circuit comprising a plurality of amplifier branches; and

a power circuit coupled to the amplification circuit, the power circuit comprising:

first switches respectively coupled between the plurality of amplifier branches and a supply voltage; and

second switches respectively coupled between the plurality of amplifier branches and ground,

the power circuit is configured to connect different numbers of the plurality of amplifier branches together in parallel via the first switch and the second switch; and

the step control circuit is configured to generate a step control signal that incrementally increases the number of the plurality of amplifier branches connected together in parallel via the power circuit to incrementally increase the first gain of the voltage mode oscillator.

11. The apparatus of claim 9, wherein:

the current mode oscillator includes:

a variable current source configured to generate a bias current; and

an amplification circuit coupled to the variable current source; and

the step control circuit is configured to generate a step control signal that incrementally increases the magnitude of the bias current to incrementally increase the second gain of the current mode oscillator.

12. The apparatus of claim 1, further comprising:

a wireless transceiver; and

a clock generator comprising an output node coupled to the wireless transceiver, the multi-mode oscillation circuitry, and the step control circuit, the clock generator configured to generate a clock signal at the output node.

13. The apparatus of claim 12, wherein:

the wireless transceiver is configured to selectively operate in a first mode of operation or a second mode of operation, the first mode of operation having a first target phase noise level that is lower than a second target phase noise level of the second mode of operation;

the first oscillator is configured to consume a first amount of power to generate a first oscillating signal having a first amount of phase noise;

the second oscillator is configured to consume a second amount of power to generate a second oscillating signal having a second amount of phase noise, the second amount of phase noise being greater than the first amount of phase noise, the second amount of power being lower than the first amount of power;

the resonator is configured to selectively:

generating the clock signal based on the first oscillation signal; or

Generating the clock signal based on the second oscillation signal; and

the multi-mode oscillation circuitry is configured to selectively be in:

the first configuration based on the first mode of operation; or

The second configuration based on the second mode of operation.

14. The apparatus of claim 12, further comprising:

a display screen; and

a processor operatively coupled to the display screen and the wireless transceiver, the processor configured to present one or more graphical images on the display screen based on signals communicated by the wireless transceiver using the clock signal.

15. The apparatus of claim 12, wherein:

the clock generator further includes a synchronizer coupled between the output node and the step control circuit, the synchronizer configured to:

generating a timing signal at a time occurring between two zero crossings of the clock signal, the timing signal causing the step control circuit to increase the first gain of the first oscillator, the time associated with a peak or a trough of the clock signal.

16. An apparatus, comprising:

multi-mode oscillating circuitry configured to be selectively in a first configuration or a second configuration, the multi-mode oscillating circuitry comprising:

a resonator;

a first oscillator coupled to the resonator, the first oscillator configured to be selectively in:

an active state based on the first configuration; and

an inactive state based on the second configuration; and

a second oscillator coupled to the resonator, the second oscillator configured to be selectively in:

the inactive state based on the first configuration; and

the active state based on the second configuration; and

a stepping component to cause the first oscillator to switch from the inactive state to the active state and to incrementally increase a first gain of the first oscillator to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

17. The apparatus of claim 16, wherein:

the step component is configured to incrementally increase the first gain of the first oscillator in two or more steps; and

the second oscillator is configured to be in the active state while the stepping component incrementally increases the first gain of the first oscillator.

18. The apparatus of claim 16, wherein the stepping component is configured to:

incrementally increasing the first gain of the first oscillator to a target gain; and

causing the second oscillator to switch from the active state to the inactive state in response to the first gain of the first oscillator being at the target gain.

19. The apparatus of claim 18, wherein:

the step component is configured to incrementally decrease a second gain of the second oscillator prior to causing the second oscillator to switch from the active state to the inactive state.

20. The apparatus of claim 16, wherein:

the step means comprises digital means for generating a step control signal, the step control signal controlling the first gain of the first oscillator.

21. The apparatus of claim 20, wherein:

the first oscillator includes:

an amplifying circuit comprising a plurality of amplifying branches;

a power circuit coupled to the amplification circuit, the power circuit comprising:

first switches respectively coupled between the plurality of amplifier branches and a supply voltage; and

second switches respectively coupled between the plurality of amplifier branches and ground,

the power circuit is configured to connect different numbers of the plurality of amplifier branches together in parallel via the first switch and the second switch;

the step control signal comprises discrete voltages which respectively control the states of the first switch and the second switch; and

the digital component is configured to incrementally increase a number of the plurality of amplifier branches connected together in parallel via the step control signal to incrementally increase the first gain of the first oscillator.

22. The apparatus of claim 20, wherein:

the first oscillator includes:

a variable current source configured to generate a bias current; and

an amplification circuit coupled to the variable current source;

the step control circuit controls the amplitude of the bias current; and

the digital component is configured to incrementally increase the first gain of the first oscillator via the step control signal to incrementally increase the magnitude of the bias current.

23. A method for operating multi-mode oscillating circuitry with step control, the method comprising:

generating a clock signal using a resonator of the multi-mode oscillation circuitry, the multi-mode oscillation circuitry including a first oscillator and a second oscillator, the first oscillator and the second oscillator coupled to the resonator;

operating the multi-mode oscillation circuitry in a first configuration to enable the resonator to generate the clock signal, the first configuration comprising the first oscillator in an active state and the second oscillator in an inactive state;

operating the multi-mode oscillation circuitry in a second configuration to enable the resonator to generate the clock signal, the second configuration comprising the first oscillator in the inactive state and the second oscillator in the active state; and

transition from the multi-mode oscillation circuitry operating in the second configuration to the multi-mode oscillation circuitry operating in the first configuration by incrementally increasing a first gain of the first oscillator while the second oscillator is in the active state.

24. The method of claim 23, wherein:

the transition from the multi-mode oscillation circuitry operating in the second configuration to the multi-mode oscillation circuitry operating in the first configuration comprises:

incrementally increasing the first gain of the first oscillator to a target gain in two or more steps; and

causing the second oscillator to switch from the active state to the inactive state in response to the first gain of the first oscillator being at the target gain.

25. The method of claim 24, wherein:

the transition from the multi-mode oscillation circuitry operating in the second configuration to the multi-mode oscillation circuitry operating in the first configuration comprises:

incrementally decreasing a second gain of the second oscillator prior to causing the second oscillator to switch from the active state to the inactive state.

26. The method of claim 23, further comprising:

transition from the multi-mode oscillation circuitry operating in the first configuration to the multi-mode oscillation circuitry operating in the second configuration by incrementally increasing a second gain of the second oscillator.

27. The method of claim 23, wherein:

the operation of the multi-mode oscillating circuitry in the first configuration comprises:

generating a first oscillating signal via the first oscillator; and

generating the clock signal based on the first oscillation signal;

the operation of the multi-mode oscillating circuitry in the second configuration comprises:

generating a second oscillation signal via the second oscillator; and

generating the clock signal based on the second oscillation signal; and

the transition from the multi-mode oscillation circuitry operating in the second configuration to the multi-mode oscillation circuitry operating in the first configuration comprises:

generating the first oscillating signal via the first oscillator;

generating the second oscillating signal via the second oscillator; and

generating the clock signal based on both the first oscillation signal and the second oscillation signal.

28. An apparatus, comprising:

a clock generator, comprising:

multi-mode oscillating circuitry comprising:

a resonator;

a first oscillator coupled to the resonator, the first oscillator configured to be selectively in an active state or an inactive state; and

a second oscillator coupled to the resonator, the second oscillator configured to be selectively in the active state or the inactive state; and

a step control circuit comprising:

a first further driver coupled to the first oscillator and configured to incrementally adjust a first gain of the first oscillator while the second oscillator is in the active state; and

a second step driver coupled to the second oscillator and configured to incrementally adjust a second gain of the second oscillator while the first oscillator is in the active state.

29. The apparatus of claim 28, wherein the clock generator comprises a synchronizer coupled between the multi-mode oscillation circuitry and the step control circuit, the synchronizer configured to control a time at which the first step driver adjusts the first gain and a time at which the second step driver adjusts the second gain.

30. The apparatus of claim 28, wherein:

the first oscillator comprises a voltage mode oscillator; and

the second oscillator comprises a current mode oscillator.

Technical Field

The present disclosure relates generally to clock generation and, more particularly, to multi-mode oscillation circuitry with step control for smooth transitions between different configurations utilizing different oscillators.

Background

Electronic devices use Radio Frequency (RF) signals to communicate information. These radio frequency signals enable users to talk with friends, download information, share pictures, remotely control home devices, receive global positioning information, detect and track with radar, or listen to radio stations. To generate these radio frequency signals, the electronic device may include a clock generator that generates a clock signal. The clock signal provides a stable frequency reference for performing wireless communications. For example, the clock signal may be provided to a mixer for frequency conversion (e.g., up-conversion or down-conversion of the communication signal) or a phase-locked loop for generating another signal having a different stable frequency reference.

Due to the dependence on the clock signal, any frequency error or noise in the clock signal directly affects the communication quality and performance. In some cases, operations performed using the clock signal may also increase the amplitude of the frequency error or noise of the clock signal. As such, it is important that the noise in the clock signal be within some predetermined threshold. One particular type of noise is phase noise, which represents random fluctuations in the phase of a clock signal. A high level of phase noise may increase the overall noise floor of the receiver, thereby reducing the sensitivity or dynamic range of the electronic device. This makes it more challenging for the electronic device to detect weaker signals or signals originating from greater distances.

The phase noise performance of a clock generator may depend on many factors including power consumption and component type. Better phase noise performance is typically achieved by higher power consumption or by utilizing larger size components. The former is expensive in terms of battery use, while the latter is expensive in terms of equipment cost. Still further, different communication standards may be associated with different phase noise thresholds. If the electronic device supports multiple communication standards (e.g., cellular, Global Positioning System (GPS), Wi-Fi^TMOr Bluetooth^TM) The design of the clock generator may have to support more than one phase noise threshold. In general, it becomes challenging to design a clock generator that supports multiple communication standards, saves power, and physically fits within a specified space.

Disclosure of Invention

An apparatus implementing multi-mode oscillating circuitry with step control is disclosed. The clock generator generates a clock signal using multi-mode oscillating circuitry that includes two or more oscillators separately coupled to a resonator. In a first configuration, the multi-mode oscillation circuitry operates with the first oscillator in an active state and the second oscillator in an inactive state. In a second configuration, the multi-mode oscillation circuitry operates with the first oscillator in an inactive state and the second oscillator in an active state.

In some cases, oscillators are designed to have different performance characteristics. For example, the first oscillator may generate a lower amount of phase noise relative to the second oscillator. However, the second oscillator may consume less power relative to the first oscillator. As such, the configuration of the multi-mode oscillation circuitry may be appropriately selected based on the operating mode of the wireless transceiver. However, abrupt switching between two or more configurations can adversely affect the clock signal generated using the multimode oscillating circuitry.

Instead of switching abruptly between different configurations as the operating mode of the wireless transceiver changes, the step control circuit enables the multi-mode oscillating circuitry to smoothly transition between different configurations. As described herein, a step control circuit incrementally adjusts respective gains of the oscillators to continuously provide a clock signal while mitigating glitches or other interference on the clock signal. This enables a sensitive system to reliably use a clock signal, such as a digital system operating to provide wireless communication. In these ways, a single resonator may be used with multiple oscillators to provide multiple clock signals with different characteristics at lower cost and in a smaller footprint.

In one example aspect, an apparatus is disclosed. The apparatus includes multi-mode oscillating circuitry configured to be selectively in a first configuration or a second configuration. The multi-mode oscillating circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator is configured to be selectively in an active state based on a first configuration and an inactive state based on a second configuration. The second oscillator is configured to be selectively in an inactive state based on the first configuration and an active state based on the second configuration. The apparatus also includes a step control circuit coupled to the multi-mode oscillation circuitry. The step control circuit is configured to cause the first oscillator to switch from an inactive state to an active state. The step control circuit is further configured to incrementally increase a first gain of the first oscillator based on the first oscillator being in an active state to enable the multi-mode oscillating circuitry to transition from the second configuration to the first configuration.

In one example aspect, an apparatus is disclosed. The apparatus includes multi-mode oscillating circuitry configured to be selectively in a first configuration or a second configuration. The multi-mode oscillating circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator is configured to be selectively in an active state based on a first configuration and an inactive state based on a second configuration. The second oscillator is configured to be selectively in an inactive state based on the first configuration and an active state based on the second configuration. The apparatus also includes a step component to cause the first oscillator to switch from an inactive state to an active state and to incrementally increase a first gain of the first oscillator to enable the multi-mode oscillating circuitry to transition from the second configuration to the first configuration.

In one example aspect, a method for operating multi-mode oscillating circuitry with step control is disclosed. The method comprises the following steps: a clock signal is generated using a resonator of a multi-mode oscillating circuitry. The multi-mode oscillating circuitry includes a first oscillator and a second oscillator coupled to a resonator. The method further comprises the following steps: the multi-mode oscillation circuitry is operated in a first configuration to enable the resonator to generate the clock signal, the first configuration including a first oscillator in an active state and a second oscillator in an inactive state. The method further comprises the following steps: the multi-mode oscillation circuitry is operated in a second configuration to enable the resonator to generate the clock signal, the second configuration including the first oscillator in an inactive state and the second oscillator in an active state. Additionally, the method comprises: transition from the multi-mode oscillating circuitry operating in the second configuration to the multi-mode oscillating circuitry operating in the first configuration by incrementally increasing a first gain of the first oscillator while the second oscillator is in an active state.

In one example aspect, an apparatus is disclosed. The apparatus includes a clock generator including multi-mode oscillating circuitry and a step control circuit. The multi-mode oscillating circuit system includes a resonator, a first oscillator coupled to the resonator, and a second oscillator coupled to the resonator. The first oscillator and the second oscillator are individually configured to be selectively in an active state or an inactive state. The step control circuit includes a first step driver coupled to the first oscillator and configured to incrementally adjust a first gain of the first oscillator while the second oscillator is in an active state. The step control circuit also includes a second step driver coupled to the second oscillator and configured to incrementally adjust a second gain of the second oscillator while the first oscillator is in an active state.

Drawings

Fig. 1 illustrates an example operating environment for implementing multi-mode oscillating circuitry with step control.

Fig. 2 illustrates an example implementation of a clock generator implementing multi-mode oscillating circuitry with step control.

Fig. 3 illustrates an example sequence flow diagram for operating multi-mode oscillation circuitry with step control.

Fig. 4-1 illustrates example signals for operating multi-mode oscillating circuitry with step control.

Fig. 4-2 illustrates other example signals for operating multi-mode oscillating circuitry with step control.

Fig. 5 illustrates an example voltage mode oscillator for implementing multi-mode oscillation circuitry with step control.

Fig. 6 illustrates an example current mode oscillator for implementing multi-mode oscillation circuitry with step control.

Fig. 7 is a flow chart illustrating an example process for operating multi-mode oscillation circuitry with step control.

Detailed Description

Electronic devices use clock generators to support radio frequency communications. The clock generator generates a reference clock signal having a predetermined frequency. The clock signal may be referenced by other components in the electronic device, including mixers, signal generators, phase-locked loops (PLLs), delay-locked loops (DLLs), and the like. Due to the dependence on the clock signal, any frequency error or phase noise in the clock signal may propagate to downstream circuit components, affecting processing or communication quality and performance. Additionally, different communication standards may be associated with different phase noise thresholds. If the electronic device supports multiple communication standards (e.g., cellular, Global Positioning System (GPS), Wi-Fi^TMOr Bluetooth^TM) The design of the clock generator may have to support more than one phase noise threshold.

To support different communication standards, some technologies use different oscillating circuitry that uses different resonators. The performance of each oscillating circuitry may be adjusted for the corresponding communication standard. However, implementing multiple oscillating circuitry adds additional complexity to the electronic device and increases cost. Further, multiple oscillating circuitry may occupy additional space in the electronic device and involve additional wiring.

In contrast, example methods for multi-mode oscillating circuitry with step control are described herein. The clock generator generates a clock signal using multi-mode oscillating circuitry that includes two or more oscillators separately coupled to a resonator. In a first configuration, the multi-mode oscillation circuitry operates with the first oscillator in an active state and the second oscillator in an inactive state. In a second configuration, the multi-mode oscillation circuitry operates with the first oscillator in an inactive state and the second oscillator in an active state.

In some cases, oscillators are designed to have different performance characteristics. For example, the first oscillator may generate a lower amount of phase noise relative to the second oscillator. However, the second oscillator may consume less power relative to the first oscillator. As such, the configuration of the multi-mode oscillation circuitry may be appropriately selected based on the operating mode of the wireless transceiver. However, abrupt switching between two or more configurations can adversely affect the clock signal generated using the multimode oscillating circuitry.

Instead of switching abruptly between different configurations as the operating mode of the wireless transceiver changes, the step control circuit enables the multi-mode oscillating circuitry to smoothly transition between different configurations. As described herein, a step control circuit incrementally adjusts respective gains of the oscillators to continuously provide a clock signal while mitigating glitches or other interference on the clock signal. This enables a sensitive system to reliably use a clock signal, such as a digital system operating to provide wireless communication. In these ways, a single resonator may be used with multiple oscillators to provide multiple clock signals with different characteristics at lower cost and in a smaller footprint.

Fig. 1 illustrates an example environment 100 for implementing multi-mode oscillating circuitry with step control. In the environment 100, the computing device 102 communicates with the base station 104 over a wireless communication link 106 (wireless link 106). In this example, computing device 102 is depicted as a smartphone. However, the computing device 102 may be implemented as any suitable computing or electronic device, such as a modem, cellular base station, broadband router, access point, cellular telephone, gaming device, navigation device, media device, laptop, desktop, tablet, wearable computer, server, Network Attached Storage (NAS) device, smart device or other internet of things (IoT) device, medical device, in-vehicle communication system, radar, radio, and so forth.

The base station 104 communicates with the computing device 102 via a wireless link 106, which wireless link 106 may be implemented as any suitable type of wireless link. Although depicted as a tower of a cellular network, the base station 104 may represent or be implemented as another device, such as a satellite, a server device, a terrestrial television broadcast tower, an access point, a peer device, a mesh network node, a fiber optic line, and so forth. Thus, the computing device 102 may communicate with the base station 104 or another device via a wired connection, a wireless connection, or a combination thereof.

The wireless link 106 may include a downlink for data or control information communicated from the base station 104 to the computing device 102 or an uplink for other data or control information communicated from the computing device 102 to the base station 104. The wireless link 106 may be implemented using any suitable communication protocol or standard, such as a second generation (2G), third generation (3G), fourth generation (4G), or fifth generation (5G) cell; IEEE 802.11 (e.g., Wi-Fi)^TM) (ii) a IEEE 802.15 (e.g., Bluetooth)^TM) (ii) a IEEE 802.16 (e.g., WiMAX)^TM) And the like. In some implementations, the wireless link 106 may provide power wirelessly and the base station 104 may include a power source.

As shown, the computing device 102 includes an application processor 108 and a computer-readable storage medium 110(CRM 110). The application processor 108 may include any type of processor, such as a multi-core processor, that executes processor executable code stored by the CRM 110. CRM110 may include any suitable type of data storage medium, such as volatile memory (e.g., Random Access Memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., a magnetic disk), and so forth. In the context of the present disclosure, the CRM110 is implemented to store instructions 112, data 114, and other information for the computing device 102, and therefore does not include a transient propagated signal or carrier wave.

The computing device 102 may also include input/output ports 116(I/O ports 116) and a display 118. The I/O ports 116 enable data exchange or interaction with other devices, networks, or users. The I/O ports 116 can include a serial port (e.g., a Universal Serial Bus (USB) port), a parallel port, an audio port, an Infrared (IR) port, a user interface port such as a touch screen, etc. The display 118 presents graphics of the computing device 102, such as a user interface associated with an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a displayport or virtual interface through which graphical content of the computing device 102 is presented.

The wireless transceiver 120 of the computing device 102 provides connectivity to the corresponding network and other electronic devices connected thereto. Alternatively or additionally, the computing device 102 may include a wired transceiver, such as an ethernet or fiber optic interface, for communicating over a local network, an intranet, or the internet. The wireless transceiver 120 may facilitate communication over any suitable type of wireless network, such as a Wireless Local Area Network (WLAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a Wireless Wide Area Network (WWAN), and/or a Wireless Personal Area Network (WPAN). In the context of the example environment 100, the wireless transceiver 120 enables the computing device 102 to communicate with the base station 104 and the networks connected thereto. However, wireless transceiver 120 may also enable computing device 102 to communicate "directly" with other devices or networks.

The wireless transceiver 120 includes circuitry and logic for transmitting and receiving communication signals via the antenna 122. The components of wireless transceiver 120 may include mixers, phase-locked loops, delay-locked loops, amplifiers, switches, analog-to-digital converters, filters, etc. for conditioning communication signals (e.g., for generating or processing signals). The wireless transceiver 120 may also include logic to perform in-phase/quadrature (I/Q) operations such as combining, encoding, modulating, decoding, demodulating, and so forth. In some cases, the components of the wireless transceiver 120 are implemented as separate receiver and transmitter entities. Additionally or alternatively, the wireless transceiver 120 may be implemented using multiple or different parts to implement respective receive and transmit operations (e.g., separate transmit and receive chains). Generally, wireless transceiver 120 processes data and/or signals associated with communicating data of computing device 102 through antenna 122.

As shown, the wireless transceiver 120 also includes at least one clock generator 124 and at least one processor 126. Alternatively, the clock generator 124 may be implemented separately from and coupled to the wireless transceiver 120. In some implementations, the clock generator 124 and the processor 126 are implemented on separate integrated circuits. In general, clock generator 124 uses a resonator to generate a clock signal rather than referencing another clock signal. This is in contrast to other signal generating components, such as PLLs, which use the clock signal from the clock generator to generate other versions of the clock signal having different frequencies. Generally, the clock signal generated by the clock generator 124 is a reference clock signal provided to other components of the wireless transceiver 120. The clock signal may additionally or alternatively be used to synchronize the timing operations of the logic. Clock generator 124 includes multi-mode oscillation circuitry 128, at least one step control circuit 130, and at least one synchronizer 132, which are further described with respect to fig. 2.

Processor 126, which may include a modem, may be implemented within wireless transceiver 120 or separate from wireless transceiver 120. As an example, the processor 126 is implemented as a system on a chip (SoC) that provides a digital communication interface for data, voice, messaging, and other applications of the computing device 102. The processor 126 may also include baseband circuitry to perform high-speed sampling processing, which may include analog-to-digital conversion, digital-to-analog conversion, gain correction, skew correction, frequency conversion, and so forth. Although not explicitly shown, the processor 126 may comprise a portion of the CRM110 or may access the CRM110 to obtain computer-readable instructions.

The processor 126 controls the wireless transceiver 120 and enables wireless communication to be performed. The processor 126 may provide the communication data to the wireless transceiver 120 for transmission. Processor 126 may also process a baseband version of the signal accepted from wireless transceiver 120 to generate data that may be provided to other portions of computing device 102 via a communication interface for wireless communication or proximity detection. Generally, the processor 126 controls the mode of operation or knows the mode of operation of the wireless transceiver 120. The different types of operating modes may include different transceiver modes (e.g., transmit mode or receive mode), different power modes (e.g., low power mode or high power mode), different resource control states (e.g., connected mode, inactive mode, or idle mode), different communication modes (e.g., 3G mode, 4G mode, 5G mode, Wi-Fi mode)^TMA mode, a GPS mode), a different modulation mode (e.g., a lower order modulation mode such as a Quadrature Phase Shift Keying (QPSK) mode or a higher order modulation mode such as 64 Quadrature Amplitude Modulation (QAM) or 256 QAM), etc. The processor 126 causes the configuration of the multi-mode oscillation circuitry 128 to change based on the operating mode of the wireless transceiver 120, as further described with respect to fig. 2.

Fig. 2 illustrates an example implementation of the clock generator 124 implementing multi-mode oscillation circuitry 128 with step control. In the depicted configuration, clock generator 124 includes multi-mode oscillation circuitry 128, step control circuitry 130, and synchronizer 132. Clock generator 124 also includes an output node 202, which output node 202 may be coupled to other circuit components within wireless transceiver 120, such as a PLL or mixer. Multimode oscillating circuitry 128 is coupled between step control circuit 130 and output node 202. The synchronizer is coupled between the output node 202 and the step control circuit 130.

The multi-mode oscillation circuitry 128 includes at least two oscillators 204-1 and 204-2 and at least one resonator 206 (e.g., at least one resonator). In some implementations, oscillators 204-1 and 204-2 are implemented on an integrated circuit and resonator 206 is implemented on a Printed Circuit Board (PCB). Resonator 206 is coupled between resonator nodes 208-1 and 208-2. In FIG. 2, resonator node 208-2 is shown coupled to output node 202. As such, resonator node 208-1 represents an input node of resonator 206, and resonator node 208-2 represents an output node of resonator 206. Each oscillator 204-1 and 204-2 is coupled to both resonator node 208-1 and resonator node 208-2.

In some implementations, the design of oscillators 204-1 and 204-2 have different performance characteristics. By way of example, oscillator 204-1 may generate a lower amount of phase noise relative to oscillator 204-2, but oscillator 204-2 may consume less power relative to oscillator 204-1. Oscillators 204-1 and 204-2 may be implemented as voltage mode oscillators, current mode oscillators, or a combination thereof. An example voltage-mode oscillator and an example current-mode oscillator are further described with respect to fig. 5 and 6, respectively. Generally, oscillators 204-1 and 204-2 include power circuitry and amplification circuitry.

Oscillators 204-1 and 204-2 may be independently configured to be in an active state or an inactive state. In the active state, the oscillator 204-1 or 204-2 consumes power and operates at a particular gain. Additionally, the oscillator 204-1 or 204-2 generates an oscillating signal 210 having a peak-to-peak voltage based on the gain. The oscillating signal 210 enables the resonator 206 to resonate. In FIG. 2, oscillator 204-1 generates oscillation signal 210-1 and oscillator 204-2 generates oscillation signal 210-2. While in the active state, the gain of the oscillator 204-1 or 204-2 may be varied. The different gains may cause the oscillator 204-1 or 204-2 to consume different amounts of power or generate different amounts of phase noise.

In the inactive state, oscillator 204-1 or 204-2 generates no oscillating signal 210 or generates an oscillating signal 210 having a peak-to-peak voltage that does not cause resonator 206 to resonate. In general, based on the inactive state, the oscillating signal 210 has a lower peak-to-peak voltage relative to any of the gain-based peak-to-peak voltages associated with the active state.

The resonator 206 may comprise, for example, a quartz crystal, as shown by quartz crystal 212. In other implementations, the resonator 206 may include an inductor capacitor (LC) resonator, a resonator transistor (e.g., a Bipolar Junction Transistor (BJT), junction gate field effect transistor (JFET), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), or gallium arsenide field effect transistor (GaAsFET))), a transmission line, a diode, a piezoelectric oscillator, a plurality of quartz crystals 212, a plurality of resonators, and so forth. The resonator 206 resonates at a particular frequency.

The multi-mode oscillating circuit system 128 also includes an amplifier 214, the amplifier 214 being coupled between the resonator node 208-2 and the output node 202. Although not shown, the multi-mode oscillation circuitry 128 may include other types of components, such as resistors and capacitors.

Step control circuit 130 is coupled between processor 126 and multi-mode oscillation circuitry 128 and includes at least two step drivers 216-1 and 216-2. Step drivers 216-1 and 216-2 are coupled to oscillators 204-1 and 204-2, respectively, and generate step control signals 218-1 and 218-2, respectively. Step control signals 218-1 and 218-2 control whether oscillators 204-1 and 204-2 are in an active state or an inactive state, respectively. Additionally, if oscillators 204-1 and 204-2 are in an active state, step control signals 218-1 and 218-2 control the respective gains of oscillators 204-1 and 204-2. Step drivers 216-1 and 216-2 may be implemented as digital voltage generators that generate control voltages or discrete voltages that are provided to components within oscillators 204-1 and 204-2 via step control signals 218-1 and 218-2, respectively.

Synchronizer 132 provides feedback information to step control circuit 130 based on clock signal 220, which clock signal 220 is generated by resonator 206 at resonator node 208-2. Specifically, synchronizer 132 generates a timing signal 222, which timing signal 222 includes a trigger to cause step driver 216-1 to adjust the gain of oscillator 204-1 or step driver 216-2 to adjust the gain of oscillator 204-2 at a particular time. In this manner, synchronizer 132 may cause the gains of oscillators 204-1 and 204-2 to change during times when clock signal 220 is not near zero crossings. By varying the gain around the peaks of the clock signal 220, glitch errors in the clock signal 220 can be avoided.

During operation, the processor 126 determines the operating mode of the wireless transceiver 120. Based on the mode of operation, processor 126 generates oscillator status signals 224-1 and 224-2, which oscillator status signals 224-1 and 224-2 control whether oscillators 204-1 and 204-2 are in an active state or an inactive state, respectively. Processor 126 also generates target gain signals 226-1 and 226-2, which target gain signals 226-1 and 226-2 specify target gains for oscillation signals 210-1 and 210-2, respectively.

The step drivers 216-1 and 216-2 appropriately configure the oscillators 204-1 and 204-2 by generating step control signals 218-1 and 218-2 based on the oscillator state signals 224-1 and 224-2 and the target gain signals 226-1 and 226-2. Based on the step control signals 218-1 and 218-2, the oscillators 204-1 and 204-2 generate oscillation signals 210-1 and 210-2, respectively. Due to the oscillating signals 210-1 and/or 210-2, the resonator 206 resonates and generates a clock signal 220, which clock signal 220 is amplified by the amplifier 214. Using the oscillator state signals 224-1 and 224-2 and the target gain reference signals 226-1 to 226-2, the processor 126 may cause the multi-mode oscillation circuitry 128 to be in a particular configuration and to switch between different configurations over time, as further described with respect to fig. 3.

Fig. 3 illustrates an example sequence flow diagram 300 for operating the multi-mode oscillation circuitry 128 with step control, where time passes in a downward direction. In the depicted example, the multi-mode oscillation circuitry 128 may be in the first configuration 302 or the second configuration 304 at different times. In the first configuration 302, the oscillator 204-1 is in an active state 306 and the oscillator 204-2 is in an inactive state 308. Additionally, for the first configuration 302, the gain of the oscillator 204-1 is at a first target gain. Oscillator 204-1 generates a first amount of phase noise and consumes a first amount of power at a first target gain.

In second configuration 304, oscillator 204-1 is in inactive state 308 and oscillator 204-2 is in active state 306. Additionally, for the second configuration 304, the gain of the oscillator 204-2 is at a second target gain. Oscillator 204-2 generates a second amount of phase noise and consumes a second amount of power at a second target gain.

For example, consider that a first amount of phase noise generated under the first configuration 302 is lower than a second amount of phase noise generated under the second configuration 304. However, the second amount of power consumed in the second configuration 304 is lower than the first amount of power consumed in the first configuration 302. Thus, the phase noise performance produced by the first configuration 302 is better and the power consumption produced by the second configuration 304 is reduced.

At 310, the wireless transceiver 120 is in a second mode of operation 312 with a particular target phase noise level. As an example, the second operation mode 312 may represent a connected mode for 4G or an idle mode for 5G. In this case, the target phase noise level for the second mode of operation 312 may be achieved using either the first configuration 302 or the second configuration 304. However, because the second configuration 304 saves power, the processor 126 causes the multi-mode oscillation circuitry 128 to operate in the second configuration 304.

At 314, the wireless transceiver 120 is in a first mode of operation 316, the first mode of operation 316 having a lower target phase noise level relative to the second mode of operation 312. As an example, the first operation mode 316 may represent a connection mode for 5G. In this case, the target phase noise level for the first mode of operation 316 may be achieved using the first configuration 302 but not the second configuration 304. As such, the processor 126 causes the multimode oscillating circuitry 128 to operate in the first configuration 302 to enable the wireless transceiver 120 to meet the target phase noise level of the first operating mode 316.

At 318, the wireless transceiver 120 is in the second operating mode 312. Thus, the processor 126 causes the multi-mode oscillation circuitry 128 to operate in the second configuration 304 to conserve power.

As the wireless transceiver 120 switches between the second operating mode 312 and the first operating mode 316, rather than abruptly switching between the second configuration 304 and the first configuration 302, the step control circuit 130 causes the multi-mode oscillation circuitry 128 to incrementally transition between the second configuration 304 and the first configuration 302. Specifically, as further described with respect to fig. 4-1 and 4-2, the step control circuit 130 incrementally adjusts the gains of the oscillator 204-1 and the oscillator 204-2 to enable the multi-mode oscillating circuitry 128 to transition between the second configuration 304 and the first configuration 302 without introducing glitch errors or stopping the clock signal 220.

Fig. 4-1 and 4-2 illustrate example signals for operating multi-mode oscillation circuitry 128 with step control. In particular, the signals shown in fig. 4-1 and 4-2 illustrate incremental transitions that occur from transitions between operating the multi-mode oscillation circuitry 128 in the second configuration 304 and operating the multi-mode oscillation circuitry 128 in the first configuration 302. Graphs 400, 402, 404, 406 illustrate changes in step control signal 218-2, step control signal 218-1, oscillation signal 210-1, and oscillation signal 210-2, respectively, that may occur during a transition.

In a first example, the multi-mode oscillation circuitry 128 transitions from the second configuration 304 to the first configuration 302, which may occur between 310 and 314 in fig. 3. Assume that the target gain 412 of the first configuration 302 is gain 410-4. However, other modes of operation may associate a target gain with a different gain, such as one of gains 410-1, 410-2, or 410-3. Oscillators 204-1 and 204-2 may operate in active state 306 with different gains. For example, oscillator 204-1 may operate with gains 408-1, 408-2, 408-3, and 408-4 ordered from lowest gain to highest gain. Additionally, oscillator 204-2 may operate with gains 410-1, 410-2, 410-3, and 410-4 also ordered from lowest gain to highest gain. Gains 408-1 through 408-4 and gains 410-1 through 410-4 may represent different gains (e.g., gains 408-1 through 408-4 are not necessarily equal to gains 410-1 through 410-4). In this example, oscillator 204-1 may operate with four different gains 408-1 through 408-4, while oscillator 204-2 may operate with four different gains 410-1 through 410-4. In other examples, oscillator 204-1 may operate with a different amount of gain relative to oscillator 204-2.

At time T0, the multi-mode oscillating circuitry 128 operates in the second configuration 304. In graph 400, step control signal 218-2 is at a level such that oscillator 204-2 is in active state 306 and has gain 408-4. In graph 402, step control signal 218-1 is at a level such that oscillator 204-1 is in inactive state 308. In the inactive state 308, the oscillator 204-1 does not generate the oscillating signal 210-1, as shown in the graph 404.

At time T1, the multi-mode oscillation circuitry 128 begins to transition to the first configuration 302 as the stepper driver 216-1 causes the oscillator 204-1 to switch from the inactive state 308 to the active state 306. To do so, the step control signal 218-1 rises to another level at T1, which places the oscillator 204-1 in the active state 306 with the gain 410-1. Thus, the oscillator 204-1 generates the oscillating signal 210-1 having a first peak-to-peak voltage, as shown in the graph 404.

From time T2 to time T3 to time T4, the multimode oscillating circuitry 128 continues to transition to the first configuration 302 as the stepper driver 216-1 incrementally increases the gain of the oscillator 204-1 until the target gain 412 is achieved. To do so, step driver 216-1 incrementally increases the level of step control signal 218-1, which causes the gain of oscillator 204-1 to be changed in steps (e.g., from gain 410-1 to gain 410-2 to gain 410-3 to gain 410-4). By incrementally changing the gain, oscillator 204-1 incrementally increases the peak-to-peak voltage of oscillating signal 210-1, as shown in graph 404. To mitigate glitch errors, synchronizer 132 causes the level of step control signal 218-1 to change at times T2, T3, and T4, which occur near the peak of oscillation signal 210-1 as shown in FIG. 4-1 (the trough in an alternative implementation not shown) and away from the zero-crossing point of oscillation signal 210-1. During this time, oscillator 204-2 continues to be in active state 306 with gain 408-4.

At time T4, oscillator 204-1 is at target gain 412 (e.g., gain 410-4). However, because the oscillator 204-2 is in the active state 306, the multi-mode oscillation circuitry 128 is still in the transitional configuration at time T4. In other words, the multi-mode oscillation circuitry 128 is not in the first configuration 302 and is not in the second configuration 304 at time T4. To address this issue, the step control signal 218-2 is adjusted, as further described with respect to fig. 4-2.

In fig. 4-2, the multi-mode oscillation circuitry 128 continues to transition to the first configuration 302 from time T5 to time T6 to time T7 to time T8 because the stepper driver 216-2 incrementally decreases the gain of the oscillator 204-2 before causing the oscillator 204-2 to switch from the active state 306 to the inactive state 308 at time T8. To do so, step driver 216-2 incrementally decreases the level of step control signal 218-2, which causes the gain of oscillator 204-2 to change at intervals (e.g., from gain 408-4 to gain 408-3 to gain 408-2 to gain 408-1). By incrementally changing the gain, oscillator 204-2 incrementally decreases the peak-to-peak voltage of oscillating signal 210-2, as shown in graph 406. To mitigate glitch errors, synchronizer 132 causes the level of step control signal 218-2 to change at times T5, T6, and T7, which occur near the trough (or peak in an alternative implementation not shown) as shown in fig. 4-2 and away from the zero crossing point. At time T7, oscillator 204-2 operates in active state 306 with the lowest gain (e.g., gain 408-1). From time T5 to time T7, oscillator 204-1 continues to be in active state 306 with gain 410-4, as shown in graph 402.

At time T8, the multi-mode oscillation circuitry 128 completes the transition to the first configuration 302 in response to the stepper driver 216-2 causing the oscillator 204-2 to switch from the active state 306 to the inactive state 308 at time T8. To do so, step driver 216-2 reduces step control signal 218-2 to another level at T8, which causes oscillator 204-2 to be in inactive state 308, as shown in graph 400. Therefore, oscillator 204-2 does not generate oscillation signal 210-2, as shown in graph 406.

From time T4 to T8 and beyond, the oscillator 204-1 is in the active state 306 and continues to generate the oscillating signal 210-1 having the gain 410-4 shown in the graph 404 at time T4. Since the multi-mode oscillating circuit system 128 is in the first configuration 302 at time T8, the resonator 206 generates the clock signal 220 based on the oscillating signal 210-1. This enables the clock signal 220 to meet the target phase noise level of the first mode of operation 316 of the wireless transceiver 120, as described above with respect to fig. 3. If the wireless transceiver 120 switches to the second operating mode 312, the multi-mode oscillation circuitry 128 may transition from the first configuration 302 to the second configuration 304 to conserve power.

As shown in fig. 4-2, incrementally reducing the gain of oscillating signal 210-2 enables a sensitive system to reliably use clock signal 220. For other types of less sensitive systems, the stepper driver 216-2 may cause the level of the stepper control signal 218-2 to change directly from T4 to T8. This causes the oscillator 204-2 to change directly from operating in the active state 306 with the gain 408-4 at time T4 to the inactive state 308 at time T8, which may reduce the time it takes for the multi-mode oscillating circuitry 128 to transition from the first configuration 302 to the second configuration 304. Additionally, because oscillator 204-1 is in active state 306 before oscillator 204-2 switches from active state 306 to inactive state 308, such a change may occur without stopping the generation of clock signal 220.

In a second example, the multi-mode oscillation circuitry 128 transitions from the first configuration 302 to the second configuration 304, which may occur between 314 and 318 in fig. 3. In this case, the operations described above are performed in the reverse order (e.g., from time T8 to time T1).

In general, the stepping rate or time period between T2, T3, T4, T5, T6, and T7 may be based on the period of the clock signal 220. As an example, the time period may be several periods of the clock signal 220 (e.g., ten or more periods of the clock signal 220). Additionally, the number of incremental steps that occur may vary based on a target gain 412, which target gain 412 may vary based on the operating mode of wireless transceiver 120. As an example, the target gain 412 of the first configuration 302 may be the gain 410-2 for the GPS mode. Alternatively, the target gain 412 of the first configuration 302 may be the gain 410-4 for the 5G mode.

In other implementations, the multi-mode oscillation circuitry 128 may include more than two oscillators 204. As such, the multi-mode oscillation circuitry 128 may operate according to more than two configurations (e.g., more than two modes). The techniques described above with respect to transitioning between the first configuration 302 and the second configuration 304 are equally applicable to transitioning between the first configuration 302 and the third configuration or between the second configuration 304 and the third configuration.

Fig. 5 illustrates an example voltage mode oscillator 500 for implementing the multi-mode oscillation circuitry 128 with step control. In some implementations, voltage mode oscillator 500 achieves better phase noise performance relative to a current mode oscillator. Voltage-mode oscillator 500 includes an input node 502, a power circuit 504, an amplification circuit 506, and an inverter 508. Consider voltage mode oscillator 500 implementing oscillator 204-1. In this case, input node 502 is coupled to stepper driver 216-1.

Power circuit 504 is coupled to input node 502, supply voltage 510, ground 512, and amplification circuit 506. The power circuit 504 includes first switches 516-1 to 516-N, the first switches 516-1 to 516-N coupled to the supply voltage 510 and the amplification circuit 506, where N represents a positive integer greater than 2. In the depicted configuration, the first switches 516-1 to 516-2 are implemented as p-channel metal oxide semiconductor field effect transistors (PMOSFETs). The power circuit 504 also includes second switches 518-1 through 518-N, the second switches 518-1 through 518-N being coupled to the ground 512 and the amplification circuit 506. The second switches 518-1 to 518-N are shown as N-channel metal oxide semiconductor field effect transistors (NMOSFETs) in FIG. 5.

The amplification circuit 506 may implement a low noise variable gain amplifier. The amplification circuit 506 includes a plurality of amplifier branches 514-1 through 514-N. The amplifier branches 514-1 through 514-N each include a Complementary Metal Oxide Semiconductor (CMOS) inverter. Each amplifier branch 514-1 to 514-N is coupled to one of the first switches 516-1 to 516-N and one of the second switches 518-1 to 518-N. The gates of the NMOSFET and PMOSFET within the CMOS inverter are coupled together to resonator node 208-1. The drains of the NMOSFETs and PMOSFETs within the CMOS inverter are coupled to the resonator node 208-2.

The step control signal 218-1 provides N discrete voltages to the second switches 518-1 through 518-N, respectively. These discrete voltages are also provided to inverter 508. The inverters 508 provide inverted versions of the discrete voltages to the respective first switches 516-1 through 516-N. Based on the discrete voltage provided by the step control signal 218-1, different combinations of amplifier branches 514-1 through 514-N within the amplification circuit 506 may be connected in parallel between the supply voltage 510 and the ground 512 to achieve different gains, such as the gains 410-1 through 410-4 in fig. 4-1. To place the voltage mode oscillator 500 in the inactive state 308, the stepped control signal 218-1 causes the first switches 516-1 through 516-N to disconnect the amplifier branches 514-1 through 514-N, respectively, from the supply voltage 510 and causes the second switches 518-1 through 518-N to disconnect the amplifier branches 514-1 through 514-N, respectively, from the ground 512.

Fig. 6 illustrates an example current mode oscillator 600 for implementing the multi-mode oscillation circuitry 128 with step control. In some implementations, the current mode oscillator 600 consumes less power relative to the voltage mode oscillator 500 of fig. 5. Current-mode oscillator 600 includes an input node 602, a power circuit 604, an amplification circuit 606, a variable current source 608, and an automatic gain control circuit 610. Consider a current mode oscillator 600 implementing oscillator 204-2. In this case, input node 602 is coupled to stepper driver 216-2.

The power circuit 604 is coupled to a variable current source 608, an amplification circuit 606, and a ground 512. The power circuit 504 includes a PMOSFET coupled between the variable current source 608 and the amplification circuit 606 and an NMOSFET coupled between the amplification circuit 606 and ground 512. The gates of the PMOSFET and NMOSFET are coupled to a voltage generator (not shown) that provides voltages that bias the PMOSFET and NMOSFET, respectively.

The amplification circuit 606 may implement a low power amplifier. In this example, the amplification circuit 606 includes one CMOS inverter. The gates of the NMOSFET and PMOSFET within the CMOS inverter are coupled together to resonator node 208-1. The drains of the NMOSFETs and PMOSFETs within the CMOS inverter are coupled to the resonator node 208-2.

Variable current source 608 is coupled to supply voltage 510, input node 602, automatic gain control circuit 610, and the PMOSFET of power circuit 604. In the depicted example, the variable current source 608 includes pairs of switches 612-1 to 612-M and PMOSFETs 614-1 to 614-M, which switches 612-1 to 612-M and PMOSFETs 614-1 to 614-M together are coupled in parallel between the supply voltage 510 and the sources of the PMOSFETs of the power circuit 604, where M represents a positive integer greater than two.

The automatic gain control circuit 610 is coupled between the resonator node 208-2 and the gates of the PMOSFETs 614-1 through 614-M. The automatic gain control circuit 610 generates a bias voltage 616 to bias the PMOSFETs 614-1 to 614-M based on the voltage at the resonator node 208-2.

The step control signal 218-2 provides M discrete voltages to the variable current source 608. These discrete voltages control the state of switches 612-1 to 612-M. Based on the discrete voltage provided by the stepped control signal 218-2, different combinations of the PMOSFETs 614-1 through 614-M are connected to the supply voltage 510 to generate bias currents having different magnitudes. The different magnitudes of the bias currents enable the current-mode oscillator 600 to achieve different gains, such as the gains 408-1 through 408-4 in fig. 4-2. To place the current mode oscillator 600 in the inactive state 308, the step control signal 218-2 causes the variable current source 608 to generate no bias current.

Fig. 7 is a flow chart illustrating an example process 700 for operating multi-mode oscillation circuitry with step control. The process 700 is described in terms of a set of blocks 702-708 that specify operations that can be performed. However, the operations are not necessarily limited to the order shown in fig. 7 or described herein, and the operations may be implemented in alternative orders or in a fully or partially overlapping manner. Moreover, more, fewer, and/or different operations may be implemented to perform process 700 or alternative processes. The operations represented by the illustrated blocks of process 700 may be performed by clock generator 124 (e.g., of fig. 1 or 2). More specifically, the operations of process 700 may be performed by multi-mode oscillation circuitry 128 and step control circuitry 130 as shown in fig. 2.

At block 702, a clock signal is generated using a resonator of a multi-mode oscillating circuitry. The multi-mode oscillating circuitry includes a first oscillator and a second oscillator coupled to the resonator. For example, the resonator 206 of the multi-mode oscillating circuitry 128 generates a clock signal 220, as shown in FIG. 2. The multi-mode oscillation circuitry 128 includes an oscillator 204-1 and an oscillator 204-2, each of the oscillator 204-1 and the oscillator 204-2 coupled to a resonator 206.

At block 704, the multi-mode oscillation circuitry operates in a first configuration that includes a first oscillator in an active state and a second oscillator in an inactive state to enable the resonator to generate a clock signal. For example, the multi-mode oscillation circuitry 128 operates in a first configuration 302, which first configuration 302 includes the oscillator 204-1 in the active state 306 and the second oscillator 204-2 in the inactive state 308, as shown at 314 in FIG. 3. The first configuration 302 enables the resonator 206 to generate the clock signal 220.

At block 706, the multi-mode oscillation circuitry operates in a second configuration that includes the first oscillator in an inactive state and the second oscillator in an active state to enable the resonator to generate the clock signal. For example, the multi-mode oscillation circuitry 128 operates in a second configuration 304, which second configuration 304 includes the oscillator 204-1 in the inactive state 308 and the second oscillator 204-2 in the active state 306, as shown in both 310 and 318 in fig. 3. The second configuration 304 enables the resonator 206 to generate the clock signal 220.

At block 708, the multi-mode oscillation circuitry transitions to operate in the second configuration by incrementally increasing the first gain of the first oscillator while the second oscillator is in the active state to transition to operate in the first configuration. For example, based on step control circuit 130 incrementally increasing the first gain of first oscillator 204-1 while second oscillator 204-2 is in active state 306, multi-mode oscillation circuitry 128 transitions from operating in accordance with second configuration 304 to operating in accordance with first configuration 302, as shown in fig. 4-1.

As used herein, unless the context indicates otherwise, the word "or" may be considered to use the term "inclusively or" or permitting the inclusion or application of one or more items linked by the word "or" (e.g., the phrase "a or B" may be interpreted as permitting only "a", only "B", or permitting both "a" and "B"). Further, the items represented in the figures and the terms discussed herein may refer to one or more items or terms, and thus reference may be made interchangeably to items and terms in single or multiple forms in this written description. Finally, although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above, including not necessarily to the order in which the features are arranged or the acts performed.