阅读说明：本技术 一种完全自主可控快速时间频率同步装置和方法 (Completely autonomous controllable rapid time frequency synchronization device and method ) 是由 许国宏 王耀磊 李希彬 李雪 孙广俊 李星 宋征 于 2021-09-10 设计创作，主要内容包括：本发明公开了一种完全自主可控快速时间频率同步装置和方法,该装置包括时统模块、主控模块、分配模块、显示模块和电源模块；时统模块包括授时电路单元、控制电路单元、时钟电路单元和电源电路单元,授时电路单元包括GPS和北斗双模接收模块,时钟电路单元包括恒温晶振和与恒温晶振电连接的数模转换器,控制电路单元为FPGA；主控模块与上述GPS和北斗双模接收模块、恒温晶振、FPGA和显示模块电连接,输出NTP授时和串口授时,分配模块与恒温晶振电连接并输出5路标频,电源模块为同步装置内的各模块供电。本发明所公开的同步装置,为多系统、多站点、多设备时间频率同步提供了强有力的支撑,在电工技术、工业自动化及智能控制等领域有着巨大的应用潜力。(The invention discloses a completely autonomous controllable rapid time frequency synchronization device and a method, wherein the device comprises a time system module, a main control module, a distribution module, a display module and a power supply module; the time system module comprises a time service circuit unit, a control circuit unit, a clock circuit unit and a power supply circuit unit, wherein the time service circuit unit comprises a GPS and Beidou dual-mode receiving module, the clock circuit unit comprises a constant-temperature crystal oscillator and a digital-to-analog converter electrically connected with the constant-temperature crystal oscillator, and the control circuit unit is an FPGA; the master control module is electrically connected with the GPS and Beidou dual-mode receiving module, the constant-temperature crystal oscillator, the FPGA and the display module, NTP time service and serial port time service are output, the distribution module is electrically connected with the constant-temperature crystal oscillator and outputs 5 road pilot frequencies, and the power supply module supplies power for all modules in the synchronizing device. The synchronization device disclosed by the invention provides powerful support for time frequency synchronization of multiple systems, multiple sites and multiple devices, and has great application potential in the fields of electrical engineering, industrial automation, intelligent control and the like.)

1. A totally autonomous controllable fast time frequency synchronization device is characterized in that: the system comprises a timing module, a main control module, a distribution module, a display module and a power supply module; the time system module comprises a time service circuit unit, a control circuit unit, a clock circuit unit and a power circuit unit, wherein the time service circuit unit comprises a GPS and Beidou dual-mode receiving module, the clock circuit unit comprises a constant-temperature crystal oscillator and a digital-to-analog converter electrically connected with the constant-temperature crystal oscillator, the control circuit unit is an FPGA, external reference 1PPS signals output by the GPS and Beidou dual-mode receiving module and 1PPS signals output by the constant-temperature crystal oscillator are input into the FPGA, the FPGA carries out TDC time difference measurement on the two 1PPS signals to obtain time difference data, the measured time difference data are filtered to finally obtain adjusting voltage and provide the adjusting voltage for the digital-to-analog converter, in addition, the FPGA also outputs 5 paths of second pulse signals, and the power circuit unit supplies power to each circuit unit in the time system module; the master control module is electrically connected with the GPS and Beidou dual-mode receiving module, the constant-temperature crystal oscillator, the FPGA and the display module, NTP time service and serial port time service are output, the distribution module is electrically connected with the constant-temperature crystal oscillator and outputs 5 road pilot frequencies, and the power supply module supplies power for all modules in the synchronizing device.

2. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the time service circuit unit also comprises a time system antenna electrically connected with the GPS and Beidou dual-mode receiving module.

3. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the clock circuit unit further comprises a crystal oscillator calibration circuit.

4. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the constant temperature crystal oscillator divides the frequency of the 1PPS signal by the frequency signal of 10 MHz.

5. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: and when no external reference 1PPS signal exists, the FPGA automatically adjusts and controls the constant temperature crystal oscillator according to the constant temperature crystal oscillator aging curve and the frequency deviation of the oscillator.

6. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the FPGA utilizes a fast carry chain to construct the TDC, the time difference measurement resolution is 250ps, and filtering is carried out by a digital loop Kalman filter of the FPGA.

7. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the main control module is an embedded control module based on ARM.

8. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: and a 10MHz crystal filter is added at the clock input end of the distribution module.

9. The fully autonomous controllable fast time frequency synchronization device according to claim 1, characterized by: the power module inputs a 220V alternating current power supply, outputs 5V direct current voltage and 12V direct current voltage and respectively outputs 4A current and 2A current.

10. A time-frequency synchronization method using the synchronization apparatus of claim 1, comprising the steps of:

step 1, equipment self-checking initialization:

after the synchronous device is started, equipment self-checking is firstly carried out, and after the synchronous device is electrified for 1min, initial assignment is carried out on the voltage control value and each parameter variable of the constant-temperature crystal oscillator, so that the frequency of the constant-temperature crystal oscillator is adjusted to the central frequency;

step 2, coarse adjustment:

reading the pulse per second time relation and state, reading the pulse per second time relation and state again after a certain test time, calculating the numerical value of the DAC to be adjusted according to the time difference and state of the two readings and a frequency taming algorithm, writing the numerical value into a DAC data register, and performing coarse adjustment operation again after the constant temperature crystal oscillator frequency is adjusted for stabilizing time until reaching a locking threshold and entering a locking state;

and step 3, locking:

the threshold of the lock state is designed to have a frequency accuracy of 1.0 x 10^-11When the time variation of the two second pulses is within one phase discrimination resolution, namely 250ps, the two second pulses enter a locking state, and after the two second pulses enter the locking state, the second pulse of the constant-temperature crystal oscillator is triggered again by the second pulse in use to generate the second pulse of the constant-temperature crystal oscillator, so that the rising edges of the two second pulses are synchronous;

step 4, fine adjustment:

after entering a locking state, stopping coarse adjustment of the constant-temperature crystal oscillator frequency, and starting large-period monitoring and adjustment of the time difference value;

the aging rate characteristic table of the constant-temperature crystal oscillator is established in advance according to the time proportion, the DAC converter control data and time analysis are carried out in a day period, the change trend and the change quantity of the voltage-controlled voltage of the constant-temperature crystal oscillator are obtained, and when the Beidou or the GPS can not be tracked, the voltage-controlled voltage data output by the DAC converter are gradually corrected.

Technical Field

The invention belongs to the technical field of time frequency synchronization, and particularly relates to a completely autonomous controllable rapid time frequency synchronization device and method in the field.

Background

The time synchronization refers to a process in which a time server acquires standard time from a time source (e.g., GNSS), and sends time information to a time synchronization client through a time distribution link to achieve time synchronization with the time source. The frequency synchronization is a process of adjusting frequency values distributed in different point frequency sources to a certain accuracy and ensuring frequency phase synchronization by a frequency comparison mode.

At present, there are NTP (Network Time Protocol) and PTP precision Time Protocol, etc., which are widely used as high-precision Time synchronization technologies, where NTP is a Time synchronization Protocol defined by RFC-1305 and is used for Time synchronization between a distributed Time server and a client. The NTP time service is based on the principle of bidirectional transmission time delay peer-to-peer, the protocol of the NTP time service comprises a timestamp of universal coordinated time (UTC), but the time stamp of the NTP is marked on an application layer and is influenced by factors such as network flow, routing and the like, and the NTP time service precision is only in millisecond order. The PTP precision time protocol is basically the same as the NTP in realization principle, the biggest difference is that the timestamp of the PTP is marked on a physical layer, and the time transmission error is reduced to the greatest extent, so that the time service precision can reach microsecond magnitude. The NTP time service generally comprises an NTP time server and a client, the PTP time service comprises a master time server, a slave time server and a client, and the slave time server is needed for the PTP time service, so that the conventional PTP protocol cannot be directly used by a plurality of clients, and the NTP time service is also a main reason for wider application of the NTP protocol than the PTP protocol.

The conventional frequency synchronization technology mainly is an analog phase-locked loop technology, and as shown in fig. 1, the conventional frequency synchronization technology is composed of three analog circuits, namely a phase discriminator, a loop filter and a voltage-controlled oscillator, wherein the phase discriminator is used for comparing the phase difference between input and output signals and outputting a voltage error; the loop filter filters noise and interference in the output signal to form a control voltage to be supplied to the voltage-controlled oscillator; the voltage-controlled oscillator outputs the adjusted frequency according to the control voltage, and the adjusted frequency is fed back to the phase discriminator end, so that the phase discrimination, the filtering and the adjustment are repeated, and finally, when the output frequency of the voltage-controlled oscillator is firmly locked on the phase of the input signal in a fixed phase relation, the phase locking is finished. In recent years, with rapid development of scientific technology and continuous improvement of automation degree, a digital phase-locked loop technology is widely applied, the working principle and the locking process of the digital phase-locked loop technology are approximately the same as those of an analog phase-locked loop, but the digital technology is adopted, so that the precision and the stability of frequency synchronization are greatly improved, and the digital phase-locked loop technology becomes a preferred technical approach for engineering application in the field of frequency synchronization.

With the continuous development of new technologies and new services in various fields and the continuous friction and upgrading of the international political and military situation, the time-frequency field puts higher requirements on the time-frequency synchronizing device: firstly, the control is completely independent and controllable; secondly, fast capture locking; thirdly, high frequency accuracy and stability; fourthly, the network time service performance is excellent, and the user capacity is large; fifthly, the temperature range is wide and the reliability is high.

Disclosure of Invention

The invention aims to solve the technical problem of providing a fully autonomous controllable rapid time frequency synchronization device and a method, which can play an extremely important role in the fields of military affairs, communication, electric power, finance and the like as a frequency reference source and a time service standard.

The invention adopts the following technical scheme:

the improvement of a fully autonomous controllable fast time frequency synchronization device is as follows: the system comprises a timing module, a main control module, a distribution module, a display module and a power supply module; the time system module comprises a time service circuit unit, a control circuit unit, a clock circuit unit and a power circuit unit, wherein the time service circuit unit comprises a GPS and Beidou dual-mode receiving module, the clock circuit unit comprises a constant-temperature crystal oscillator and a digital-to-analog converter electrically connected with the constant-temperature crystal oscillator, the control circuit unit is an FPGA, external reference 1PPS signals output by the GPS and Beidou dual-mode receiving module and 1PPS signals output by the constant-temperature crystal oscillator are input into the FPGA, the FPGA carries out TDC time difference measurement on the two 1PPS signals to obtain time difference data, the measured time difference data are filtered to finally obtain adjusting voltage and provide the adjusting voltage for the digital-to-analog converter, in addition, the FPGA also outputs 5 paths of second pulse signals, and the power circuit unit supplies power to each circuit unit in the time system module; the master control module is electrically connected with the GPS and Beidou dual-mode receiving module, the constant-temperature crystal oscillator, the FPGA and the display module, NTP time service and serial port time service are output, the distribution module is electrically connected with the constant-temperature crystal oscillator and outputs 5 road pilot frequencies, and the power supply module supplies power for all modules in the synchronizing device.

Furthermore, the time service circuit unit also comprises a time system antenna electrically connected with the GPS and Beidou dual-mode receiving module.

Further, the clock circuit unit further comprises a crystal oscillator calibration circuit.

Furthermore, the constant temperature crystal oscillator divides the frequency of the 1PPS signal by the frequency signal of 10 MHz.

Furthermore, when no external reference 1PPS signal exists, the FPGA automatically adjusts and controls the constant temperature crystal oscillator according to the constant temperature crystal oscillator aging curve and the frequency deviation of the oscillator.

Furthermore, the FPGA utilizes a fast carry chain to construct the TDC, the time difference measurement resolution is 250ps, and a digital loop Kalman filter of the FPGA carries out filtering.

Furthermore, the main control module is an embedded control module based on ARM.

Furthermore, a 10MHz crystal filter is added at the clock input end of the distribution module.

Further, the power module inputs 220V alternating current power supply, outputs 5V direct current voltage and 12V direct current voltage, and outputs 4A current and 2A current respectively.

The improvement of a time frequency synchronization method using the synchronization device is that the method comprises the following steps:

step 1, equipment self-checking initialization:

after the synchronous device is started, equipment self-checking is firstly carried out, and after the synchronous device is electrified for 1min, initial assignment is carried out on the voltage control value and each parameter variable of the constant-temperature crystal oscillator, so that the frequency of the constant-temperature crystal oscillator is adjusted to the central frequency;

step 2, coarse adjustment:

reading the pulse per second time relation and state, reading the pulse per second time relation and state again after a certain test time, calculating the numerical value of the DAC to be adjusted according to the time difference and state of the two readings and a frequency taming algorithm, writing the numerical value into a DAC data register, and performing coarse adjustment operation again after the constant temperature crystal oscillator frequency is adjusted for stabilizing time until reaching a locking threshold and entering a locking state;

and step 3, locking:

the threshold of the lock state is designed to have a frequency accuracy of 1.0 x 10^-11When the time variation of the two second pulses is within one phase discrimination resolution, namely 250ps, the two second pulses enter a locking state, and after the two second pulses enter the locking state, the second pulse of the constant-temperature crystal oscillator is triggered again by the second pulse in use to generate the second pulse of the constant-temperature crystal oscillator, so that the rising edges of the two second pulses are synchronous;

step 4, fine adjustment:

after entering a locking state, stopping coarse adjustment of the constant-temperature crystal oscillator frequency, and starting large-period monitoring and adjustment of the time difference value;

the aging rate characteristic table of the constant-temperature crystal oscillator is established in advance according to the time proportion, the DAC converter control data and time analysis are carried out in a day period, the change trend and the change quantity of the voltage-controlled voltage of the constant-temperature crystal oscillator are obtained, and when the Beidou or the GPS can not be tracked, the voltage-controlled voltage data output by the DAC converter are gradually corrected.

The invention has the beneficial effects that:

the synchronizer disclosed by the invention provides powerful support for time frequency synchronization of multiple systems, multiple sites and multiple devices, has huge application potential in the fields of electrical engineering, industrial automation, intelligent control and the like, and has the following advantages compared with the traditional synchronizer:

(1) completely autonomous and controllable: using 100% nationwide production of electronic components; (2) the capture locking is quick: the satellite acquisition time is less than 1 minute, and the locking time is smallAt 5 minutes; (3) the frequency accuracy is high: can reach 1.0 multiplied by 10^-11(ii) a (4) The frequency stability is high: is superior to 5 × 10e^-12A/day; (5) NTP time service precision is high: less than 10 ms; (6) the time source modes are multiple: the method supports a single Beidou, a single GPS and a combined mode, and supports a holding mode; (7) the time service capacity is large: 5000 times/second. (8) The operation is simple, the human-computer interface is good, and the BIT alarm function is realized; (9) the equipment amount is less, the cost is low, and the reliability is high.

The synchronization method disclosed by the invention is matched with the synchronization device, and has high frequency accuracy and stability.

Drawings

FIG. 1 is a functional block diagram of an analog phase locked loop;

fig. 2 is a schematic block diagram of a synchronization apparatus disclosed in embodiment 1 of the present invention;

FIG. 3 is a schematic block diagram of a timing module in the synchronization apparatus disclosed in embodiment 1 of the present invention;

FIG. 4 is a schematic flow chart of a synchronization method (frequency synchronization discipline) disclosed in embodiment 1 of the present invention;

FIG. 5 is a second pulse precedence graph.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the embodiment 1, the embodiment discloses a completely autonomous controllable fast time frequency synchronization device, which adopts a method of domesticating a constant temperature crystal oscillator by Beidou or GPS, corrects the long-term stability of the constant temperature crystal oscillator in real time through a digital phase-locked loop technology, and simultaneously filters out the random phase jitter of the Beidou or GPS, thereby finally realizing the perfect combination of the long-term stability of the Beidou or GPS and the short-term stability of the constant temperature crystal oscillator. The main function of the synchronizer is to provide accurate UTC time and frequency reference for other equipment, and finally realize the time and frequency synchronization of multiple systems, multiple sites and multiple equipment. The synchronizer adopts a digital phase-locked loop disciplined technical scheme, and the principle is as shown in figure 2, and the synchronizer comprises a time system module, a main control module, a distribution module, a display module and a power supply module.

The timing module is a core module of the synchronizer and mainly comprises a timing circuit unit, a control circuit unit, a clock circuit unit, a power circuit unit and the like, as shown in fig. 3, wherein the timing circuit unit comprises a GPS and Beidou dual-mode receiving module, a timing antenna, a peripheral circuit and the like which are electrically connected with the GPS and Beidou dual-mode receiving module, and the GPS and Beidou dual-mode receiving module receives Beidou or GPS satellite signals and outputs external reference 1PPS signals; the clock circuit unit comprises a constant-temperature crystal oscillator and a digital-to-analog converter electrically connected with the constant-temperature crystal oscillator, the constant-temperature crystal oscillator divides a frequency into 1PPS signals through 10MHz frequency signals, and the clock circuit unit also comprises a crystal oscillator calibration circuit used for calibrating the constant-temperature crystal oscillator according to second pulses of the GPS and Beidou dual-mode receiving module; the control circuit unit is an FPGA and mainly has the functions of time system information analysis, TDC time difference measurement, data filtering, time sequence generation, communication with the main control module and the like. The external reference 1PPS signal and the 1PPS signal output by the constant temperature crystal oscillator are input into an FPGA, the FPGA carries out TDC time difference measurement (namely a digital phase discriminator) on the two 1PPS signals to obtain time difference data, then the measured time difference data is filtered by a frequency discipline algorithm (namely a digital loop filter), finally, an adjusting voltage is obtained by calculation and is supplied to the constant temperature crystal oscillator (namely a voltage-controlled oscillator) through a digital-to-analog converter, and the constant temperature crystal oscillator 1PPS signal and the external reference 1PPS signal are synchronized through discipline of a discipline loop. In addition, the FPGA also outputs 5 paths of second pulse signals; the power supply circuit unit supplies power to each circuit unit in the timing system module.

The timing module is responsible for completing functions of Beidou and GPS tracking, outputting clock signals and pulse per second signals and the like. Time interval measurement is carried out on a system 1PPS signal and a constant temperature crystal oscillator frequency division 1PPS signal by utilizing a fast carry chain to construct a Time Data Converter (TDC) in a time system module FPGA, the time difference measurement resolution is 250ps, and then the time difference value is sent to an FPGA digital loop filter for data filtering, so that the influence of 1PPS random jitter of the Beidou or GPS on a tame system is reduced. In view of the fact that Kalman filtering has a good noise filtering effect, the digital loop filtering algorithm of the present embodiment adopts a Kalman filter to improve the performance of the system.

The main control module is electrically connected with the GPS and Beidou dual-mode receiving module, the constant-temperature crystal oscillator, the FPGA and the display module and outputs NTP time service and serial port time service.

The main control module adopts an embedded control module based on ARM, and the CPU uses an i.MX6 (Cortex A9 architecture) four-core processor of Freescale and has a dominant frequency of 1 GHz. The memory 1GHz DDR3, the local storage 4GB eMMC, runs the Linux operating system. The main functions of the main control module comprise: receiving and analyzing an external command, and supporting remote control and state query; receiving and reporting local time information and state information; NTP time service function; a network monitoring function; implementing a filtering algorithm; and establishing an OCXO aging rate characteristic table and the like.

NTP (Network Time Protocol) is a Time synchronization Protocol defined by RFC-1305, and is used to perform Time synchronization between a distributed Time server and a client.

The method for realizing the NTP time service function of the synchronizer is realized by establishing an NTP server in a main control module, taking GPS or Beidou as a time reference and running bottom layer service programs such as GPSD, PPS, NTPD and the like. The GPS and Beidou dual-mode receiving module provides NMEA0183 sentences and 1PPS signals output by the serial port, and the GPSD service program receives and continuously analyzes the NMEA0183 sentences transmitted by the GPS and Beidou dual-mode receiving module. Since it takes a long time to parse the statements, and the running time is easily preempted by other programs, delay and jitter are generated, and at this time, the PPS service program directly triggers the interrupt of the CPU using the 1PPS signal, so that the operating system processes the statements at a high priority without being influenced by other programs, and the generation of delay and jitter is greatly reduced, so that extremely accurate time information can be acquired by the GPSD and the PPS underlying service program. And finally, carrying out network time service by using an NTPD service program, wherein the NTPD is an uninterrupted Daemon process of an operating system, and is used for correcting the time between a local system and an Internet standard clock source, and finally realizing the NTP network time service process.

The distribution module is electrically connected with the constant temperature crystal oscillator and outputs 5 road frequencies. The synchronous device distribution module mainly distributes the tamed local standard frequency and 1PPS signals into 5 paths of output respectively and meets the system requirements. In order to further optimize the signal quality of the output frequency of the synchronous device, a 10MHz crystal filter is added at the clock input end of the distribution module, so that the near-end spectrum purity of the output frequency can be greatly improved.

The display module is mainly used for setting the local control parameters and displaying the state of the synchronizer, and is designed to adopt a 3.5-inch capacitive industrial control touch screen DMT32240M035-03W produced by the company Divinkyu, Hunan; the power module has the main functions of providing power for each module of the synchronizer, the input of the power module is 220V alternating current power supply, AC/DC conversion is carried out through the power module, the power module adopts ZRY series linear power module ZRY50-220E0512 of Shanghai Bingzhui allowing electronic technology Limited company, the output voltage is 12V, and the output current is 2A; the output voltage is 5V and the output current is 4A.

When the input reference signal is unavailable, the synchronization device automatically switches to a holding mode, automatically adjusts and controls the constant-temperature crystal oscillator according to the running characteristics of the constant-temperature crystal oscillator, such as the aging curve, the frequency deviation of the oscillator and the like, and continues to keep high-precision time and frequency signal output.

This synchronizer exports 5 way frequency signal, 5 way 1PPS signals, 1 way NTP time service information, 1 way serial ports time information, adopts national electronic components, integrates, modularization, miniaturized design, and job stabilization is reliable, and structural design considers the shock resistance, can be used to shipborne and on-vehicle, also can regard as the fixed station to use.

One of the main innovation points of the synchronizer is that 100% nationwide electronic components are adopted for development and design, and the synchronizer has completely autonomous controllable capability, and has special positive significance under the large background of technical barriers in the field of international semiconductors, towering, particularly the chip struggle in China and America. The main core electronic components of the synchronization device have the following use conditions: constant temperature crystal oscillator: HJ180 Beijing Taiford electronic technologies, Inc.; FPGA: JFM7K325T Shanghai Compound denier microelectronics group, Inc.; GPS and big dipper bimodulus receiving module: STAR-OEM-4050 Beijing Zhongxing Hengtong technology Limited, the module uses 100% domestic electronic components, supports the ability of receiving Beidou No. three; an amplifier: HE315 thirteenth institute of electrical science and technology group, china; serial port chip: SM3232 Shenzhen City microelectronics shares, Inc.; a power supply chip: SM74401 Shenzhen City microelectronics shares, Inc.

The embodiment also discloses a time frequency synchronization method (frequency synchronization taming), which uses the above synchronization apparatus, as shown in fig. 4, and includes the following steps:

step 1, equipment self-checking initialization:

the method comprises the following steps that equipment self-checking is firstly carried out after a synchronous device is started, because the temperature of a constant-temperature crystal oscillator is not stable due to initial electrification, the output frequency accuracy and frequency temperature deviation of the constant-temperature crystal oscillator are large, if the constant-temperature crystal oscillator is not actually regulated and controlled at the moment, the constant-temperature control of the constant-temperature crystal oscillator basically reaches a normal state after the constant-temperature crystal oscillator is electrified for 1min, the output frequency of the crystal oscillator tends to be stable, initial assignment is immediately carried out on a voltage control value and various parameter variables of the constant-temperature crystal oscillator, and the frequency of the constant-temperature crystal oscillator can be adjusted to the central frequency as soon as possible;

step 2, coarse adjustment:

the purpose of coarse adjustment is to quickly adjust the constant-temperature crystal oscillator so that the second signal output by the constant-temperature crystal oscillator is quickly synchronous with the second signal of the time system. When the self-checking is initialized, the constant temperature crystal oscillator second pulse is generated by triggering the rising edge of the time-sharing second pulse signal, so the difference between the leading edges of the first two second signals is not large, but the constant temperature crystal oscillator second pulse signal can drift relative to the time-sharing second pulse signal because the constant temperature crystal oscillator frequency is not completely accurate compared with the time-sharing frequency. The synchronous device takes the constant-temperature crystal oscillator second pulse signal as a reference, and when the constant-temperature crystal oscillator second pulse is in front of a time axis of the time system second pulse, the time system second pulse is defined as an advance; and when the second pulse of the constant temperature crystal oscillator is behind the time axis of the second pulse of the time system, the hysteresis is defined. The pulse over pulse second relationship is shown in figure 5.

The modulation process of coarse tuning is to read the time relation and state of the second pulse at the beginning of adjustment, namely, to read the time difference and the lead-lag state of the second pulse, then to read the time relation and state of the second pulse again after a certain test time, to calculate the value of DAC to be adjusted according to the frequency taming algorithm of the synchronizer according to the time difference and state read twice, to write into the data register of DAC, then to perform coarse tuning operation again after the frequency of the constant temperature crystal oscillator is adjusted for a stable time until reaching the locking threshold, and to enter the locking state.

And step 3, locking:

the threshold of the lock state is designed to have a frequency accuracy of 1.0 x 10^-11When the two-second pulse time variation is within one phase discrimination resolution, i.e. 250ps, the synchronization device enters a locked state. At the moment, the systematic pulse per second and the constant-temperature crystal oscillator pulse per second are basically synchronous, and the relative drift amount is small, but in the phase discrimination process in the early stage, the two pulse per second continuously drift relatively, so that the rising edge time difference of the two pulse per second needs to be eliminated after the phase discrimination enters a locking state. When the design is in a locking state, the system second pulse is triggered again to generate the constant-temperature crystal oscillator second pulse when in use, so that the rising edges of the two second pulses are synchronous, and the strict synchronization of the clock frequency and the phase is realized.

Step 4, fine adjustment:

and the synchronizer starts fine adjustment operation after entering a locking state, and the fine adjustment aims at continuously tracking the external reference system and further improving the frequency accuracy of the system. After the synchronizer enters a locking state, the coarse adjustment of the constant-temperature crystal oscillator frequency is stopped, the large-period monitoring and adjustment of the time difference value are started, and the frequency accuracy index of the synchronizer is gradually improved along with the lapse of the operation time.

The frequency synchronization taming process cannot be executed due to the fact that the GPS and Beidou dual-mode receiving module is invalid occasionally, and accordingly the output frequency of the constant-temperature crystal oscillator cannot track the Beidou or the GPS. When the problem occurs, the device enters a 'holding' state, an aging rate characteristic table of the constant-temperature crystal oscillator is established in advance according to a time proportion, the DAC converter control data/time analysis is carried out by taking a day as a period, the change trend and the change quantity of the voltage-controlled voltage of the constant-temperature crystal oscillator can be obtained simply and quickly, then the voltage-controlled voltage data output by the DAC converter are gradually corrected in the working state, and the purpose that the device keeps certain synchronization capacity is achieved.