阅读说明：本技术 具有重叠范围的命令的并行重叠管理 (Parallel overlap management of commands with overlapping ranges ) 是由 C.帕斯夸里 R.N.德格林 A.莫汉 S.R.纳达库迪蒂 于 2021-03-02 设计创作，主要内容包括：本发明公开了一种存储设备,其包括：用于存储从主机设备接收的主机数据的一个或多个逻辑块,所述逻辑块具有逻辑块地址(LBA)；LBA范围表,所述LBA范围表用于存储与通过存储接口从所述主机设备接收的一个或多个命令相关联的一个或多个LBA范围；以及重叠检查电路,所述重叠检查电路用于将与活动请求相关联的LBA范围和与所述一个或多个命令相关联的一个或多个LBA范围进行比较,并且确定与所述活动请求相关联的LBA范围和与所述一个或多个命令相关联的一个或多个LBA范围中的任一者之间的重叠。(The invention discloses a storage device, which comprises: one or more logical blocks for storing host data received from a host device, the logical blocks having Logical Block Addresses (LBAs); an LBA range table to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and overlap checking circuitry to compare an LBA range associated with an active request to one or more LBA ranges associated with the one or more commands and determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands.)

1. A storage device, comprising:

one or more logical blocks configured to store host data received from a host device, the logical blocks having logical block addresses, LBAs;

an LBA range table configured to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and

overlap checking circuitry configured to compare an LBA range associated with an active request to one or more LBA ranges associated with the one or more commands, and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands.

2. The storage device of claim 1, wherein the overlap checking circuitry is configured to prevent execution of a command associated with the active request in response to determining that at least one of an LBA range associated with the active request and one or more LBA ranges associated with the one or more commands overlap; and in response to determining that any of the LBA ranges associated with the active request and the one or more LBA ranges associated with the one or more commands do not overlap, allowing execution of the command associated with the active request.

3. The storage device of claim 2, wherein the one or more commands correspond to pending commands that are blocked by the overlap check circuitry by having overlapping LBA ranges or correspond to pending commands that are executing.

4. The storage device of claim 1, wherein the active request corresponds to an incoming command received from the host device over the storage interface, and the LBA range associated with the active request comprises disjoint LBA ranges of the incoming command.

5. The storage device of claim 4, wherein the overlap check circuitry is configured to block execution of the incoming command for at least a first LBA range of the disjoint LBAs ranges and allow execution of the incoming command for at least a second LBA range of the disjoint LBAs ranges for the same incoming command.

6. The storage device of claim 1, wherein the overlap checking circuitry comprises one or more comparators configured to compare an LBA range associated with the active request to one or more LBA ranges associated with the one or more commands, and each of the comparators is configured to compare an LBA range associated with the active request to a different range of the one or more LBA ranges associated with the one or more commands.

7. The storage device of claim 1, wherein the overlap check circuitry is configured to maintain an execution order sequence of commands having overlapping LBA ranges.

8. The storage device of claim 7, wherein the overlap check circuitry is configured to set an overlap count value for the LBA range associated with the active request in response to determining that at least one of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands overlap, and the overlap count value corresponds to a number of overlaps between the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands.

9. The storage device of claim 8, wherein the overlap check circuit is configured to decrease the overlap count value in response to completion of execution of one of the one or more commands having an LBA range that overlaps an LBA range associated with the active request, and to allow execution of the LBA range associated with the active request in response to the overlap count value decreasing to a threshold value.

10. The storage device of claim 1, wherein the LBA range associated with the active request is registered to the LBA range table, and the overlap check circuitry is configured to retrieve the LBA range associated with the active request from the LBA range table.

11. A method for checking for overlap in logical block addresses, LBAs, associated with commands issued by a host device to a storage device, the method comprising:

storing, by an LBA range table, one or more LBA ranges associated with one or more commands received from the host device over a storage interface;

comparing, by the overlap checking circuitry of the storage device, the LBA range associated with the active request to one or more LBA ranges associated with the one or more commands; and

determining, by the overlap check circuitry, an overlap between an LBA range associated with the active request and any of one or more LBA ranges associated with the one or more commands.

12. The method of claim 11, further comprising:

in response to determining that at least one of the LBA ranges associated with the active request and the one or more LBA ranges associated with the one or more commands overlap, preventing, by the overlap check circuitry, execution of the command associated with the active request; and

in response to determining that any of the LBA ranges associated with the active request and the one or more LBA ranges associated with the one or more commands do not overlap, allowing, by the overlap check circuitry, execution of the command associated with the active request.

13. The method of claim 12, wherein the one or more commands correspond to pending commands that are blocked by the overlap check circuitry by having overlapping LBA ranges or correspond to pending commands that are executing.

14. The method of claim 11, wherein the active request corresponds to an incoming command received from the host device over the storage interface, and LBA ranges associated with the active request comprise disjoint LBA ranges of the incoming command.

15. The method of claim 14, further comprising:

preventing, by the overlap check circuitry, execution of the incoming command for at least a first LBA range of the disjoint LBAs ranges; and

allowing, by the overlap check circuit, execution of the incoming command for at least a second LBA range of the disjoint LBA ranges of the same incoming command.

16. The method of claim 11, wherein the overlay checking circuit comprises one or more comparators, and the method further comprises:

comparing, by the comparator, the LBA range associated with the active request with one or more LBA ranges associated with the one or more commands,

wherein each of the comparators compares an LBA range associated with the active request to a different range of one or more LBA ranges associated with the one or more commands.

17. The method of claim 11, further comprising:

an execution order sequence of commands with overlapping LBA ranges is maintained by the overlap check circuit.

18. The method of claim 17, wherein to maintain the execution order sequence, the method further comprises:

setting, by the overlap check circuit, an overlap count value for the LBA range associated with the active request in response to determining that at least one of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands overlap,

wherein the overlap count value corresponds to a number of overlaps between the LBA range associated with the active request and one or more LBA ranges associated with the one or more commands.

19. The method of claim 18, further comprising:

reducing, by the overlap check circuit, the overlap count value in response to completion of execution of one of the one or more commands having an LBA range that overlaps with an LBA range associated with the active request;

allowing, by the overlap check circuit, execution of the LBA range associated with the active request in response to the overlap count value decreasing to a threshold value.

20. The method of claim 11, wherein an LBA range associated with the active request is registered to the LBA range table, and the method further comprises:

retrieving, by the overlap check circuit, an LBA range associated with the active request from the LBA range table.

Technical Field

Aspects of one or more exemplary embodiments of the present disclosure relate to storage devices, and more particularly, to storage devices for managing commands with overlapping ranges.

Background

A storage system typically includes a host device and one or more storage devices. The host device may manage data stored in the storage device by transmitting various commands to the storage device to update one or more logical blocks of the storage device. For example, the host device may transmit an UNMAP command or a read GN BLOCKS command to the storage device along with one or more Logical Block Addresses (LBAs) or LBA ranges, such that the storage device reclaims (e.g., UNMAP) or changes the physical location of the logical BLOCKS (e.g., read GN BLOCKS) associated with the one or more LBAs or LBA ranges. In this case, the storage device may block other commands, such as READ and WRI TE (READ and write) commands, that have LBA or LBA ranges that overlap one or more of the UNMAP commands or READ GN BLOCKS commands, (or may similarly block READ GN BLOCKS or UNMAP commands that have overlapping LBA or LBA ranges) to maintain atomicity within the affected LBA or LBA range.

The above information disclosed in this background section is for enhancement of understanding of the background of the disclosure and, therefore, it may contain information that does not form the prior art.

Disclosure of Invention

One or more exemplary embodiments of the present disclosure are directed to a storage device including a hardware module (e.g., LOC circuitry) to check for overlap of commands having multiple disjoint LBAs or LBA ranges.

One or more example embodiments of the present disclosure relate to a storage device that includes hardware modules (e.g., LOC circuitry) to enable execution of commands having non-overlapping LBAs or LBA ranges even when one or more LBAs or LBA ranges of the same command are blocked by overlap.

According to one or more exemplary embodiments of the present disclosure, a storage device includes: one or more logical blocks configured to store host data received from a host device, the logical blocks having Logical Block Addresses (LBAs); an LBA range table configured to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and overlap checking circuitry positioned to compare an LBA range associated with an active request to one or more LBA ranges associated with the one or more commands and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands.

In one example embodiment, the overlap checking circuitry may be configured to prevent execution of a command associated with the active request in response to determining that at least one of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands overlap; and in response to determining that any of the LBA ranges associated with the active request and the one or more LBA ranges associated with the one or more commands do not overlap, allowing execution of the command associated with the active request.

In one exemplary embodiment, the one or more commands may correspond to pending commands that are blocked or in execution by the overlap check circuitry by having overlapping LBA ranges.

In one exemplary embodiment, the active request may correspond to an incoming command received from the host device over the storage interface, and the LBA ranges associated with the active request may include disjoint LBA ranges of the incoming command.

In one exemplary embodiment, the overlap check circuitry may be configured to block execution of the incoming command for at least a first LBA range of the disjoint LBA ranges and allow execution of the incoming command for at least a second LBA range of the disjoint LBA ranges of the same incoming command.

In one example embodiment, the overlap checking circuitry may include one or more comparators configured to compare the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands, and each of the comparators may be configured to compare the LBA range associated with the active request and a different range of the one or more LBA ranges associated with the one or more commands.

In one exemplary embodiment, the overlap check circuitry may be configured to maintain an execution order sequence of commands having overlapping LBA ranges.

In one example embodiment, the overlap check circuitry may be configured to set an overlap count value for the LBA range associated with the active request in response to determining that at least one of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands overlap, and the overlap count value may correspond to a number of overlaps between the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands.

In one example embodiment, the overlap check circuit may be configured to decrease the overlap count value in response to completion of execution of one of the one or more commands having an LBA range that overlaps the LBA range associated with the active request, and to allow execution of the LBA range associated with the active request in response to the overlap count value decreasing to a threshold.

In one exemplary embodiment, the LBA range associated with the active request may be registered to the LBA range table, and the overlap check circuitry may be configured to retrieve the LBA range associated with the active request from the LBA range table.

According to one or more exemplary embodiments of the present disclosure, a method for checking for overlap in Logical Block Addresses (LBAs) associated with commands issued by a host device to a storage device includes: storing, by an LBA range table, one or more LBA ranges associated with one or more commands received from the host device over a storage interface; comparing, by overlap checking circuitry of the storage device, the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands; and determining, by the overlap check circuitry, an overlap between any of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands.

In one exemplary embodiment, the method may further include: preventing, by the overlap check circuitry, execution of a command associated with the active request in response to determining that at least one of the LBA ranges associated with the active request and the one or more LBA ranges associated with the one or more commands overlap; and allowing, by the overlap check circuitry, execution of the command associated with the active request in response to determining that the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands do not overlap.

In one exemplary embodiment, the one or more commands may correspond to pending commands that are blocked or in execution by the overlap check circuitry by having overlapping LBA ranges.

In one exemplary embodiment, the active request may correspond to an incoming command received from the host device over the storage interface, and the LBA ranges associated with the active request may include disjoint LBA ranges of the incoming command.

In one exemplary embodiment, the method may further include: preventing, by the overlap check circuitry, execution of the incoming command for at least a first LBA range of the disjoint LBAs ranges; and allowing, by the overlap check circuit, execution of the incoming command for at least a second LBA range of the disjoint LBA ranges of the same incoming command.

In one exemplary embodiment, the overlay check circuit may include one or more comparators, and the method may further include: comparing, by the comparators, the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands, and each of the comparators may compare the LBA range associated with the active request and a different range of the one or more LBA ranges associated with the one or more commands.

In one exemplary embodiment, the method may further include: an execution order sequence of commands with overlapping LBA ranges is maintained by the overlap check circuit.

In one exemplary embodiment, in order to maintain the execution order sequence, the method may further include: setting, by the overlap check circuitry, an overlap count value for the LBA range associated with the active request in response to determining that at least one of the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands overlap, and the overlap count value may correspond to a number of overlaps between the LBA range associated with the active request and the one or more LBA ranges associated with the one or more commands.

In one exemplary embodiment, the method may further include: reducing, by the overlap check circuitry, the overlap count value in response to completion of execution of one of the one or more commands having an LBA range that overlaps the LBA range associated with the active request; allowing, by the overlap check circuit, execution of the LBA range associated with the active request in response to the overlap count value decreasing to a threshold value.

In one exemplary embodiment, the LBA range associated with the active request may be registered to the LBA range table, and the method may further include: retrieving, by the overlap check circuit, the LBA range associated with the active request from the LBA range table.

Drawings

The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the attached drawings.

Fig. 1 is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

Fig. 2 is a block diagram illustrating a LOC circuit of a memory device according to one or more exemplary embodiments of the present disclosure.

Fig. 3 illustrates an example format of an LBA range table in accordance with one or more example embodiments of the present disclosure.

Fig. 4 is a block diagram of an inspection circuit of the LOC circuit according to one or more exemplary embodiments of the present disclosure.

Fig. 5 is a schematic circuit diagram illustrating a detection circuit of an inspection circuit according to one or more exemplary embodiments of the present disclosure.

Fig. 6 is a schematic circuit diagram illustrating a counting circuit of an inspection circuit according to one or more exemplary embodiments of the present disclosure.

FIG. 7 is a flow diagram of an illustrative example of blocking commands with overlapping ranges in accordance with one or more illustrative embodiments of the present disclosure.

Detailed Description

Exemplary embodiments will be described in more detail below with reference to the drawings, in which like reference numerals refer to like elements throughout. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a complete understanding of the various aspects and features of the disclosure may not be described by those of ordinary skill in the art. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and written description, and thus the description thereof may not be repeated.

According to one or more exemplary embodiments of the present disclosure, a host device (e.g., a host computer) may issue a command to a storage device to request an update to one or more logical blocks of the storage device that store host data. In this case, each command may provide the storage device with a list of one or more Logical Block Addresses (LBAs) or LBA ranges associated with the command. For example, an UNMAP command (e.g., a SCSI UNMAP command) may provide the storage device with a list of LBAs, and a READSI GN BLOCKS command (e.g., an SCSI REASSI GN BLOCKS command) may provide the storage device with a list of LBA ranges. The storage device may block other commands, such as READ and WRI TE commands, having LBA overlap with the READ GN BLOCKS command or UNMAP command, (and/or may similarly block READ GN BLOCKS or UNMAP commands having overlapping LBA or LBA ranges) to maintain atomicity within the affected LBA or LBA range. However, this may present performance problems.

For example, the comparing storage device may sequentially check for overlap in LBAs or LBA ranges so that the comparing storage device may process one LBA or LBA range at a time. In this case, however, even if the subsequent commands do not have overlapping LBAs or LBA ranges, the compare memory device may block all subsequent commands until the commands with overlapping ranges are resolved (e.g., processed and/or executed). This may reduce the performance of the storage device because rather than allowing commands with non-overlapping LBAs or LBA ranges to execute (e.g., execute immediately), these commands may be blocked until any previous commands with overlapping LBAs or LBA ranges have been resolved and executed. Similarly, for commands having multiple disjoint LBAs or LBA ranges (e.g., a single command), the comparing storage device may sequentially check for overlap in LBAs or LBA ranges such that the overlap of a first LBA or LBA range of the multiple disjoint LBAs or LBA ranges may prevent the comparing storage device from processing a second LBA or LBA range of the multiple disjoint LBAs or LBA ranges even if no overlap affects the second LBA or LBA range.

According to one or more example embodiments of the present disclosure, a storage device may include a hardware module (e.g., LOC circuitry) to support overlapping checking of multiple LBAs or LBA ranges simultaneously (e.g., simultaneously or at the same time). In this case, the hardware module may block execution of commands with overlapping LBAs or LBA ranges while allowing execution of commands (e.g., subsequent commands) without overlapping LBAs or LBA ranges even if one or more previous commands were blocked by having overlapping LBAs or LBA ranges. Accordingly, the performance of the storage device may be improved.

According to one or more example embodiments of the present disclosure, a hardware module (e.g., LOC circuitry) may simultaneously check for overlap in multiple disjoint LBAs or LBA ranges for a single command. For example, the LBA or LBA range of a single command may be divided into multiple entries of the LBA range table, which the hardware module may use to check for overlaps with those of pending commands (e.g., commands that are executing or waiting to be executed). In some embodiments, any LBAs or LBA ranges of commands that overlap with one or more of those of the pending commands may be blocked, while those of the same commands that do not overlap with those of the pending commands may be allowed to execute (e.g., may execute immediately or may continue execution). In some embodiments, any received commands that overlap with the LBA or LBA range of the in-progress command may be automatically blocked until the range is fully processed. Thus, performance can be improved.

According to one or more exemplary embodiments of the present disclosure, a hardware module (e.g., a LOC circuit) may offload overlap checking from firmware or software. For example, using firmware or software (e.g., a processor executing instructions) to check for overlap in multiple disjoint LBAs or LBA ranges may introduce delay (e.g., due to processing time), and/or may reduce throughput (e.g., overall throughput) of the storage device (e.g., by utilizing limited processing resources of the storage device). Thus, by offloading the overlap check to the hardware module, latency may be reduced, and/or throughput of the storage device 104 may be improved.

Fig. 1 is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

In brief overview, in accordance with one or more embodiments of the present disclosure, a storage system 100 may include a host device (e.g., host computer) 102 and a storage device 104. The host device 102 may issue commands to the storage device 104 such that the storage device 104 manages the host data stored therein according to the commands. For example, the host device 102 may be communicatively connected to the storage device 104 (e.g., through the storage interface 110) and may issue various commands (e.g., READ, WRITE, UNMAP, READ GN BLOCK, TRIM, etc.) to the storage device 104 as well as one or more LBAs or LBA ranges associated with the respective commands. The storage device 104 may store, update, and/or otherwise manage host data in one or more logical blocks associated with one or more LBAs or LBA ranges. Once the command is executed, the storage device 104 may transmit a response to the host device 102 indicating that the command has completed successfully.

In one or more exemplary embodiments, rather than using firmware or software (e.g., a processor executing instructions, such as storage controller 114) to perform the overlap check, storage device 104 may include a hardware module (e.g., LOC circuitry 122) to check for overlap between one or more LBAs or LBA ranges associated with an incoming command and those of the pending command. For example, in some embodiments, LBAs or LBA ranges associated with one or more pending commands (e.g., one or more commands in progress that are executing or waiting to execute) may be divided into various entries of a table (e.g., LBA range table 120). In this case, the hardware module may compare the one or more LBAs or LBA ranges associated with the incoming command to those in the table to determine whether the one or more LBAs or LBA ranges associated with the incoming command overlap with those in the table. An incoming command may be blocked if one or more LBAs or LBA ranges associated with the incoming command overlap those in the table. On the other hand, if one or more LBAs or LBA ranges associated with the incoming command do not overlap with any of those in the table, the incoming command may be executed (e.g., may be executed immediately or may continue to be executed).

In one or more exemplary embodiments, a hardware module (e.g., LOC circuitry 122) may check multiple disjoint LBAs or LBA ranges associated with a command (e.g., a single command) simultaneously (e.g., simultaneously or at the same time) and may enable execution of the command for non-overlapping LBAs or LBA ranges while preventing execution of the same command for overlapping LBAs or LBA ranges. Thus, by allowing a command to be executed for non-overlapping LBAs or LBA ranges while preventing the same command from being executed for overlapping LBAs or LBA ranges, the execution time of the command may be reduced or minimized.

In more detail, referring to fig. 1, host device 102 may include a host processor 106 and a host memory 108. Host processor 106 may be a general purpose processor, such as a Central Processing Unit (CPU) core of host device 102. Host memory 108 may be considered high performance main memory (e.g., main memory) of host device 102. For example, in some embodiments, host memory 108 may include (or may be) volatile memory, such as Dynamic Random Access Memory (DRAM), for example. However, the present disclosure is not so limited, and as is known to those skilled in the art, host memory 108 may include (or may be) any suitable high-performance main memory (e.g., main memory) replacement for host device 102. For example, in other embodiments, host memory 108 may be a relatively high performance non-volatile memory, such as NAND flash memory, Phase Change Memory (PCM), resistive RAM, spin transfer torque RAM (sttram), any suitable memory based on PCM technology, memristor technology, and/or resistive random access memory (ReRAM), and may include, for example, an chalcogenide, or the like.

The storage device 104 can be considered secondary storage that can persistently store data accessible by the host device 102. In this case, the storage device 104 may include (or may be) relatively slow memory when compared to the high performance memory of the host memory 108. For example, in some embodiments, the storage device 104 may be a secondary memory of the host device 102, such as a Solid State Drive (SSD), for example. However, the present disclosure is not so limited, and in other embodiments, the storage device 104 may include (or may be) any suitable storage device, such as, for example, a magnetic storage device (e.g., a Hard Disk Drive (HDD), etc.), an optical storage device (e.g., a blu-ray disc drive, a Compact Disc (CD) drive, a Digital Versatile Disc (DVD) drive, etc.), other kinds of flash memory devices (e.g., a USB flash drive, etc.), and so forth. In various embodiments, the storage device 104 may conform to a large form factor standard (e.g., a 3.5 inch hard drive form factor), a small form factor standard (e.g., a 2.5 inch hard drive form factor), an m.2 form factor, an e1.s form factor, and the like. In other embodiments, the storage device 104 may conform to any suitable or desired derivative of these form factors. For convenience, the storage device 104 may be described below in the context of an SSD, although the disclosure is not so limited.

The storage device 104 may be communicatively connected to the host device 102 through a storage interface 110. The storage interface 110 may facilitate communication (e.g., using connectors and protocols) between the host device 102 and the storage device 104. In some embodiments, the storage interface 110 may facilitate the exchange of storage requests and responses between the host device 102 and the storage device 104. For example, in one embodiment, the storage interface 110 (e.g., connectors and their protocols) may include (or may conform to) Small Computer System Interface (SCSI), non-volatile memory express (nvme), and the like. However, the disclosure is not so limited, and in other embodiments, the storage interface 110 (e.g., connectors and protocols thereof) may conform to other suitable storage interfaces, such as peripheral component interconnect express (pcie), remote direct memory access over ethernet (RDMA), Serial Advanced Technology Attachment (SATA), fibre channel, serial attached scsi (sas), NVMe over fiber (NVMe-af), and the like. In other embodiments, the storage interface 110 (e.g., connectors and protocols thereof) may include (or may conform to) various general-purpose interfaces, such as Ethernet, Universal Serial Bus (USB), and so forth. For convenience, the storage interface 110 may be described below in the context of a SCSI interface, although the disclosure is not so limited.

In some embodiments, storage device 104 may include a storage controller 114 and a storage memory 116. The storage controller 114 may be connected to the storage interface 110 (e.g., via the command pipeline circuitry 112) and may be responsive to input/output (I/O) requests received from the host device 102 through the storage interface 110. Memory controller 114 may provide an interface to control and provide access to and from memory 116. For example, the storage controller 114 may include at least one processing circuit embedded thereon for interfacing with the host device 102 and the storage memory 116. The processing circuitry may include, for example, digital circuitry (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.)) capable of executing data access instructions (e.g., via firmware and/or software) to provide access to and from data stored in storage memory 116 according to the data access instructions. For example, the data access instructions may include any suitable data storage and retrieval algorithm (e.g., READ/WRI TE) instructions, data management and update algorithm (e.g., UNMAP, READSI GN BLOCKS, TRIM, etc.) instructions, and the like.

Storage memory 116 may permanently store data received from host device 102. For example, the storage memory 116 may include a plurality of logic blocks 118 to store host data received from the host device 102. In one embodiment, storage memory 116 may comprise non-volatile memory, such as NAND flash memory. However, the present disclosure is not so limited, and storage memory 116 may comprise any suitable memory, depending on the type of storage device 104.

In one or more exemplary embodiments, the storage device 104 may include an LBA range table 120. The LBA range table 120 may include a plurality of separate time slots that store LBAs or LBA ranges associated with one or more commands in progress that are in progress or are waiting to be executed such that LBAs or LBA ranges in the LBA range table 120 may be compared to LBAs or LBA ranges of incoming commands. For example, in some embodiments, the LBA range table 120 may be stored in a buffer or in a volatile memory (such as DRAM) of the storage device 104. However, the present disclosure is not so limited, and the LBA range table 120 may be stored in any suitable memory such that LBAs or LBA ranges in the LBA range table 120 may be retrieved and compared to those of the incoming command. For example, in another embodiment, the LBA range table 120 may be stored in the storage memory 116.

In one or more exemplary embodiments, storage device 104 can also include command pipeline circuitry 112 and LBA Overlap Checking (LOC) circuitry 122. In some embodiments, the command pipeline circuitry 112 may receive commands (e.g., command frames, commit queue entries, etc.) from the host device 102 through the storage interface 110 and may issue (e.g., may transmit) the commands (e.g., via a notification) to the storage controller 114 (or another processor using firmware or software). In this case, storage controller 114 (or another processor using firmware or software) may submit the LBA range or ranges associated with each command to LOC circuitry 122 for overlap checking. In some embodiments, the command pipeline circuitry 112 may receive commands (e.g., command frames, commit queue entries, etc.) from the host device 102 and may parse the commands (e.g., determine a command type for each command and one or more LBAs or LBA ranges associated with each command). In this case, in some embodiments, command pipeline circuitry 112 may submit one or more LBAs or LBA ranges associated with each command to LOC circuitry 122 for overlap checking. In some embodiments, each of command pipeline circuitry 112 and storage controller 114 (or another processor using firmware or software) may submit LBAs or LBA ranges to LOC circuitry 122 for overlap checking. In other embodiments, depending on the implementation or type of storage device 104, the appropriate one of command pipeline circuitry 112 and storage controller 114 (or another processor using firmware or software) may submit the LBAs or LBA ranges to LOC circuitry 122 for overlap checking. However, the present disclosure is not so limited, and depending on the type and/or implementation of the memory device 104, one of the command pipeline circuit 112 and the memory controller 114 may be omitted.

In some embodiments, LOC circuit 122 may be implemented as a hardware module (e.g., an electronic circuit) communicatively connected to memory controller 114 and/or command pipeline circuit 112, and may receive overlay check requests from memory controller 114 and/or command pipeline circuit 112. The LOC circuitry 122 may check for overlap between one or more LBAs or LBA ranges associated with the overlap check request and one or more LBAs or LBA ranges from the LBA range table 120. For example, in one embodiment, LOC circuit 122 may be implemented as an integrated circuit (I C) attached to (or mounted on) memory device 104 (e.g., it may be embedded on the same board or the same circuit board, like the circuitry of memory device 104). For example, the LOC circuit 122 may be implemented on the storage device 104 as a system on a chip (SOC) (e.g., may be attached to or mounted on a memory device). However, the present disclosure is not limited thereto. For example, in another embodiment, LOC circuit 122 may be implemented on a circuit board separate from the circuit board of memory device 104 (e.g., a printed circuit board PCB) and may be connected to memory controller 114 and/or command pipeline circuit 112.

In one or more exemplary embodiments, as discussed in detail below with reference to fig. 2-7, LOC circuitry 122 may receive requests from storage controller 114 and/or command pipeline circuitry 112 to check for overlaps in multiple LBAs or LBA ranges simultaneously (e.g., simultaneously or at the same time). For example, storage controller 114 and/or command pipeline circuitry 112 may register LBAs or LBA ranges (which may be collectively referred to hereinafter as LBA ranges) of an incoming command into respective time slots of LBA range table 120, and LOC circuitry 122 may use LBA range table 120 to simultaneously check for overlap of one or more LBA ranges in the request with those in LBA range table 120. In some embodiments, LOC circuitry 122 may block execution of any commands having LBA ranges that overlap with one or more ranges in LBA range table 120 and may allow execution of commands having LBA ranges that do not overlap with ranges in LBA range table 120. In some embodiments, LOC circuitry 122 may enable commands to be executed for non-overlapping LBA ranges while preventing the same commands from being executed for overlapping LBA ranges. Thus, the execution time of commands may be reduced or minimized, latency may be reduced, and/or throughput may be improved.

Fig. 2 is a block diagram illustrating a LOC circuit of a memory device according to one or more exemplary embodiments of the present disclosure.

In brief overview, LOC circuit 122 may be a hardware module (e.g., an electronic circuit) that is connected to memory controller 114 (e.g., as indicated by the solid-line arrows) and/or command pipeline circuit 112 (e.g., as indicated by the dashed-line arrows) such that LOC circuit 122 may receive overlay check requests from memory controller 114 and/or command pipeline circuit 112. In some embodiments, LOC circuitry 122 may select one of the overlap check requests as an active request and may fetch (e.g., may retrieve or read) one or more LBA ranges associated with the active request from LBA range table 120 into an internal table (e.g., an internal register of a flip-flop). LOC circuitry 122 may compare one or more LBA ranges associated with the active request to other LBA ranges in the internal table associated with other pending commands (e.g., commands that are in progress or waiting to be executed). LOC circuit 122 may determine the overlap between LBA ranges based on the comparison results. In some embodiments, LOC circuitry 122 may generate an overlap count that may be used to maintain an execution order sequence of commands having overlapping LBA ranges. For example, in some embodiments, the LOC circuitry 122 may include selection circuitry 202, acquisition circuitry 204, and check circuitry 206.

In more detail, referring to fig. 2, in some embodiments, the command pipeline circuit 112 may receive an incoming command (e.g., a command frame, a commit queue entry, etc.) such as an UNMAP command (e.g., a SCSI UNMAP command) or a read GN BLOCKS command (e.g., an SCSI REASSI GN BLOCKS command) from the host device 102 through the storage interface 110. The incoming command may include one or more LBA ranges associated with the command, such that storage device 104 performs the operation associated with the command on one or more logical blocks 118 corresponding to the one or more LBA ranges. In some embodiments, the command pipeline circuitry 112 may issue (e.g., may transmit) commands (e.g., via a notification) to the memory controller 114 so that the memory controller 114 may process the commands using, for example, firmware or software. In this case, storage controller 114 may update LBA range table 120 in storage memory 116 according to the command and the LBA range or ranges associated with the command. In another embodiment, the command pipeline circuitry 112 may include parsing circuitry to parse the command (e.g., to determine the type of command and the LBA range or ranges associated with the command). In this case, the command pipeline circuitry 112 may update the LBA range table 120 in the storage memory 116 according to the command and the LBA range or ranges associated with the command. In another embodiment, each of the command pipeline circuitry 112 and the storage controller 114 may update the LBA range table 120 in the storage memory 116 with LBA ranges associated with the incoming commands. In some embodiments, command pipeline circuitry 112 and/or storage controller 114 may partition a single command having multiple disjoint LBA ranges into entries of LBA range table 120.

For example, fig. 3 illustrates an example format of an LBA range table in accordance with one or more example embodiments of the present disclosure. As shown in fig. 3, LBA range table 120 may include a plurality of entries (e.g., a plurality of separate time slots), each entry corresponding to a command and an LBA range associated with the command. The LBA range table 120 may be updated by the command pipeline circuitry 112 and/or the storage controller 114 by providing the LBA range 302 of the incoming command to the LBA range table 120. For example, the LBA range 302 of the incoming command may define the starting LBA and the ending LBA of the LBA range. In another example, the LBA range 302 of the incoming command may define a starting LBA and LBA count. However, the present disclosure is not limited thereto. For example, when the LBA range includes a single LBA, the LBA range 302 may include the single LBA (e.g., instead of the start LBA and the end LBA), or the start LBA and the end LBA may include the same LBA corresponding to the single LBA. Additionally, as shown in FIG. 3, a single command (e.g., command 2) having multiple disjoint LBA ranges may be partitioned into multiple entries of the LBA range table 120 such that each disjoint LBA range of the same command has its own entry in the LBA range table 120.

Referring again to FIG. 2, in some embodiments, the command pipeline circuitry 112 and/or the memory controller 114 may transmit an overlap check request to the LOC circuitry 122. For example, the selection circuitry 202 may receive an overlap check request from the command pipeline circuitry 112 and/or the memory controller 114. Selection circuitry 202 may select an appropriate one of the overlap check requests as the active request such that the LOC circuitry checks whether one or more LBA ranges associated with the active request overlap with one or more LBA ranges loaded from LBA range table 120. For example, in some embodiments, the selection circuitry 202 may pool (pool) multiple overlapping check requests received from the command pipeline circuitry 112 and/or the memory controller 114, and may select an appropriate or desired overlapping check request from the pool according to suitable selection logic. For example, the selection circuitry 202 may select the active request from among the overlapping check requests received from the command pipeline circuitry 112 and/or the memory controller 114 according to a first-in-first-out algorithm, a last-in-first-out algorithm, a weighted round robin algorithm, a command type associated with the request, a command priority associated with the request, a priority associated with the source of the request (e.g., the memory controller 114 may be given a higher priority), a particular LBA range associated with the request, and so on. However, the present disclosure is not so limited, and in some embodiments, the selection circuit 202 may be omitted. For example, in some embodiments, LOC circuit 122 may process overlap check requests in the order in which they are received, and in this case, selection circuit 202 may be omitted.

In some embodiments, different types of commands with overlapping ranges may be processed differently depending on atomicity requirements. For example, a READ command that overlaps another READ command and a READ command that overlaps a WRI TE command may be processed differently because those commands that modify the state of a logical block may affect atomicity. In this case, for example, command pipeline circuitry 112 and/or memory controller 114 may transmit an overlap check request to LOC circuitry 122 based on (e.g., depending on) the type of command, and/or selection circuitry 202 may select an active request based on (e.g., depending on) the type of command. However, the present disclosure is not limited thereto.

In certain embodiments, the LOC circuitry 122 may retrieve (e.g., read or retrieve) the LBA range associated with the active request from the LBA range table 120, and may load the LBA range into an internal table (e.g., internal registers of a flip-flop, etc.) of the LOC circuitry 122 for comparison with one or more LBA ranges of one or more pending commands. For example, in some embodiments, the active request may include an index, pointer, or the like into the LBA range table 120 of the storage memory 116 that specifies the LBA range associated with the active request to be obtained. In some embodiments, the fetch circuitry 204 may include an internal table to store one or more LBA ranges of one or more pending commands, which may be compared to LBA ranges associated with the active request.

In some embodiments, the LBA range of the pending command may correspond to a previously active request that has been checked for overlap and, therefore, may have been previously loaded into the internal table of the fetch circuitry 204. In this case, when execution of a pending command of the pending commands is complete, the pending command may be cleared (e.g., removed or deleted) from the internal table such that the LBA range of the pending command is not compared to the subsequent active request and used to block the subsequent active request. However, the disclosure is not so limited, and in another embodiment, the acquisition circuitry 204 may acquire (e.g., may read or may retrieve) LBA ranges associated with the active request from the LBA range table 120 and LBA ranges of pending commands for comparison each time a new active request is received. In this case, when execution of a pending command of the pending commands is complete, the storage controller 114 and/or the command pipeline circuitry 112 may clear (e.g., remove or delete) the pending command from the LBA range table 120 so that its LBA range is not fetched and compared to the LBA range of the active request under consideration.

In some embodiments, as discussed in more detail below with reference to fig. 4, LOC circuitry 122 may compare LBA ranges associated with the active request to one or more LBA ranges of the pending commands to determine whether there is overlap therebetween. For example, the check circuitry 206 may compare the LBA range of the active request to each LBA range of the pending command (e.g., retrieved from the LBA range table 120) to determine whether the LBA range of the active request overlaps any LBA ranges in the pending command. In some embodiments, if the LBA range of the active request does not overlap any LBA ranges of pending commands, a notification may be provided to the initiator of the overlap check request associated with the active request (e.g., to the memory controller 114 and/or the command pipeline circuitry 112) so that the command associated with the active request may be executed (e.g., immediately executed or continued to be executed). In such a case, in some embodiments, the initiator (e.g., memory controller 114 and/or command pipeline circuitry 112) may provide a response to host device 102 indicating that the command has been successfully executed. On the other hand, if the LBA range of the active request overlaps with any LBA range of pending commands, no notification may be provided to the initiator so that commands associated with the active request may be blocked. In this case, in some embodiments, the check circuitry 206 may generate an overlap count to determine the sequential sequence of execution of the commands associated with the active request.

Fig. 4 is a block diagram of an inspection circuit of the LOC circuit according to one or more exemplary embodiments of the present disclosure.

In brief overview, the fetch circuitry 204 may receive an activity request (e.g., via the selection circuitry 202) corresponding to an overlap check request received from the memory controller 114 or the command pipeline circuitry 112. In some embodiments, the active request may include an index, pointer, or the like, that specifies the location of one or more LBA ranges associated with the active request in LBA range table 120. In some embodiments, the fetch circuitry 204 may fetch (e.g., may read or may retrieve) one or more LBA ranges (e.g., active ranges) associated with the active request from the LBA range table 120, and may load the one or more active ranges associated with the active request into an internal table (e.g., internal registers of a trigger, etc.). The fetch circuitry 204 may provide the check circuitry 206 with one or more active ranges associated with the active request, and LBA ranges Range 1 through Range N (where N is a natural number) associated with one or more pending commands (e.g., associated with commands that are executing, blocked, and waiting to execute), and the check circuitry 206 may check for overlap therebetween. For example, in some embodiments, the check circuitry 206 may include comparison circuitry 402, an overlap bitmap 404, detection circuitry 406, and counting circuitry 408.

In more detail, referring to fig. 4, in some embodiments, the comparison circuit 402 may include a plurality of comparators 1 to N. Each of comparators Comparator 1-Comparator N may receive an active Range (e.g., an LBA Range associated with an active request) for comparison with a corresponding one of LBA ranges Range 1-Range N associated with one or more pending commands. For example, a first Comparator Comparator 1 may compare the active Range to a first LBA Range 1 in one or more pending commands, a second Comparator Comparator2 may compare the active Range to a second LBA Range 2 in one or more pending commands, and so on, such that an Nth Comparator Comparator N may compare the active Range to an Nth (e.g., last) LBA Range N in one or more pending commands. In some embodiments, comparators 1 to Comparator N may perform comparisons at the same time (e.g., simultaneously or at the same time) as each other, although the disclosure is not so limited.

In some embodiments, each of comparators 1-N may output the comparison result, indicating whether the active Range (e.g., LBA Range of the active request) overlaps with the corresponding LBA ranges Range 1-Range N of the one or more pending commands. In some embodiments, the results of the comparisons of comparators 1 through Comparator N may be used to generate the overlay bitmap 404. For example, in one embodiment, if the active Range overlaps with the corresponding LBA ranges Range 1 through Range N of one or more pending commands, the corresponding comparators Comparator 1 through Comparator N may set the corresponding bit (0/1) in the overlap bitmap 404 to an overlap level (e.g., high level). On the other hand, if the active Range does not overlap with the corresponding LBA ranges Range 1 through Range N of the one or more pending commands, the corresponding comparators Comparator 1 through Comparator N may set the corresponding bit (0/1) in the overlap bitmap 404 to a non-overlapping level (e.g., a low level).

In some embodiments, the detection circuit 406 may detect overlap based on the comparison results of the comparison circuit 402. For example, in some embodiments, the detection circuitry 406 may output an overlap detection signal based on the overlap bitmap 404. In this case, if any bit (0/1) in the overlap bitmap 404 is set to an overlap level (e.g., high), an overlap signal (e.g., a high signal) may be output as an overlap detection signal, indicating that the active Range of the active request overlaps with at least one of the LBA ranges Range 1 through Range N of the pending command. On the other hand, if each bit (0/1) in the overlap bitmap 404 is set to a non-overlap level (e.g., low), a valid signal (e.g., a low signal) may be output as an overlap detection signal, indicating that the active Range of the active request does not overlap the LBA ranges Range 1 through Range N of pending commands.

For example, referring to fig. 5, a schematic circuit diagram illustrating detection circuit 406 is shown, according to one or more exemplary embodiments of the present disclosure. As shown in fig. 5, in some embodiments, the detection circuit 406 may include one or more logic gates. For example, the detection circuit 406 may include an OR logic gate 502. In this case, the or logic gate 502 may determine whether to set at least one bit (0/1) in the overlap bitmap 404 to an overlap level (e.g., a high level), and if the at least one bit (0/1) has the overlap level (e.g., a high level), the or logic gate 502 may output an overlap signal (e.g., a high level signal) as the overlap detection signal. On the other hand, if each bit (0/1) in the overlap bitmap 404 is set to a non-overlap level (e.g., a low level), the or logic gate 502 may output an active signal (e.g., a low level signal) as an overlap detection signal. However, the present disclosure is not limited thereto, and various modifications may be made to the detection circuit 406 in accordance with the spirit and scope of the present disclosure. For example, detection circuit 406 may include (e.g., be implemented with) various suitable hardware structures, electronic components, and/or components, such as, for example, other various suitable logic gates (e.g., nand gates, nor gates, xor gates, not gates, xor gates, etc.), various suitable switches, various suitable transistors, various suitable resistors, various suitable capacitors, etc., as will be appreciated by one of skill in the art in light of this disclosure and/or from practicing one or more embodiments of the present disclosure.

In some embodiments, the compare circuit 402 may cause a command having multiple disjoint LBA ranges to be executed even if one or more of the multiple disjoint LBA ranges are blocked. As an illustrative example, consider a command having two disjoint LBA ranges, such that the two disjoint LBA ranges do not overlap each other, and it is assumed that a first LBA range of the two disjoint LBA ranges overlaps one or more LBA ranges of a pending command, and a second LBA range of the two disjoint LBA ranges does not overlap any LBA ranges of the pending command. In this case, if the first LBA range is checked first, the first LBA range may be blocked for overlap with one or more LBA ranges of pending commands. However, when a second LBA range of the same command is subsequently checked for overlap, the second LBA range of the command may continue to execute even though the first LBA range of the same command is blocked because the second LBA range does not overlap with the first LBA range or any LBA range of a pending command. Thus, performance can be improved.

Referring again to FIG. 4, in some embodiments, the count circuit 408 may track the overlap count to maintain an execution order sequence of commands with overlapping LBA ranges. For example, as will be described in more detail below with reference to fig. 6, in some embodiments, the count circuit 408 may track a number of overlapping ranges between the active range of the active request under consideration and the LBA range of the pending command, and may generate an overlap count corresponding to the number of overlapping ranges. In this case, the overlap count may be used to determine the order in which commands corresponding to the activity request may be executed. After execution of one of the pending commands with overlapping ranges completes, the overlap count for the corresponding request may be reduced so that the execution order sequence for the corresponding request may be maintained. In this case, the command associated with the corresponding request among the pending commands having the same overlap range may be executed next when the overlap count of the corresponding request is reduced to 0.

Fig. 6 is a schematic circuit diagram illustrating a counting circuit of an inspection circuit according to one or more exemplary embodiments of the present disclosure. For convenience, the counting circuit 408 is shown for the 3-bit overlay bitmap 404 in fig. 6, but the disclosure is not limited thereto.

Referring to fig. 6, in some embodiments, the count circuit 408 for the 3-bit bitmap 404 may generate an overlapping count from a binary count of a plurality of count bits. For example, for the illustrative 3-bit overlap bitmap 404, the count circuit 408 may generate an overlap count from a first count bit (e.g., the least significant bit) S0 and a second count bit (e.g., the more significant bit or, in this illustrative 3-bit example, the most significant bit) S1. However, the present disclosure is not so limited, and one of ordinary skill in the art will appreciate that the count circuit 408 may generate overlapping counts from more or less count bits depending on the number of bits of the bitmap 404. In some embodiments, the counting circuit 408 may include one or more logic circuits having different circuit structures from each other to generate overlapping counts from the plurality of bits S0 and S1. For example, the counting circuit 408 may include a first logic circuit 602 for generating a bit value of the first count bit S0, and a second logic circuit 604 for generating a bit value of the second count bit S1.

In this example, the first logic 602 may output the first count bit S0 depending on whether one of the bits B0, B1, and B2 of the overlap bitmap 404 or all of the bits B0, B1, and B2 are or will be set to have an overlap level (e.g., a high level). The second logic circuit 604 may output a second count bit S1 depending on whether at least two of the bits B0, B1, and B2 are set to have an overlap level (e.g., a high level). Thus, in some embodiments, the first logic 602 may have a circuit structure different from that of the second logic 604. For example, in one embodiment, the first logic circuit 602 may include (e.g., may be implemented with) a first logic gate, and the second logic circuit 604 may include (e.g., may be implemented with) a plurality of second logic gates 606, 608, and 610 and a third logic gate 612.

The first logic gate of the first logic circuit 602 may output the first count bit S0 to have the bit value depending on whether any or all of the bits B0, B1, and B2 of the overlap bitmap 404 have an overlap level (e.g., a high level). For example, in one embodiment, the first logic gate of the first logic circuit 602 may be implemented as an exclusive or gate such that if any one of the bits B0, B1, and B2 of the overlap bitmap 404, or if all of the bits B0, B1, and B2 have an overlap level (e.g., a high level), the first logic circuit 602 outputs the first count bit S0 to have a high level (e.g., 1). Otherwise, the first logic circuit 602 outputs the first count bit S0 to have a low level (e.g., 0).

The second logic circuit 604 may include (e.g., may be implemented with) a plurality of second logic gates 606, 608, and 610 and a third logic gate 612. Each of the plurality of second logic gates 606, 608, and 610 may determine whether two corresponding bits of the bits B0, B1, and B2 of the overlap bitmap 404 have an overlap level (e.g., a high level), and the third logic gate 612 may output the second count bit S1 according to the output of the second logic gates 606, 608, and 610. For example, in one embodiment, each of the second logic gates 606, 608, and 610 may be implemented as an and gate, and the third logic gate 612 may be implemented as an or gate. In this case, each of the second logic gates 606, 608, and 610 may perform an and operation on a different set of bits B0, B1, and B2 of the overlay bitmap 404. For example, the first-second logic gate 606 may perform an and operation between a first bit B0 and a second bit B1 among bits B0, B1, and B2 of the overlap bitmap 404, the second-second logic gate 608 may perform an and operation between a second bit B1 and a third bit B2 among bits B0, B1, and B2 of the overlap bitmap 404, and the third-second logic gate 610 may perform an and operation between a first bit B0 and a third bit B2 among bits B0, B1, and B2 of the overlap bitmap 404. If any one or more of the second logic gates 606, 608, and 610 determines that their corresponding two of the bits B0, B1, and B2 of the overlap bitmap 404 have an overlap level (e.g., a high level), the third logic gate 612 may output the second count bit S1 to have a high level value. Otherwise, the third logic gate 612 may output the second count bit S1 to have a low level (e.g., 0).

For example, consider submitting 4 overlapping LBA ranges in sequence for overlap checking, and assuming that the first LBA range of the 4 overlapping LBA ranges does not overlap with any currently pending commands. In this case, when checking the first LBA range, the count circuit 408 may output an overlap count of 0 indicating no overlap (e.g., S0 ═ 0, S1 ═ 0, etc.) so that the first LBA range may continue execution. When a second LBA range of the 4 overlapping LBA ranges is examined, the first LBA range may now be loaded by the fetch circuitry 204 as one of the LBA ranges of the pending command (e.g., in execution), overlapping the second LBA range with the first LBA range. In this case, the count circuit 408 outputs an overlap count to have a value of 1 (e.g., S0 ═ 1 and S1 ═ 0) indicating that the second LBA range overlaps with one of the LBA ranges of the pending command (e.g., the first LBA range).

Likewise, when checking a third LBA range of the 4 overlapping LBA ranges, the second LBA range may be loaded (e.g., blocked and waiting to execute) by the fetch circuitry 204 as one of the LBA ranges of the pending command such that the third LBA range overlaps the first LBA range and the second LBA range. In this case, the count circuit 408 outputs an overlap count to have a value of 2 (e.g., S0 ═ 0 and S1 ═ 1), indicating that the third LBA range overlaps with both of the LBA ranges of the pending command (e.g., the first LBA range and the second LBA range). Further, when checking a fourth LBA range of the 4 overlapping LBA ranges, the third LBA range may be loaded (e.g., blocked and waiting to execute) by the fetch circuitry 204 as one of the LBA ranges of the pending command such that the fourth LBA range overlaps the first LBA range, the second LBA range, and the third LBA range. In this case, the count circuit 408 outputs an overlap count to have a value of 3 (e.g., S0 ═ 1 and S1 ═ 1), indicating that the fourth LBA range overlaps with three of the LBA ranges of the pending command (e.g., the first LBA range, the second LBA range, and the third LBA range).

In this illustrative example, as the command for each of the first, second, third, and fourth LBA ranges completes (e.g., a response that was successfully executed and/or provided to host device 102), the overlap count for each of the remaining ranges having overlapping ranges may decrease. Once its overlap count is reduced to 0, the corresponding command may be unblocked so that the corresponding command may continue execution. For example, when the command of the first LBA range is successfully executed, the overlap count of the second LBA range may be decreased from 1 to 0, the overlap count of the third LBA range may be decreased from 2 to 1, and the overlap count of the third LBA range may be decreased from 3 to 2. In this case, the command for the second LBA range may be unblocked so that it may continue execution and, after its successful execution, the overlap count for each of the remaining third and fourth overlapping LBA ranges may be reduced. Because the overlap count of the third LBA range is reduced to 0, commands of the third LBA range may be unblocked to continue execution and, upon successful execution thereof, the overlap count of the fourth LBA range may be reduced to 0 and, in response, the fourth LBA range may be unblocked and commands associated with the fourth LBA range may continue execution.

FIG. 7 is a flow diagram of an illustrative example of blocking commands with overlapping ranges in accordance with one or more illustrative embodiments of the present disclosure.

Referring to FIG. 7, the fetch circuitry 204 of the LOC circuitry 122 may receive a first activity request 702 corresponding to a first command (e.g., a READ command). For example, the first activity request may correspond to a first LBA Range 1. The fetch circuitry 204 may fetch (e.g., may read or may retrieve) the first LBA Range 1 from the storage memory 116 (e.g., from the LBA Range table 120) and may load the first LBA Range into an internal table (e.g., an internal register of a flip-flop) of the fetch circuitry 204 for comparison. In this illustrative example, the first LBA range may not overlap with any other ranges, and thus, the first LBA range may continue execution.

While the first command of the first LBA range is pending (e.g., executing), the fetch circuitry 204 may receive a second activity request 704 corresponding to a second command (e.g., an UNMAP command). The second activity request 704 may correspond to a second LBA Range 2 and a third LBA Range 3. For example, the second LBA Range 2 and the third LBA Range 3 may be disjoint LBA ranges of the same second command that do not overlap with each other. In this case, the fetch circuitry 204 may fetch (e.g., may read or may retrieve) each of the second and third LBA ranges Range 2 and Range 3 from the storage memory 116 (e.g., from the LBA Range table 120), and may load the second and third LBA ranges Range 2 and Range 3 into the internal table at the same time (e.g., at the same time or at the same time).

In this illustrative example, the second LBA Range 2 may overlap the first LBA Range 1, and thus, the second LBA Range 2 of the second command may be blocked. For example, an overlap count associated with the second LBA Range 2 may be set (e.g., by counting circuitry 408) such that the second LBA Range 2 is blocked. On the other hand, the third LBA Range 3 may not overlap with any other Range and thus may continue execution even if the second LBA Range 2 of the same command is blocked. When the first command associated with the first LBA Range 1 is completed, the overlap count of the second LBA Range 2 may be decreased, and once the overlap count of the second LBA Range 2 is decreased to 0, the second LBA Range 2 may be unblocked to continue execution.

Still referring to FIG. 7, while the second command of the third LBA Range Range 3 is pending (e.g., executing), the fetch circuitry 204 may receive a third activity request 706 corresponding to a third command (e.g., a READ command). The third activity request 706 may correspond to a fourth LBA Range 4. In this case, the obtaining circuitry 204 may obtain (e.g., may read or may retrieve) the fourth LBA Range 4 from the storage memory 116 (e.g., from the LBA Range table 120), and may load the fourth LBA Range 4 into the internal table. The fourth LBA Range 4 may overlap the third LBA Range 3 and thus may be blocked. For example, an overlap count associated with the fourth LBA Range 4 may be set (e.g., by counting circuitry 408) such that the fourth LBA Range 4 is blocked. When the second command associated with the third LBA Range 3 is completed, the overlap count of the fourth LBA Range 4 may be decreased, and once the overlap count of the fourth LBA Range 4 is decreased to 0, the fourth LBA Range 4 may be unblocked to continue execution. In this case, when the portion of the second command corresponding to the third LBA Range 3 is completed, the fourth LBA Range 4 may be unblocked to continue execution even if the second command itself (e.g., the second commands 704 of both the second Range 2 and the third Range 3) is not completed.

As discussed above, in accordance with one or more exemplary embodiments of the present disclosure, the storage device includes LOC circuitry 122 to enable overlap checking of multiple LBAs or LBA ranges simultaneously (e.g., simultaneously or at the same time). In some embodiments, LOC circuitry 122 may block execution of commands having overlapping LBAs or LBA ranges, while allowing execution of commands that do not have overlapping LBAs or LBA ranges (e.g., the same command and/or subsequent commands). Accordingly, the performance of the storage device may be improved.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated and/or simplified for clarity. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

It will be understood that when an element or layer is referred to as being "on …," "connected to," or "coupled to" another element or layer, it can be directly "on …," "connected to," or "coupled to" the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," "contains," "has" and/or "containing," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When the expression "at least one of" or the like is used after a list of elements, the entire list of elements is modified rather than modifying individual elements in the list.

As used herein, the terms "substantially," "about," and the like are used as approximate terms rather than as degree terms and are intended to account for inherent variations in measured or calculated values that would be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure. As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilizing," "utilizing," and "utilized," respectively.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of the present disclosure. It should be understood that the description of features or aspects of each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments, unless noted otherwise. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.