阅读说明：本技术 通过电脑模拟数字调光协议时序逻辑的方法、装置及介质 (Method, apparatus and medium for simulating digital dimming protocol sequential logic by computer ) 是由 陈志曼 黄荣丰 陈运筹 于 2021-10-27 设计创作，主要内容包括：本发明涉及数字信号控制领域,具体公开了一种通过电脑模拟数字调光协议时序逻辑的方法、装置及介质,包括根据电脑的第一端口的可配置参数,以及所需模拟的数字调光协议数据包,计算出模拟时序参数；按照所述模拟时序参数,将数字调光协议数据包转换为报文数据帧；将所述第一端口的参数配置为所述模拟时序参数；控制所述第一端口根据所述报文数据帧向电平转换电路发送第一电平信号。本发明通过电脑的端口直接输出模拟数字调光协议时序逻辑的电平信号,无需再通过单片机电路进行输出信号的协议转换,节约了硬件成本,使信号输出延迟更低,增加了控制信号的传输速度,使设备连接更便捷。(The invention relates to the field of digital signal control, and particularly discloses a method, a device and a medium for simulating digital dimming protocol time sequence logic through a computer, wherein the method comprises the steps of calculating a simulation time sequence parameter according to a configurable parameter of a first port of the computer and a digital dimming protocol data packet to be simulated; converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter; configuring parameters of the first port as the analog timing parameters; and controlling the first port to send a first level signal to a level conversion circuit according to the message data frame. The invention directly outputs the level signal of the analog-digital dimming protocol sequential logic through the port of the computer, does not need to perform protocol conversion of the output signal through a single chip circuit, saves the hardware cost, reduces the signal output delay, increases the transmission speed of the control signal and enables the equipment to be connected more conveniently.)

1. A method for simulating digital dimming protocol sequential logic via a computer, comprising:

calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and a digital dimming protocol data packet to be simulated;

converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;

configuring parameters of the first port as the analog timing parameters;

and controlling the first port to send a first level signal to a level conversion circuit according to the message data frame, so that the level conversion circuit converts the first level signal into a digital dimming signal and then sends the digital dimming signal to a digital dimming control bus.

2. The method according to claim 1, wherein the calculating the analog timing parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be simulated comprises:

calculating the minimum unit data bit time according to the communication speed which can be simulated by the first port;

and obtaining the analog time sequence parameter of the first port according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.

3. The method according to claim 2, wherein the converting of the digital dimming protocol packet into the message data frame according to the analog timing parameter comprises:

the digital dimming protocol data packet comprises: a control frame and a data frame;

obtaining a first analog timing sequence parameter according to the timing sequence logic of the control frame and the minimum unit data bit time;

and obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time.

4. The method according to claim 3, wherein the converting of the digital dimming protocol packet into the message data frame according to the analog timing parameter comprises:

converting the control frame into a first message data frame according to the first analog time sequence parameter;

and converting the data frame into a second message data frame according to the second analog time sequence parameter.

5. The method according to claim 4, wherein the configuring the parameter of the first port as the analog timing parameter controls the first port to send a first level signal to a level shifter circuit according to the message data frame, specifically:

configuring the first port as a first analog timing parameter, and controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;

and then configuring the first port as a second analog time sequence parameter, and controlling the first port to send a data frame signal to a level conversion circuit according to the second message data frame.

6. A device for simulating digital dimming protocol sequential logic through a computer is characterized by comprising a parameter calculation module, a data conversion module, a parameter configuration module, a sending control module and a level conversion circuit;

the parameter calculation module is used for calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and a digital dimming protocol data packet to be simulated;

the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;

the parameter configuration module is used for configuring the parameter of the first port as the simulation timing sequence parameter;

the sending control module is used for controlling the first port to send a first level signal to a level conversion circuit according to the message data frame;

the level conversion circuit is used for converting the first level signal into a digital dimming signal and then sending the digital dimming signal to a digital dimming control bus.

7. The apparatus of claim 6, wherein the parameter calculating module comprises a first calculating unit and a second calculating unit;

the digital dimming protocol data packet comprises: a control frame and a data frame;

the first calculating unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;

the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.

8. The apparatus of claim 7, wherein the data conversion module comprises a first conversion unit and a second conversion unit;

the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;

the second conversion unit is configured to convert the control frame into a second message data frame according to the second analog timing parameter.

9. The apparatus of claim 8, wherein the transmission control module comprises a first control unit and a second control unit;

the first control unit is configured to control the parameter configuration module to configure the parameter of the first port as the first analog timing parameter, and control the first port to send a control frame signal to a level shift circuit according to the first packet data frame;

the second control unit is configured to control the parameter configuration module to configure the parameter of the first port as the second analog timing parameter, and control the first port to send a data frame signal to a level shift circuit according to the second packet data frame.

10. A computer-readable storage medium, comprising a stored computer program, wherein the computer program, when executed, controls an apparatus in which the computer-readable storage medium is located to perform the method for simulating digital dimming protocol sequential logic by a computer according to any one of claims 1 to 5.

Technical Field

The present invention relates to the field of digital signal control, and in particular, to a method, an apparatus, and a medium for simulating a digital dimming protocol sequential logic through a computer.

Background

With the development of modern technology, the electrification and digitization degree of stages and entertainment places is higher and higher, how to more efficiently and conveniently control various kinds of complicated lighting and stage equipment becomes a difficult problem in the development of the industry, and a digital multiplexing signal protocol for controlling a plurality of equipment by sharing a control bus is one of the schemes for solving the problems.

The most common digital multiplexing signal protocol is the international standard USITT DMX512-A protocol (DMX 512 for short), because the DMX512 has microsecond level signal timing requirement, the existing light control console generally adopts the IO pin of MCU singlechip to simulate the timing level of DMX512 protocol, and then outputs to 458 bus through the level switching circuit, which is easy to realize, but for the port of computer, because it is difficult to directly control the IO port to generate the required timing level as singlechip, only simply send data signal, so it is common to establish the conventional data communication protocol between computer end and singlechip circuit, computer end sends 512 channel data to singlechip circuit, singlechip receives data and then uses IO pin to simulate the timing signal logic required by DXM512 protocol, however, the singlechip switching circuit has high cost, complex debugging and can generate certain delay, the installation and recovery of the equipment are troublesome.

Disclosure of Invention

In order to overcome the problems of high implementation cost, complex debugging, delayed signals and troublesome equipment installation and recovery of the conventional digital dimming protocol conversion circuit, the invention provides a method, a device and a medium for simulating the sequential logic of a digital dimming protocol through a computer.

The technical scheme adopted by the invention is as follows: a method for simulating digital dimming protocol sequential logic by a computer, comprising:

calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and a digital dimming protocol data packet to be simulated;

converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;

configuring parameters of the first port as the analog timing parameters;

and controlling the first port to send a first level signal to a level conversion circuit according to the message data frame, so that the level conversion circuit converts the first level signal into a digital dimming signal and then sends the digital dimming signal to a digital dimming control bus.

Preferably, the calculating an analog timing parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be simulated includes:

calculating the minimum unit data bit time according to the communication speed which can be simulated by the first port;

and obtaining the analog time sequence parameter of the first port according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.

Preferably, the converting the digital dimming protocol data packet into a message data frame according to the analog timing parameter specifically includes:

the digital dimming protocol data packet comprises: a control frame and a data frame;

obtaining a first analog timing sequence parameter according to the timing sequence logic of the control frame and the minimum unit data bit time;

and obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time.

Preferably, the converting the digital dimming protocol data packet into a message data frame according to the analog timing parameter specifically includes:

converting the control frame into a first message data frame according to the first analog time sequence parameter;

and converting the data frame into a second message data frame according to the second analog time sequence parameter.

Preferably, the configuring the parameter of the first port as the analog timing parameter controls the first port to send a first level signal to a level shift circuit according to the packet data frame, specifically:

configuring the first port as a first analog timing parameter, and controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;

and then configuring the first port as a second analog time sequence parameter, and controlling the first port to send a data frame signal to a level conversion circuit according to the second message data frame.

The technical scheme adopted by the invention also comprises the following steps: a device for simulating digital dimming protocol sequential logic through a computer comprises a parameter calculation module, a data conversion module, a parameter configuration module, a sending control module and a level conversion circuit;

the parameter calculation module is used for calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and a digital dimming protocol data packet to be simulated;

the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;

the parameter configuration module is used for configuring the parameter of the first port as the simulation timing sequence parameter;

the sending control module is used for controlling the first port to send a first level signal to a level conversion circuit according to the message data frame;

the level conversion circuit is used for converting the first level signal into a digital dimming signal and then sending the digital dimming signal to a digital dimming control bus.

Preferably, the parameter calculation module comprises a first calculation unit and a second calculation unit;

the digital dimming protocol data packet comprises: a control frame and a data frame;

the first calculating unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;

the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.

Preferably, the data conversion module comprises a first conversion unit and a second conversion unit;

the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;

the second conversion unit is configured to convert the control frame into a second message data frame according to the second analog timing parameter.

Preferably, the sending control module comprises a first control unit and a second control unit;

the first control unit is configured to control the parameter configuration module to configure the parameter of the first port as the first analog timing parameter, and control the first port to send a control frame signal to a level shift circuit according to the first packet data frame;

the second control unit is configured to control the parameter configuration module to configure the parameter of the first port as the second analog timing parameter, and control the first port to send a data frame signal to a level shift circuit according to the second packet data frame.

The technical scheme adopted by the invention also comprises a computer readable storage medium, wherein the computer readable storage medium comprises a stored computer program, and when the computer program runs, the equipment where the computer readable storage medium is located is controlled to execute the method for simulating the digital dimming protocol time sequence logic through the computer.

The invention has the beneficial effects that:

the level signal of the analog-digital dimming protocol sequential logic is directly output through the port of the computer, protocol conversion of the output signal is not required through a single chip circuit, hardware cost is saved, signal output delay is lower, control signal transmission speed is increased, and equipment connection is more convenient.

Preferably, the control frame and the data frame are respectively sent through different port configuration parameters, so that the optimal port parameters are configured for different signals, the universality of the scheme is higher, and the sending efficiency is higher.

Drawings

The invention will be further described with reference to the accompanying drawings, in which:

FIG. 1 is a schematic flow chart of one embodiment of the present invention;

FIG. 2 is a diagram of serial port output connection according to an embodiment of the present invention;

fig. 3 is a schematic diagram of COM serial port configuration parameters according to an embodiment of the present invention;

FIG. 4 is a table of DMX512 signal simulation parameters according to one embodiment of the present invention;

FIG. 5 is a table of parameters for the DMX512 signal;

FIG. 6 is a schematic diagram of the timing logic of the DMX512 signal.

In the figure: 1. a BREAK signal; 2. a MAB signal; 3. a data frame time slot; 4. a data frame start bit; 5. a lowest data bit; 6. the highest data bit; 7. a first stop position; 8. a second stop bit; 9. a data frame interval; 10. an MTBP signal; 11. a packet time slot; 12. transmitting a reset sequence; 13. a DMX512 data packet; 14. an SC signal; 15. a first data frame; 16. the nth data frame.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention relates to a method, a device and a medium for simulating digital dimming protocol time sequence logic through a computer, the working principle of the scheme relates to TTL level, USB level, RS232 level and RS485 level, the bus (and the bus interface on the computer mainboard) communication of the computer adopts TTL level, the serial communication interface (COM serial port) adopts RS-232 level, the USB interface adopts USB level, the RS485 bus communication adopts RS-485 level, and a level conversion circuit among the levels belongs to the prior art.

Referring to fig. 1 to 4, as one embodiment of the present invention, the embodiment is applied to a com serial port of a computer to simulate a signal timing logic of an international standard USITT DMX512-a protocol (DMX 512 for short), and outputs a TTL signal through a serial port, and the TTL signal is directly converted into an RS485 bus transmission signal through an RS485 chip for transmission.

Referring to fig. 1 to 2, the method of the present embodiment includes the following steps:

s1, calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be simulated;

s2, converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;

s3, configuring the parameters of the first port as the simulation time sequence parameters;

and S4, controlling the first port to send a first level signal to a level conversion circuit according to the message data frame, wherein the level conversion circuit converts the level of the first level signal into a level corresponding to the digital dimming control bus and sends the level to the digital dimming control bus.

Preferably, the method for calculating the analog timing parameter comprises the following steps:

a1, calculating the minimum unit data bit time according to the communication speed which can be simulated by the first port;

and A2, calculating the solution of the configuration parameter of the first port as an analog time sequence parameter according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.

The first port configuration parameters comprise communication rate, data bits, stop bits and parity bits.

Preferably, the digital dimming protocol data packet is converted into a message data frame according to the analog timing parameter, and the digital dimming protocol data packet includes a control frame and a data frame, so that the implementation steps are as follows:

b1, obtaining a first simulation timing sequence parameter according to the timing sequence logic of the control frame and the minimum unit data bit time;

and B2, obtaining a second simulation timing parameter according to the timing logic of the data frame and the minimum unit data bit time.

Preferably, the converting the digital dimming protocol data packet into the message data frame according to the analog timing parameter includes the following steps:

c1, converting the control frame into a first message data frame according to the first analog time sequence parameter;

and C2, converting the data frame into a second message data frame according to the second analog time sequence parameter.

Preferably, the configuring the parameter of the first port as the analog timing parameter, and controlling the first port to send a first level signal to a level shifter according to the packet data frame includes the following steps:

d1, configuring the first port as a first simulation timing parameter;

d2, controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;

d3, configuring the first port as a second simulation timing parameter;

and D4, controlling the first port to send a data frame signal to a level conversion circuit according to the second message data frame.

According to the scheme, the level signal of the analog-digital dimming protocol sequential logic is directly output through the port of the computer, protocol conversion of the output signal is not required through a single chip circuit, the hardware cost is saved, the signal output delay is lower, the control signal transmission speed is increased, and the equipment connection is more convenient.

As another embodiment of the present invention, a method for simulating DMX512 sequential logic through a COM serial port of a computer, where a first port corresponds to the COM serial port, and the digital dimming protocol data packet includes: a control frame and a data frame; the first level signal includes a control frame signal and a data frame signal.

Referring to fig. 5 and 6, DMX512 signal transmission relies on a hardware circuit RS485 bus transmission signal, strict time limitation requirements are imposed on signal timing, certain requirements are imposed on data transmission rate, the typical transmission rate is 250kbps, the duration of each bit is 4us, the duration of each data field is 44us, and the protocol also provides that each DMX512 data packet 13 can maximally support transmission of 512 frame data.

In the DMX512 timing logic simulated through the port of the computer, the MTBP signal 10, the BREAK signal 1 and the MAB signal 2 belong to control signals, and the data frame signal corresponds to a data field in the DMX512 protocol timing logic to be simulated, wherein the data field comprises an SC signal 14 as a start code.

In this embodiment, the method for simulating the digital dimming protocol sequential logic by the computer includes the following steps:

s1, calculating the minimum unit data bit time according to the communication speed which can be simulated by the first port;

s1.1, obtaining a first simulation time sequence parameter according to the time sequence logic of the control frame and the minimum unit data bit time;

s1.2, acquiring a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time;

s2, calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame, and converting the control frame into a first message data frame according to the first simulation time sequence parameter; calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame, and converting the data frame into a second message data frame according to the second simulation time sequence parameter;

s3, configuring the first port as a first analog timing parameter, and controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;

and S4, configuring the first port as a second analog time sequence parameter, and controlling the first port to send a data frame signal to a level conversion circuit according to the second message data frame.

Since DMX512 specifies that each timing unit must proceed according to a specified timing format and time, a complete DMX512 packet 13 consists of an MTBP signal 10, a BREAK signal 1, and a MAB signal 2, followed by data fields, and the duration of the DMX512 packet 13 corresponds to the packet slot 11, which is as follows:

(1) the MTBP signal 10(Mark Time Between Packages), also called MBB signal (Mark Before Between), marks that the transmission of a complete DMX512 data packet 13 is completed, and is also a Mark bit for the next DMX512 data packet 13 to start, and the high level is valid, which indicates that the current transmission line is in an idle state and no data is transmitted;

(2) BREAK signal 1 is the start control signal for a DMX512 packet 13, corresponding to the start of a new DMX512 packet 13; the DMX512 protocol specifies that the signal of BREAK is effective at low level, and the duration is not less than the length of the data fields in the two DMX512 data packets 13, namely, is more than or equal to 88 us;

(3) MAB signal 2(Mark After BREAK) is an indication that DMX512 data packet 13 starts to be transmitted, and since the first bit of each data field is low, MAB signal 2 is added to distinguish between low of BREAK and low of the start bit of the data field; the protocol specifies that the typical duration of a MAB is 8us to 1s, i.e., two bits of time, the high level is active;

(4) the SC signal 14(Start Code), i.e., Start Code, frame 0 data, is the same as a normal data field, but its 8-bit data bits are all zero, which is the Start flag byte of the data field in the DMX512 packet 13;

(5) a data field, beginning with the SC signal 14, followed by a first data frame 15 to an nth data frame 16, where n is 512 at maximum, i.e. the DMX512 packet 13 contains 512 data frames at most; carrying the valid contents of DMX512 packet 13.

The BREAK signal 1, the MAB signal 2, and the SC signal 14 together form a transmission reset sequence 12, that is, after each DMX512 data packet 13 is sent, the transmission reset sequence 12 confirms that the next DMX512 data packet 13 starts to be sent.

The duration of a single data frame corresponds to a data frame time slot 3, and each data frame consists of a data frame start bit 4, a lowest data bit 5 to a highest data bit 6, a first stop bit 7 and a second stop bit 8; a data frame interval 9 is provided between two adjacent data frames.

Referring to fig. 3 to 4, the specific calculation steps of the present embodiment are as follows:

s1, calculating time sequence parameters of the simulated MTBP signal 10, the BREAK signal 1 and the MAB signal 2 according to the configurable parameters of the COM serial port of the computer and the DMX512 protocol time sequence logic;

s1.1, according to the DMX512 protocol sequential logic, the MTBP signal 10 is omitted because the effective time of the MTBP signal 10 can be 0;

s1.2, performing sequential logic according to a BREAK signal 1 and an MAB signal 2 in a DMX512 protocol; according to effective configurable parameters of a COM serial port of a computer, setting a communication speed as b, a data bit as d, a stop bit as s and a parity bit p as null, solving b, d and s, and outputting as a first analog timing sequence parameter;

s1.3, solving COM serial port configuration parameters suitable for generating data fields, solving b, d and S, and outputting the parameters as second analog time sequence parameters;

s2, compiling a first message data frame according to BREAK signal 1 and MAB signal 2 of DMX512 protocol sequential logic, and compiling a second message data frame according to data fields;

s3, configuring a parameter of a COM serial port on a computer as a first simulation time sequence parameter; the COM serial port sends a control frame signal to the level conversion circuit according to the first message data frame;

s4, configuring the parameter of the COM serial port on the computer as a second simulation time sequence parameter; the COM serial port sends a data frame signal to the level conversion circuit according to the second message data frame;

and S5, the level conversion circuit converts the levels of the control frame signal and the data frame signal into the level corresponding to the digital dimming control bus and sends the level to the digital dimming control bus.

The specific calculation process of the simulation time sequence parameter is as follows: the unit of baud rate b which can be output by the COM serial port is bps, the time of the corresponding minimum unit data bit is t, and the unit is us, namely b and t satisfy the following equation:

t is 1 second/baud rate is 1000000 us/b;

according to the signal sequential logic of the COM serial port, the output data format is as follows:

the starting bit (1bit) + the data bit (4-8 bit) + the parity bit (0-1 bit) + the stop bit (1,1.5,2 bit).

Now set the data bits to variable d, the preferred values for d are 4,5,6,7, 8; the stop bit is set as a variable s, and the desirable values of s are 1,1.5 and 2; simulating a BREAK signal 1 and an MAB signal 2, wherein COM serial port configuration parameters need to meet the following formula conditions:

the formula is 1000000/b-t;

the formula is that s is more than or equal to 8 us;

formula (c) s x t is less than or equal to 12 us;

formula (1+ d) t is more than or equal to 88 us;

in one embodiment of the present invention, the baud rate b of the COM serial port is 250000bps, and the corresponding minimum unit data bit time is t 1000000us/250000bps 4 us; according to the DMX512 protocol sequential logic, the BREAK signal 1 time is more than or equal to 88us, and the MAB signal 2 time generally takes more than or equal to 8us and less than or equal to 12 us.

Since s is preferably only three, the simplest substitution can be used to solve the above.

If s is 1, the obtainable value of t is 8, 9, 10, 11, 12 according to formula (ii) and formula (iii), and then t is 8, 9, 10, 11, 12 are respectively substituted into formula (i), and since b is a positive integer, t is 8us and 10 us; substituting the value of t-8 us into a formula (1+ d) 8 is not less than 88, and obtaining d to be not less than 10 can meet the condition, and the value range of d is only 4,5,6,7 and 8, so that t-8 is not suitable;

substituting the value of t ═ 10us into a formula (1+ d) × 10 ≥ 88, and obtaining d ≥ 7.8 can meet the condition, and d can be equal to 8 because the value range of the data bit d is only 4,5,6,7 and 8;

other combination modes are also derived in the same way as long as the 4 formulas are met;

parameter configuration of serial ports of one group of analog BREAK signal 1 and MAB signal 2COM can be obtained, that is, a first analog timing parameter is b 100000bps, d 8 bits, and s 1; at the moment, the format of the COM serial port data frame is 1-bit start bit, 8-bit data bit and 1-bit stop bit, and the communication speed is 100000 bps.

Sending a BREAK signal 1: when the configuration transmission Data is 0, the time for the serial port transmitting end Data line Tx to keep the low level BREAK is (1+8) × 10us ═ 90us, and the condition of being more than or equal to 88us is met.

And simultaneously, generating an MAB signal 2 by using the delay time Ts (Ts x t) 1 x 10us (10 us) of the stop bit, wherein the MAB signal 2 meets the use requirements of more than or equal to 8us and less than or equal to 12us of the standard.

Because the formats of the SC signal 14 and the data field are the same, the same COM serial port parameter configuration, that is, the second analog timing parameter, is configured with a communication rate b of 250000 bps; data bit d is 8 bits; the stop bit s is 1 bit; parity bit p is set to none; transmitting the SC signal 14; then sending data fields from the first data frame 15 to the nth data frame 16, wherein the data fields have 512 fields at most;

and finally, a first level signal formed by the control frame signal and the data frame signal is output to the RS485 bus through the RS 232-to-RS 485 level conversion circuit.

The configuration parameters can have a plurality of solutions, and the solution can be used in a scheme that the COM serial port outputs the DMX512 protocol without repeated calculation.

In the embodiment, sequential logic signals conforming to the DMX512 protocol are directly output through the COM port or the USB port of the computer, protocol conversion of output signals is not required through the MCU singlechip circuit, so that the hardware cost is saved, the signal output delay is lower, the transmission speed of control signals is increased, and the equipment connection is more convenient.

The scheme can be used for interconnection between various computer ports and various analog-digital dimming protocols, is compatible with various bus level conversion circuits, and has high scheme compatibility.

The invention further provides a device for simulating the sequential logic of a digital dimming protocol through a computer, which comprises a parameter calculation module, a data conversion module, a parameter configuration module, a transmission control module and a level conversion circuit.

The parameter calculation module is used for calculating an analog time sequence parameter according to the configurable parameter of the first port of the computer and a digital dimming protocol data packet to be simulated;

the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the digital dimming protocol time sequence logic and the analog time sequence parameter;

the parameter configuration module is used for configuring the parameters of the first port into simulation time sequence parameters;

the sending control module is used for controlling the first port to send a first level signal to the level conversion circuit according to the message data frame;

the level conversion circuit is used for converting the level of the first level signal into the level corresponding to the digital dimming control bus and sending the level to the digital dimming control bus.

The device of the embodiment realizes the method for simulating the digital dimming protocol sequential logic through the computer.

Preferably, the parameter calculation module comprises a first calculation unit and a second calculation unit;

the digital dimming protocol data packet comprises: a control frame and a data frame;

the first calculating unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;

the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.

Preferably, the data conversion module comprises a first conversion unit and a second conversion unit;

the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;

the second conversion unit is configured to convert the control frame into a second message data frame according to the second analog timing parameter.

Preferably, the sending control module comprises a first control unit and a second control unit;

the first control unit is configured to control the parameter configuration module to configure the parameter of the first port as the first analog timing parameter, and control the first port to send a control frame signal to a level shift circuit according to the first packet data frame;

the second control unit is configured to control the parameter configuration module to configure the parameter of the first port as the second analog timing parameter, and control the first port to send a data frame signal to a level shift circuit according to the second packet data frame.

The invention also discloses a terminal device, which comprises a processor and a storage device, wherein the storage device is used for storing one or more programs; when the one or more programs are executed by the processor, the processor implements the method for testing impact properties of a material as described above. The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, which is the control center for the test equipment and connects the various parts of the overall test equipment using various interfaces and lines.

The storage means may be adapted to store computer programs and/or modules, and the processor may be adapted to implement various functions of the terminal device by running or executing the computer programs and/or modules stored in the storage means and by invoking data stored in the storage means. The storage device may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the storage device may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.

Wherein, the terminal device integrated module/unit can be stored in a computer readable storage medium if it is implemented in the form of software functional unit and sold or used as a stand-alone product. Based on such understanding, all or part of the flow in the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in at least one computer-readable storage medium and used for instructing related hardware to implement the steps of the above-described embodiments of the method when executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like.

It should be noted that the above-described embodiments of the apparatus and device are merely schematic, where units illustrated as separate components may or may not be physically separate, and components illustrated as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.

The above-mentioned embodiments are further detailed to explain the objects, technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the scope of the present invention. It should be understood that any modifications, equivalents, improvements and the like, which come within the spirit and principle of the invention, may occur to those skilled in the art and are intended to be included within the scope of the invention.