阅读说明：本技术 一种时域高稳定超宽谱脉冲源 (Time domain high-stability ultra-wide spectrum pulse source ) 是由 杨瑜 肖建平 朱维 罗尧天 唐冬林 童允 于 2021-01-19 设计创作，主要内容包括：本发明公开了一种时域高稳定超宽谱脉冲源,包括雪崩管V1～V22,所述雪崩管V1的基极、雪崩管V2的基极、电阻R25的一端连接、电阻R23的一端连接12V脉冲输入,所述雪崩管V1的集电极分别与电容C1的一端、雪崩管V2的集电极和电阻R2的一端连接,所述电阻R2的另一端与电阻R1的一端连接。本发明将前n级雪崩管改成了低压触发雪崩管,其抖动最优的触发点相应降低。从而大大减轻了对触发信号幅度和前沿的要求,提高了整个链路的输出时域稳定性。(The invention discloses a time domain high-stability ultra-wide spectrum pulse source which comprises avalanche transistors V1-V22, wherein a base electrode of a avalanche transistor V1, a base electrode of an avalanche transistor V2 and one end of a resistor R25 are connected, one end of a resistor R23 is connected with 12V pulse input, a collector electrode of an avalanche transistor V1 is respectively connected with one end of a capacitor C1, a collector electrode of the avalanche transistor V2 and one end of a resistor R2, and the other end of the resistor R2 is connected with one end of a resistor R1. The invention changes the first n-grade avalanche transistors into low-voltage trigger avalanche transistors, and the trigger point with the optimal jitter is correspondingly reduced. Therefore, the requirements on the amplitude and the leading edge of the trigger signal are greatly reduced, and the output time domain stability of the whole link is improved.)

1. A time domain high-stability ultra-wide spectrum pulse source is characterized by comprising avalanche transistors V1-V22, a base of an avalanche transistor V1, a base of an avalanche transistor V2 and one end of a resistor R25 are connected, one end of a resistor R23 is connected with a 12V pulse input, a collector of the avalanche transistor V1 is respectively connected with one end of a capacitor C1, a collector of the avalanche transistor V2 and one end of a resistor R2, the other end of the resistor R2 is connected with one end of a resistor R1, the other end of the capacitor C1 is connected with one end of a resistor R24, an emitter of the avalanche transistor V1 is respectively connected with an emitter of an avalanche transistor V2, one end of a resistor R26 and one end of a capacitor C2, the other end of a capacitor C2 is respectively connected with one end of a resistor R7, a collector of an emitter of an avalanche transistor V3 and a collector of the avalanche transistor V13, and bases of the avalanche transistors V36 3 2 and 13 are respectively connected with bases of the avalanche transistors V13 and 36 3 2, One end of a resistor R13 is connected with one end of a capacitor C3, the other end of the capacitor C3 is respectively connected with one end of a resistor R4, a collector of an avalanche tube V4 and a collector of an avalanche tube V14, a base of the avalanche tube V4 is respectively connected with an emitter of an avalanche tube V4, an emitter of an avalanche tube V14, a base of an avalanche tube V14, one end of a resistor R14 and one end of a capacitor C4, the other end of the capacitor C4 is respectively connected with one end of a resistor R5, a collector of an avalanche tube V5 and a collector of an avalanche tube V15, a base of the avalanche tube V15 is respectively connected with an emitter of the avalanche tube V15, a base of the avalanche tube V15, one end of the resistor R15 and one end of the capacitor C15, the other end of the capacitor C15 is respectively connected with one end of the resistor R15, the collector of the avalanche tube V15, the base of the avalanche tube V15 and the collector of the avalanche tube V15, An emitter of the avalanche transistor V16, a base of the avalanche transistor V16, one end of a resistor R16 and one end of a capacitor C6 are connected, the other end of the capacitor C6 is respectively connected with one end of a resistor R7, a collector of the avalanche transistor V7 and a collector of the avalanche transistor V17, a base of the avalanche transistor V7 is respectively connected with an emitter of the avalanche transistor V7, an emitter of the avalanche transistor V17, a base of the avalanche transistor V17, one end of a resistor R17 and one end of a capacitor C7, the other end of the capacitor C7 is respectively connected with one end of a resistor R8, a collector of the avalanche transistor V8 and a collector of the avalanche transistor V8, a base of the avalanche transistor V8 is respectively connected with an emitter of the avalanche transistor V8, a base of the avalanche transistor V8, one end of the resistor R8 and one end of the collector of the capacitor C8, the other end of the capacitor C8 is respectively connected with the collector of the avalanche transistor V8 and the collector of the avalanche transistor V8, the base of the avalanche transistor V9 is respectively connected with the emitter of the avalanche transistor V9, the emitter of the avalanche transistor V19, the base of the avalanche transistor V19, one end of a resistor R19 and one end of a capacitor C9, the other end of the capacitor C9 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V20, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the emitter of the avalanche transistor V20, the base of the avalanche transistor V20, one end of a resistor R20 and one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V10, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the base of the avalanche transistor V10, one end of the resistor R10 and one end of the capacitor C10, and the other end of the resistor C10 are respectively connected with the emitter of the avalanche transistor V10 and the other, The collector of the avalanche transistor V12 is connected with the collector of the avalanche transistor V22, the base of the avalanche transistor V12 is connected with the emitter of the avalanche transistor V12, the emitter of the avalanche transistor V22, the base of the avalanche transistor V22 and one end of a resistor R22 respectively and outputs UWB signals, and the other end of the resistor R23, the other end of the resistor R24, the other end of the resistor R25, the other end of the resistor R26, the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, the other end of the resistor R16, the other end of the resistor R17, the other end of the resistor R18, the other end of the resistor R19, the other end of the resistor R20, the other end of the resistor R21 and the other end of the resistor R22 are all connected to.

2. The time-domain highly stable ultra-wide spectrum pulse source according to claim 1, wherein the other end of the resistor R1, the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8 and the other end of the resistor R9 are all connected with a 100V DC input.

3. The time-domain highly stable ultra-wide spectrum pulse source according to claim 1, wherein the other end of the resistor R10, the other end of the resistor R11 and the other end of the resistor R12 are all connected to a 300V dc input.

4. The time domain highly stable ultra-wide spectrum pulse source according to claim 1, wherein each of the avalanche transistors V1-V8 and V13-V18 is a low voltage avalanche transistor.

5. The time domain highly stable ultra-wide spectrum pulse source according to claim 1, wherein said avalanche transistors V9-V12 and V19-V22 are medium voltage avalanche transistors.

6. The time-domain highly stable ultra-wide spectrum pulse source according to claim 1, wherein one end of the resistor R23 is further connected to the anode of the diode V23, and one end of the resistor R25 is further connected to the cathode of the diode V23.

Technical Field

The invention belongs to the field of ultra-wide spectrum pulse sources, and particularly relates to a time domain high-stability ultra-wide spectrum pulse source.

Background

The ultra-wide spectrum pulse source is mainly used for generating carrier-free and ultra-wide spectrum pulse signals with frequency spectrum covering direct current to several GHz.

The ultra-wide spectrum pulse source generally adopts a Marx circuit, the working principle of the Marx circuit is that a plurality of capacitors in the circuit are charged in parallel when no trigger pulse is input, and after the trigger pulse is input from the outside, the capacitors are connected in series to discharge to a load through the conduction of an avalanche tube, so that the ultra-wide spectrum pulse is formed on the load.

The main indicators of the ultra-wide spectrum pulse source are output power, efficiency, pulse repetition frequency, time domain stability and the like. The time domain stability index of the ultra-wide spectrum pulse source is one of important indexes of the ultra-wide spectrum pulse source.

A typical Marx circuit used in the existing ultra-wide spectrum pulse source is shown in fig. 1, and the so-called Marx circuit is a circuit which is invented by the german scientist Marx and has a plurality of tubes which are charged in parallel by a power supply and then are discharged to a load in series. The Marx circuit structure has the outstanding advantages due to the parallel charging and series discharging mechanisms, can obtain higher output pulse with lower power supply voltage, and has the amplitude far higher than the power supply voltage. In the design, a charging and discharging mechanism and a pulse forming mechanism of the Marx circuit are researched, and an analysis process is briefly introduced below.

Fig. 1 shows a 5-stage Marx circuit, in which avalanche transistors are turned off but are already in the critical avalanche state before the trigger pulse is added. The capacitors C1-C5 are all charged with DC bias power supply voltage EC.

After the trigger pulse is added, T1 avalanche breakdown is caused firstly, so that the left end potential of C2 is equal to the right end potential of C1, i.e. approximately equal to EC (referring to ground potential, the same applies hereinafter), after the capacitor is charged, the charge charged on the capacitor is not discharged instantaneously, so that the potential difference between the two ends of the capacitor is almost kept unchanged, and then, the instantaneous potential of 2 times EC can be obtained at the right end of C2. The potential applied to the T2 at this instant will also cause avalanche breakdown in T2, and so on, and the T3-T5 tubes will avalanche successively. Eventually, at the right end of C5, an instantaneous potential of almost 5 times EC will be obtained.

The above simple analysis does not take into account the avalanche voltage range of the tube. In practice, a potential of 2 or even 5 times EC is applied to the tube and the tube will have to burn out. Fortunately, this does not happen. At a slight rise in the potential at the right end of C2 from EC to EC + Δ, an avalanche short will occur at T2. After nanosecond-scale time, when the potential at the right end of the C2 rises to two times EC, the T2 will not suffer from 2EC voltage drop, even the subsequent tubes T3-T5 already avalanche, and will not bear large voltage drop, so as to cause burnout, and the avalanche of the tubes T2-T5 will not necessarily be performed in sequence. This phenomenon corresponds to an avalanche acceleration effect, which is very advantageous for cascade generation of high voltage narrow pulses.

After all the stages are avalanche, since the capacitors C1-C5 are equivalent to being connected in series and discharged from the left end of C1 to the ground and the right end of C5 to the ground, the potential will rapidly fade, and a fast-fading pulse trailing edge is formed. The load connected to both ends of the circuit can effectively prevent reflection to improve the waveform, and positive and negative pulses are obtained on RL1 and RL2 respectively. The disadvantage is that the output pulse amplitude is halved.

In the existing typical Marx circuit, as the trigger pulse amplitude of the avalanche transistors T2-T5 close to the output end is high, and the leading edge is steep, the influence on the stability of the output pulse is small; the avalanche transistor T1 near the input end is triggered by the base electrode, and the trigger pulse is a video signal, which has a low amplitude and a slow leading edge. Therefore, the time-domain stability of the finally output ultra-wide spectrum pulse is mainly determined by the first stage of the whole Marx link, namely the avalanche transistor T1.

The jitter mean square error is about 14ps due to the time domain stability of the current typical circuit at normal temperature.

Disclosure of Invention

Aiming at the defects in the prior art, the ultra-wide spectrum pulse source with high stability of the time domain provided by the invention solves the problem of low stability of the ultra-wide spectrum pulse source.

In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a time domain high-stability ultra-wide spectrum pulse source is characterized by comprising avalanche transistors V1-V22, a base of an avalanche transistor V1, a base of an avalanche transistor V2 and one end of a resistor R25 are connected, one end of a resistor R23 is connected with a 12V pulse input, a collector of the avalanche transistor V1 is respectively connected with one end of a capacitor C1, a collector of the avalanche transistor V2 and one end of a resistor R2, the other end of the resistor R2 is connected with one end of a resistor R1, the other end of the capacitor C1 is connected with one end of a resistor R24, an emitter of the avalanche transistor V1 is respectively connected with an emitter of an avalanche transistor V2, one end of a resistor R26 and one end of a capacitor C2, the other end of a capacitor C2 is respectively connected with one end of a resistor R7, a collector of an emitter of an avalanche transistor V3 and a collector of the avalanche transistor V13, and bases of the avalanche transistors V36 3 2 and 13 are respectively connected with bases of the avalanche transistors V13 and 36 3 2, One end of a resistor R13 is connected with one end of a capacitor C3, the other end of the capacitor C3 is respectively connected with one end of a resistor R4, a collector of an avalanche tube V4 and a collector of an avalanche tube V14, a base of the avalanche tube V4 is respectively connected with an emitter of an avalanche tube V4, an emitter of an avalanche tube V14, a base of an avalanche tube V14, one end of a resistor R14 and one end of a capacitor C4, the other end of the capacitor C4 is respectively connected with one end of a resistor R5, a collector of an avalanche tube V5 and a collector of an avalanche tube V15, a base of the avalanche tube V15 is respectively connected with an emitter of the avalanche tube V15, a base of the avalanche tube V15, one end of the resistor R15 and one end of the capacitor C15, the other end of the capacitor C15 is respectively connected with one end of the resistor R15, the collector of the avalanche tube V15, the base of the avalanche tube V15 and the collector of the avalanche tube V15, An emitter of the avalanche transistor V16, a base of the avalanche transistor V16, one end of a resistor R16 and one end of a capacitor C6 are connected, the other end of the capacitor C6 is respectively connected with one end of a resistor R7, a collector of the avalanche transistor V7 and a collector of the avalanche transistor V17, a base of the avalanche transistor V7 is respectively connected with an emitter of the avalanche transistor V7, an emitter of the avalanche transistor V17, a base of the avalanche transistor V17, one end of a resistor R17 and one end of a capacitor C7, the other end of the capacitor C7 is respectively connected with one end of a resistor R8, a collector of the avalanche transistor V8 and a collector of the avalanche transistor V8, a base of the avalanche transistor V8 is respectively connected with an emitter of the avalanche transistor V8, a base of the avalanche transistor V8, one end of the resistor R8 and one end of the collector of the capacitor C8, the other end of the capacitor C8 is respectively connected with the collector of the avalanche transistor V8 and the collector of the avalanche transistor V8, the base of the avalanche transistor V9 is respectively connected with the emitter of the avalanche transistor V9, the emitter of the avalanche transistor V19, the base of the avalanche transistor V19, one end of a resistor R19 and one end of a capacitor C9, the other end of the capacitor C9 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V20, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the emitter of the avalanche transistor V20, the base of the avalanche transistor V20, one end of a resistor R20 and one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V10, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the base of the avalanche transistor V10, one end of the resistor R10 and one end of the capacitor C10, and the other end of the resistor C10 are respectively connected with the emitter of the avalanche transistor V10 and the other, The collector of the avalanche transistor V12 is connected with the collector of the avalanche transistor V22, the base of the avalanche transistor V12 is connected with the emitter of the avalanche transistor V12, the emitter of the avalanche transistor V22, the base of the avalanche transistor V22 and one end of a resistor R22 respectively and outputs UWB signals, and the other end of the resistor R23, the other end of the resistor R24, the other end of the resistor R25, the other end of the resistor R26, the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, the other end of the resistor R16, the other end of the resistor R17, the other end of the resistor R18, the other end of the resistor R19, the other end of the resistor R20, the other end of the resistor R21 and the other end of the resistor R22 are all connected to.

Further: the other end of the resistor R1, the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8 and the other end of the resistor R9 are all connected with 100V direct current input.

Further: the other end of the resistor R10, the other end of the resistor R11 and the other end of the resistor R12 are connected with 300V direct current input.

Further: the avalanche tubes V1-V8 and the avalanche tubes V13-V18 are low-pressure avalanche tubes.

Further: the avalanche tubes V9-V12 and the avalanche tubes V19-V22 are medium-pressure avalanche tubes.

Further: one end of the resistor R23 is further connected with the anode of the diode V23, and one end of the resistor R25 is further connected with the cathode of the diode V23.

The invention has the beneficial effects that: the invention changes the first n-grade avalanche transistors into low-voltage trigger avalanche transistors, and the trigger point with the optimal jitter is correspondingly reduced. Therefore, the requirements on the amplitude and the leading edge of the trigger signal are greatly reduced, and the output time domain stability of the whole link is improved.

Drawings

FIG. 1 is a 5-stage Marx circuit;

FIG. 2 is a circuit diagram of the present invention;

FIG. 3 is a Marx circuit jitter test schematic diagram;

FIG. 4 is a schematic diagram of a pulse jitter mechanism;

FIG. 5 is a graph of an avalanche pipe input trigger curve;

fig. 6 is a block diagram of a high stability ultra-wide spectrum pulse source test.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.

As shown in fig. 2, the time domain ultra-wide spectrum pulse source with high stability is characterized by comprising avalanche tubes V1 to V22, wherein a base of the avalanche tube V1, a base of the avalanche tube V2 and one end of a resistor R25 are connected, one end of a resistor R23 is connected with 12V pulse input, a collector of the avalanche tube V1 is respectively connected with one end of a capacitor C1, a collector of the avalanche tube V2 and one end of a resistor R2, the other end of the resistor R2 is connected with one end of a resistor R1, the other end of the capacitor C1 is connected with one end of a resistor R24, an emitter of the avalanche tube V1 is respectively connected with an emitter of the avalanche tube V2, one end of the resistor R26 and one end of a capacitor C2, the other end of the capacitor C2 is respectively connected with one end of a resistor R3, an emitter of the avalanche tube V3 and a collector of the avalanche tube V13, and the base of the snow tube V3 is respectively connected with one end of the emitter of the avalanche tube V13 and the avalanche tube V13, The base of the avalanche transistor V13, one end of the resistor R13 and one end of the capacitor C3 are connected, the other end of the capacitor C3 is respectively connected with one end of the resistor R4, the collector of the avalanche transistor V4 and the collector of the avalanche transistor V14, the base of the avalanche transistor V4 is respectively connected with the emitter of the avalanche transistor V4, the emitter of the avalanche transistor V14, the base of the avalanche transistor V14, one end of the resistor R14 and one end of the capacitor C4, the other end of the capacitor C4 is respectively connected with one end of the resistor R4, the collector of the avalanche transistor V4 and the collector of the avalanche transistor V4, the base of the avalanche transistor V4 is respectively connected with the emitter of the avalanche transistor V4, the base of the resistor R4 and one end of the emitter of the capacitor C4, the other end of the capacitor C4 is respectively connected with one end of the emitter of the resistor R4, the collector of the avalanche transistor V4 and the collector of the avalanche transistor V4, and the collector of the emitter of the avalanche transistor V4 and the collector of the avalanche transistor V4 are respectively connected with one end of the emitter, An emitter of the avalanche transistor V16, a base of the avalanche transistor V16, one end of a resistor R16 and one end of a capacitor C6 are connected, the other end of the capacitor C6 is respectively connected with one end of a resistor R7, a collector of the avalanche transistor V7 and a collector of the avalanche transistor V17, a base of the avalanche transistor V7 is respectively connected with an emitter of the avalanche transistor V7, an emitter of the avalanche transistor V17, a base of the avalanche transistor V17, one end of a resistor R17 and one end of a capacitor C7, the other end of the capacitor C7 is respectively connected with one end of a resistor R8, a collector of the avalanche transistor V8 and a collector of the avalanche transistor V8, a base of the avalanche transistor V8 is respectively connected with an emitter of the avalanche transistor V8, a base of the avalanche transistor V8, one end of the resistor R8 and one end of the collector of the capacitor C8, the other end of the capacitor C8 is respectively connected with the collector of the avalanche transistor V8 and the collector of the avalanche transistor V8, the base of the avalanche transistor V9 is respectively connected with the emitter of the avalanche transistor V9, the emitter of the avalanche transistor V19, the base of the avalanche transistor V19, one end of a resistor R19 and one end of a capacitor C9, the other end of the capacitor C9 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V20, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the emitter of the avalanche transistor V20, the base of the avalanche transistor V20, one end of a resistor R20 and one end of a capacitor C10, the other end of the capacitor C10 is respectively connected with one end of a resistor R10, the collector of the avalanche transistor V10 and the collector of the avalanche transistor V10, the base of the avalanche transistor V10 is respectively connected with the emitter of the avalanche transistor V10, the base of the avalanche transistor V10, one end of the resistor R10 and one end of the capacitor C10, and the other end of the resistor C10 are respectively connected with the emitter of the avalanche transistor V10 and the other, The collector of the avalanche transistor V12 is connected with the collector of the avalanche transistor V22, the base of the avalanche transistor V12 is connected with the emitter of the avalanche transistor V12, the emitter of the avalanche transistor V22, the base of the avalanche transistor V22 and one end of a resistor R22 respectively and outputs UWB signals, and the other end of the resistor R23, the other end of the resistor R24, the other end of the resistor R25, the other end of the resistor R26, the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, the other end of the resistor R16, the other end of the resistor R17, the other end of the resistor R18, the other end of the resistor R19, the other end of the resistor R20, the other end of the resistor R21 and the other end of the resistor R22 are all connected to.

The other end of the resistor R1, the other end of the resistor R3, the other end of the resistor R4, the other end of the resistor R5, the other end of the resistor R6, the other end of the resistor R7, the other end of the resistor R8 and the other end of the resistor R9 are all connected with 100V direct current input.

The other end of the resistor R10, the other end of the resistor R11 and the other end of the resistor R12 are connected with 300V direct current input.

Important improvements are in the following areas:

(1) the avalanche transistor is added from a single tube to a double tube which are connected in parallel, so that the conduction resistance of the avalanche transistor during conduction can be reduced, and the reliability is improved;

(2) avalanche triodes in the circuit are increased from the original type to two types: a first medium pressure avalanche pipe; a second low pressure avalanche pipe; in the circuit diagram, V1-V8 and V13-V18 adopt low-voltage avalanche transistors, and V9-V12 and V19-V22 adopt medium-voltage avalanche transistors;

(3) the power supply is changed into two different voltages to respectively supply power to the two avalanche transistors.

The avalanche triode in the typical Marx pulse circuit only has a medium-voltage avalanche transistor model, the invention improves the circuit, changes the front n-stage avalanche circuit into a low-voltage avalanche transistor model, correspondingly increases the direct current power supply of the n-stage avalanche circuit, and keeps the back stage avalanche circuit unchanged. The purpose of this improvement is primarily to increase the relative trigger voltage of the avalanche circuit and thus the stability of the output pulse.

Since the stability of the time domain appears as phase noise in the frequency domain, they are interrelated via fourier transform. Thus, the time domain stability is improved, and at the same time, the phase noise of the output signal is also improved.

To illustrate the practical effects of the present invention, the pulse jitter mechanism was first analyzed, and is shown in fig. 4. The input trigger pulse of each stage of the pulse source enables the avalanche diode to be instantly conducted to form an output pulse front edge, and the avalanche diode is turned off to form an output pulse back edge along with the end of capacitor discharge. The avalanche diode generates jitter of output pulses due to the uncertainty of the time of switching from off to on, which is caused by the fact that the level condition of the switching state transition is a range of values, not a strictly determined value. In connection with the illustration, assume that the level range of the avalanche switch state transition is [ V ]_O-V_B,V_O+V_B]Under the condition that the slope of the trigger signal is K, the output time base range is [ T_O-T_B,T_O+T_B]. The time base jitters T_BSwitching level conversion range V_BAnd the rising edge slope K of the trigger signal satisfies the following conditions:

it can be seen that the time base jitter is inversely related to the rising edge slope K of the trigger signal. Therefore, the jitter of the output time base of the avalanche diode can be reduced by increasing the slope K.

Due to the fact that the input trigger signal of the avalanche diode can be approximately equivalent to the energy storage capacitor discharging through the switch, the graph of the simulated input trigger signal is shown in figure 5. It can be seen that the slope of the trigger curve is relatively shallow near the top M1 of the curve, and if the trigger point is set in the middle of the curve, i.e. near EC/2, the slope of the trigger curve is steepest, at which point the jitter in the output time base of the avalanche pipe is minimal.

In the traditional circuit, because all devices adopted by each stage of avalanche circuit are medium-voltage trigger avalanche transistors, the trigger point with optimal jitter is about one half of the highest trigger voltage. In the front-stage circuit, because the trigger voltage is generated by multiplying the voltage step by inputting a video signal, it is difficult to generate a fast leading edge trigger signal near an optimal trigger point, thereby resulting in poor output time domain stability of the whole link.

The invention changes the first n-grade avalanche transistors into low-voltage trigger avalanche transistors, and the trigger point with the optimal jitter is correspondingly reduced. Therefore, the requirements on the amplitude and the leading edge of the trigger signal are greatly reduced, and the output time domain stability of the whole link is improved.

In order to verify the correctness of the principle analysis and the feasibility of the scheme design, a test block diagram is shown in fig. 6, wherein a signal generated by a crystal oscillator is subjected to digital frequency division to generate a signal with a PRF of 10kHz as a trigger signal, an output of an ultra-wide spectrum source is subjected to an attenuator, a high-speed broadband oscilloscope is used for testing the time domain stability of a pulse source, and a frequency spectrograph is used for testing phase noise.

And connecting a test circuit according to the figure 6, triggering one path of two paths of output of the digital frequency divider as an oscilloscope, triggering the other path of output of the digital frequency divider as an ultra-wide spectrum source, setting the oscilloscope to be in an afterglow display mode, accumulating for 200 times, and measuring the time domain jitter. And then the output of the ultra-wide spectrum source is connected with an attenuator, a 600MHz filter and a spectrometer, and the phase noise of the frequency domain is measured.

As shown in fig. 3, in order to evaluate the effect of the improvement of the present invention, the circuit before the improvement (typical design) and the circuit after the improvement (design of the present invention) were subjected to comparative tests under the same conditions, and the results are shown in table 1. It can be seen that the jitter mean square error of the present invention is reduced from 14ps to 3.9ps, the jitter maximum is reduced from 50ps to 18ps, and the phase noise is reduced from-70 dBc/Hz to-79 dBc/Hz.

TABLE 1 ultra-broad spectrum stability Normal temperature test results

	Jitter mean square error (ps)	Jitter maximum (ps)	Phase noise (dBc/Hz)
				Typical design	14	50	-70
The invention	3.9	18	-79

In order to verify the working stability of the circuit under the environmental condition, the circuit is respectively placed under the environment of minus 40 ℃, minus 10 ℃ and plus 60 ℃ to work, and corresponding tests are carried out, and the results are shown in table 2. It can be seen that the improvement of the present invention at low temperature of-40 ℃ is particularly obvious, the jitter mean square error is reduced from 200ps to 5.78ps, the jitter maximum is reduced from 1000ps to 24ps, and the phase noise is reduced from-50 dBc/Hz to-72.6 dBc/Hz.

TABLE 2 ultra-broad spectrum source stability environmental test results

	Jitter mean square error(ps)	Jitter maximum (ps)	Phase noise (dBc/Hz)
				-40 ℃ according to the invention	5.78	24	-72.6
Typical design at-40 deg.C	200	1000	-50
				At-10 ℃ in the present invention	3.65	15	-76.3
Typical design at-10 deg.C	22	74	-68
				+60 ℃ of the invention	3.14	13	-78.9