阅读说明：本技术 用于感测介质的阻抗变化的半导体装置 (Semiconductor device for sensing impedance change of medium ) 是由 埃尼斯·通杰尔 维卡斯·古普塔 于 2019-10-16 设计创作，主要内容包括：所描述实例包含一种传感器装置,其具有定位在半导体衬底上方的第一导体层(110)的中央垫上的至少一个导电细长第一柱(140),所述第一柱(140)在正交于所述第一导体层(110)的表面的平面的第一方向上延伸。导电细长第二柱(150)以正交定向定位在所述半导体衬底上方的第二导体层(120)上,所述导电细长第二柱(150)处在与所述第一导体层(110)中的通孔开口重合的位置处。所述第二导体层(120)平行于所述第一导体层(110)并通过至少绝缘体层(130)与所述第一导体层(110)间隔,所述导电细长第二柱(150)在所述第一方向上延伸通过所述通孔开口中的相应一者。所述至少一个导电细长第一柱(140)通过间隙与环绕导电细长第二柱(150)间隔。(Described examples include a sensor device having at least one electrically conductive elongated first pillar (140) positioned on a central pad of a first conductor layer (110) over a semiconductor substrate, the first pillar (140) extending in a first direction orthogonal to a plane of a surface of the first conductor layer (110). A conductive elongated second post (150) is positioned in an orthogonal orientation on a second conductor layer (120) above the semiconductor substrate, the conductive elongated second post (150) being at a location coincident with a via opening in the first conductor layer (110). The second conductor layer (120) is parallel to the first conductor layer (110) and spaced from the first conductor layer (110) by at least an insulator layer (130), the conductive elongated second posts (150) extending in the first direction through respective ones of the via openings. The at least one electrically conductive elongated first post (140) is spaced from the surrounding electrically conductive elongated second post (150) by a gap.)

1. A sensor device, comprising:

at least one electrically conductive elongated first pillar having a first height and a first cross section positioned on a central pad of a first conductor layer above a semiconductor substrate, the first pillar extending in a first direction orthogonal to a plane of a surface of the first conductor layer;

a conductive elongated second column having a second height and a second cross-section positioned in an orthogonal orientation on a second conductor layer above the semiconductor substrate, the conductive elongated second column being at a location coincident with a via opening in the first conductor layer, the second conductor layer being parallel to the first conductor layer and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second column extending in the first direction through a respective one of the via openings; and

the at least one conductive elongated first post is spaced from the surrounding conductive elongated second post by a gap.

2. The sensor device of claim 1, wherein the gap is an equal gap.

3. The sensor device of claim 1, wherein the second height is equal to a sum of the first height, a thickness of the first conductor layer, and a thickness of the insulator layer.

4. The sensor device of claim 1, wherein the dielectric medium in the gap comprises molecules that are ionizable by an electric field generated between the at least one conductive elongated first pillar and the conductive elongated second pillar.

5. The sensor device of claim 1, wherein the first conductor layer and the second conductor layer are selected from the group consisting essentially of: a metal; graphene; and doping the semiconductor material.

6. The sensor device of claim 1, wherein the first cross-section and the second cross-section are circular.

7. The sensor device of claim 1, wherein the at least one conductive elongated first post and the conductive elongated second post have smooth surfaces.

8. The sensor device of claim 1, wherein the at least one conductive elongated first post and the conductive elongated second post are a material selected from the group consisting essentially of: doping a semiconductor material; a metal; graphene; and alloys and composites thereof.

9. The sensor device of claim 1, wherein the conductive elongated second post is arranged in a polygon around the at least one conductive elongated first post.

10. The sensor device of claim 9, wherein the polygon is an equilateral polygon selected from the group including triangles, squares, hexagons, and octagons.

11. The sensor device of claim 1, wherein the first height is in a range from about 2 μ ι η to 50 μ ι η.

12. The sensor device of claim 1, wherein the at least one conductive elongated first pillar and the conductive elongated second pillar have a cylindrical shape with a circular perimeter in a range from about 5 μ ι η to 10 μ ι η.

13. The sensor device of claim 4, wherein the dielectric medium is a dielectric medium selected from the group consisting essentially of: air, gases, and biological fluids; and the ionizable molecule is a molecule selected from the group consisting of a water molecule, a gas blend, and a dissolved molecule.

14. The sensor device of claim 1, wherein the gap is in a range from about 2 μ ι η to about 50 μ ι η.

15. A method for manufacturing a sensor device, comprising:

etching a recess into a semiconductor substrate from a first surface of the semiconductor substrate, the recess extending vertically into the semiconductor substrate, the recess having equal depths and having sidewalls at an angle to the first surface, the recess being shaped as a network of pads and interconnects defining a plurality of protrusions of unetched semiconductor material having the first surface, the plurality of protrusions being positioned in a zigzag sequence pattern when viewed in plan view;

filling the recess with a polymeric material until exposed surfaces of the polymeric material are coplanar with the first surfaces of the plurality of protrusions;

forming a first conductor layer by depositing a conductive material having a uniform height onto the first surfaces of the plurality of protrusions;

removing the polymeric material from the groove; and

classifying the plurality of protrusions into a first group and a second group such that each protrusion of the first group is spaced from a protrusion of the second group by a gap, resulting in the protrusions of the first group being surrounded by a circular polygon formed by the protrusions of the second group.

16. The method of claim 15, further comprising:

depositing a second photoresist layer having a thickness onto the first conductor layer on top of each protrusion of the second set;

filling the recess with a first insulating compound until a surface of the insulating compound is coplanar with a surface of the second photoresist layer and simultaneously forming a coplanar layer of the first insulating compound on the first conductor layer of the first set of protrusions, the coplanar layer of the first insulating compound having a first layer thickness;

removing the second photoresist layer;

adding a third photoresist layer having a thickness on top of the surface of the first insulating compound to create sidewalls around the first conductor layer on the second set of protrusions, the height of the sidewalls being the sum of the thickness of the third photoresist layer and the thickness of the first insulating compound layer;

depositing additional conductive material onto the first conductor layer on the second set of protrusions until the conductive material achieves a coplanar surface with the third photoresist layer, thereby forming a second conductor layer parallel to the first conductor layer;

removing the third photoresist layer, thereby exposing a height difference between the surface of the additional conductive material and the surface of the first insulating compound; and

depositing a second insulating compound across the first surface to add a continuous planar insulator layer across the first surface;

wherein the first set of protrusions form a first set of conductive pillars and the second set of protrusions form a second set of conductive pillars spaced apart from the first set of conductive pillars by gaps.

17. The method of claim 16, further comprising:

depositing a spot of an etch stop material layer on a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate, the spot matching locations and matching circular surface areas of the first and second sets of protrusions;

etching the semiconductor material of the semiconductor substrate unprotected by spots of an etch stop material layer, the etching proceeding vertically into the semiconductor substrate from the second surface until reaching the insulating compound, remaining unetched semiconductor material protected by spots of the etch stop material layer forming conductive elongated pillars of semiconductor material having parallel sidewalls and a circular cross section for the protrusions of the first and second sets; and

removing spots of the layer of etch stop material, thereby releasing the surface of the electrically conductive elongated pillars.

18. The method of claim 16, further comprising:

depositing a spot of etch stop material on a second surface of the substrate opposite the first surface of the substrate, the spot of etch stop material matching the location and surface area of the pad and interconnected network used to create the recess defining the circular first and second protrusions;

etching the semiconductor substrate unprotected by the spots of the etch stop material vertically from the second surface into the semiconductor substrate until reaching the deposited conductor, thereby forming a slot with parallel sidewalls through the material of the semiconductor substrate;

filling the slots with a conductive material until a surface of the conductive material is coplanar with a surface of the spot of etch stop material, forming elongated pillars of conductive material having parallel sidewalls, and

removing spots of the etch stop material and underlying material of the semiconductor substrate, releasing the sidewalls of the elongated pillars of conductive material.

19. The method of claim 16, wherein the protrusions have equal size and rounded profile.

20. The method of claim 16, wherein the grooves form equilateral triangles with corresponding grooves of adjacent rows.

21. The method of claim 16, wherein the first and the second conductive materials are selected from the group consisting essentially of metals, alloys, graphene, and doped semiconductor compounds.

22. A packaged semiconductor sensor system, comprising:

a semiconductor device including an integrated circuit for activation, control, and circuitry for analyzing data from an impedance sensor;

an impedance sensor coupled to the integrated circuit, the integrated circuit being selected from the group consisting essentially of: humidity sensor, gas sensor, biological fluid sensor and impedance sensor; wherein the impedance sensor further comprises:

a first group of conductive pillars spaced apart from a second group of conductive pillars by a gap, the first group of conductive pillars forming a first electrode, the second group of conductive pillars forming a second electrode, and the impedance sensor being configured to form an electric field between the first and second electrodes so as to ionize a dielectric medium in the gap; and

the package for a semiconductor device and the sensor, wherein at least a portion of the sensor is exposed to an external environment.

23. The packaged semiconductor sensor system of claim 22, wherein the impedance analysis circuitry is current sensing circuitry having a pulsed voltage input.

24. The packaged semiconductor sensor system of claim 22, wherein the impedance sensor is a humidity sensor.

Background

Sensors for measuring properties of media, such as moisture content, are used in electrical systems. The measurement may be performed by using a material having physical properties that change with humidity, such as polyimide. The material is exposed to a medium, such as air, and the physical property of the material is measured after allowing a time sufficient for a change in the physical property to occur in the material. Humidity sensing in these systems is indirect, i.e., does not measure the humidity content in the medium (e.g., ambient atmosphere); instead, the material is exposed to a medium and then the physical properties of the material sensitive to humidity are measured. Using the correlation between material properties and humidity level, the humidity content in the medium can be derived. For example, a lookup table may be used in which humidity levels are stored with physical measurements of materials known to change with humidity levels (e.g., resistance, conductance, or other measurable property). The system must expose the material to the medium, wait for the material to respond to the medium, measure the physical property change in the medium, and then the system derives the measured property of the medium from the stored measurements or a correlation table. In instances where humidity levels are measured, changes in material response to humidity can occur in indirect sensing systems, resulting in errors in the measurement, as well as delays in making the measurement to allow the material to absorb humidity prior to the measurement.

Disclosure of Invention

In described examples, a sensor device includes a first conductor layer separated from a parallel second conductor layer by an insulator layer having a thickness. The first conductor layer and the insulator layer are patterned with coincident via openings arranged around respective central pads of the first conductor layer. An electrically conductive elongated first post having a first height and a first cross section is positioned on the central pad, the first post being orthogonal to a plane of a surface of the first conductor layer. A conductive elongated second column having a second height and a second cross-section, the second height being equal to the sum of the first height, the thickness of the first conductor layer, and the thickness of the insulating layer, is positioned in an orthogonal orientation on a second conductor layer location coincident with a respective one of the via openings, the second column being perpendicular to the second conductor layer and extending through the respective via opening. The first post is spaced from the surrounding second post by an equal gap. In further described examples, a dielectric medium is in the gap.

Drawings

FIG. 1A illustrates an arrangement of sensor devices; FIG. 1B is an enlarged view of a portion of the sensor device of FIG. 1A.

Fig. 2A and 2B illustrate the arranged conductor layers and elongated pillars in plan and projection views, respectively.

Fig. 3 illustrates in a projection view a set of elongated posts forming part of an arrangement.

Fig. 4A-4B illustrate in a flow chart a method for forming an arranged sensor.

Fig. 5A-5M illustrate in a series of cross-sectional views the results of the steps of the method of fig. 4A-4B in forming an arrangement.

Fig. 6A-6C illustrate, in cross-sectional views, the result of the step of fig. 4B for forming the posts for arrangement.

Fig. 7A-7D illustrate, in additional cross-sectional views, the result of the steps of fig. 4B for an alternative method for forming pillars for arrangement.

Fig. 8A-8B illustrate two alternative packaged sensor device arrangements in two cross-sectional views.

Fig. 9A to 9B illustrate two alternative arrangements for the sensor device in cross-sectional views.

Detailed Description

Corresponding numbers and symbols in the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily to scale.

In this description, the term "column" is a vertical structure such as a vertical column. In this description, the term "elongated post" is a post having the shape of a fiber length whose length is much greater than its width. In this description, the term "electrically conductive elongate post" is an elongate post that is an electrical conductor. Materials for the electrically conductive elongated pillars as described herein include doped semiconductors, metals, graphene or composites of these materials, or composites of other electrically conductive materials. In this description, the term "groove" is a long, narrow cut or indentation in a surface. In an example process for forming an arrangement, a recess is made in a surface of a semiconductor substrate. In this description, "zigzag" means a pattern with alternating directions of abrupt right and left turns. In an example arrangement, the posts are arranged in a zigzag pattern when viewed from a plan view.

In an example arrangement, the problem of sensing a characteristic of a medium is addressed by using direct measurements. Direct measurement is based on ionization of the medium and detection of changes in the impedance of the medium. In an example, the humidity content of the ambient atmosphere may be measured. The ionization current and the conduction in the dielectric medium (e.g., air) at which corona ionization occurs depend on the moisture content of the medium, enabling direct measurement by ionizing the dielectric medium between the electrodes and by observing the current or conduction value. A technical report No. 70106 by b.r. maskel (b.r. maskell) at Royal Aircraft research institute (Royal Aircraft Establishment) presented details of The relationship between ionization current and moisture in Air in "The Effect of moisture on Corona Discharge in Air" (month 6 1970); the report is hereby incorporated by reference herein. In addition to direct humidity sensing of air, impedance change sensing may also be performed on another medium under ionization. These impedance changes can be used to detect humidity in the gas, detect the gas, or perform other sensing using direct sensing. By ionizing the medium, the sensor can perform direct measurements without using a specific humidity sensitive material, and without the need to take indirect measurements after exposing the material to the medium and then waiting for a change in the material. In an arrangement, a structure is formed in which the medium is located between the electrodes in the sensor. The electrodes may be used to ionize a medium. In an example, the structure is a capacitive structure having elongated pillars spaced from each other by gaps, and the dielectric is in the gaps. The use of a capacitive structure with a small feature size enables ionization to occur at small voltages. However, structures can be formed on a larger scale, and a larger voltage can be used to generate an electric field for ionization of the medium. In an example arrangement, the sensor includes a first set of conductive pillars forming a first electrode and a second set of conductive pillars forming a second electrode, the second set of pillars being spaced from the first set of pillars by a gap. A voltage is applied between the electrodes to ionize the medium in the gap. During ionization, a current can be observed and the humidity of the medium can be determined. In another example, the medium is ambient atmosphere or air. Other dielectric media may be in the gap, such as gases and biological fluids; and the ionizable molecules are molecules selected from the group consisting of water molecules, gas mixtures and dissolved molecules.

FIG. 1A illustrates an arrangement of a sensor device for fabrication in combination with a semiconductor device (e.g., an integrated circuit); FIG. 1B illustrates a portion of the sensor device of FIG. 1A in an enlarged view for ease of description. The sensor device in the example arrangement shown is in principle a capacitive structure formed on a semiconductor substrate with unidirectional conductive pillars. As shown in fig. 1A, a dielectric medium 170 (e.g., air) is between the pillars 140, 150. Applying a voltage difference between the positive and negative sides of the structure will allow the dielectric medium between the pillars to ionize. The ionization changes the impedance of the capacitive structure, which is an electrode arrangement formed by conductive pillars. Quantitatively, to achieve ionization, the electric field at the tip of the capacitive structure should exceed 3V/μm; this value can be achieved with relatively large structural features and using relatively large voltages, or with small structural features and using relatively small voltages.

In fig. 1B, a line 101 represents a first surface of an original semiconductor substrate 100 made of a single crystal semiconductor, and a column end surface 102 is a portion of a second surface of the semiconductor substrate. The single crystal semiconductor of substrate 100 is selected from the group consisting of silicon, silicon germanium, gallium arsenide, gallium nitride, and other III-V and II-VI compound semiconductors used in manufacturing. In an example, the pillars, e.g., 140, 150, are bulk portions of a semiconductor substrate. The semiconductor material of the substrate is doped such that the pillars are conductive. Alternatively, in additional arrangements, the posts 140, 150 may be made of metal, graphene, or composites of these materials, or other electrically conductive materials.

As illustrated in fig. 1A and 1B, the first conductor layer 110 is spaced apart from the second conductor layer 120 by an insulator layer 130 that contacts the first and second conductor layers. The first insulator layer has a thickness 130 a. The first conductive layer 110 and the second conductive layer 120 are parallel to each other. As described below, elements of an arrangement are described as being "parallel" to each other when the elements are intended to lie in planes that would not intersect when infinitely extended. However, the term parallel as used herein also encompasses surfaces that may deviate slightly in direction due to manufacturing tolerances, if the two surfaces lie substantially in spaced apart planes and do not intersect when extended indefinitely, then the surfaces are also parallel when made free of these deviations. The parallel surfaces extend side by side in one direction and do not intersect.

The first conductive layer 110 and the second conductive layer 120 are planar. As the term "planar" is used herein, a planar surface lies in a plane and is flat. It should be understood, however, that in manufacturing, some variation in the surface can occur due to tolerances in manufacturing, and that the term planar encompasses surfaces that are intended to be flat and in one plane, even if some deviation occurs in the surface during manufacturing.

A second insulator layer designated 161 in fig. 1B may be formed to protect the conductor layer 120 and provide further mechanical strength to the structure, as described further below. Another insulator 137 is formed around portions of the pillars 140 and 150, as described further below.

Fig. 1A and 1B also illustrate a conductive elongated second pillar 150 having a second height 151 and a second cross section 152 positioned in an orthogonal orientation on each second pillar location on the second conductor layer 120, the second pillar location coinciding with the via opening. Thus, each second post 150 is reached through a respective through-hole opening. The second height 151 is equal to the sum of the first pillar height 141, the thickness of the first conductor layer 110, and the thickness of the insulator layer 130. The second posts 150 are positioned in a vertical orientation to the second conductor layer 120 and extend through respective via openings.

In fig. 2A-2B, like reference numerals are used for elements like those shown in fig. 1A-1B for ease of explanation. The first conductor layer 210 (corresponding to 110 in fig. 1B) and the insulator layer 230 (corresponding to layer 130 in fig. 1B) are illustrated in the top view of fig. 2A and in the perspective view in fig. 2B. The first conductor layer 210 and the insulator layer 230 are patterned by substantially equal-sized and coincident via openings 231 arranged in circular polygons, labeled 233, surrounding respective central pads 232 of the first conductor layer 210. The example circular polygon 233 as illustrated in fig. 2A is a hexagon consisting of six via openings. In other example arrays, the polygon may be an equilateral triangle, square, rectangle, or octagon. The through-hole opening 231 has a preferably circular profile, but other shapes are possible and may be used. Each of the central pads 232 of the first conductive layer 210 has an area sufficient to receive the first pillar 240. As seen in the plan view of fig. 2A, in this illustrated example, the via openings 231 are positioned to be arranged in a zigzag pattern in ordered rows, with sequential rows alternating with a zigzag sequence. In alternative arrangements, other via patterns are possible.

Fig. 1B, 2A and 2B illustrate a conductive elongated first pillar (140 or 240) having a first height (141 or 241) and a first cross-section (142 or 242) positioned on a central pad (232 or 132) of a first conductor layer (210 or 110). In this example, the first pillar (140 or 240) is shown oriented orthogonal to the surface of the first conductor layer (110 or 210). The elements orthogonal to each other have an angle of 90 degrees between the directions in which the respective elements are oriented at the intersections of the elements. As the term "orthogonal" is used herein, it is understood that some variation in manufacturing occurs in the 90 degree angle between the post and the conductor layer due to tolerances in manufacturing. As an example, the first height 141 (see fig. 1B) or 241 may be in a range from about 1 μm to 100 μm.

In fig. 3, like elements to those shown in fig. 1A and 1B are similarly numbered to facilitate understanding. For example, second column 350 in fig. 3 corresponds to second column 150 in fig. 1A-1B. Fig. 1A-1B and fig. 3 illustrate a conductive elongated second column (150 or 350) having a second height (151 or 351) and having a second cross section (152 or 352), the second column being positioned at each second conductor layer (120 or 320) location in an orthogonal direction, coincident with the via opening. Thus, each second post 350 is reached through a respective through-hole opening. The second height (see 151 in fig. 1B) is equal to the sum of the first height 141, the thickness of the first conductor layer 110, and the thickness of the insulator layer (330 or 130). The second posts 350 are positioned in a vertical orientation to the second conductor layer 320 and extend through the respective via openings.

In an example sensor device, the conductive first and second posts may be formed from: doping a semiconductor material; metals such as copper and aluminum; graphene; and composites of these materials. In a later example, some pillars may be partially doped semiconductor and partially metallic.

In the example illustrated in fig. 1A, 1B, 2A, 2B, and 3, the first and second posts have a cylindrical shape, and the first cross-section (142 in fig. 1B) of the first post and the second cross-section (152 in fig. 1B) of the second post are circular; the circular circumference may range from about 2 μm to 25 μm. However, in other examples, the cross-section may be elliptical or have other profiles with substantially smooth surfaces. Examples include cross-sections that are square, rectangular, and polygonal in shape. In addition, the first and second posts have smooth surfaces along the length of the posts. With respect to the term "smooth" as used herein, it is understood that some variation in the surface may occur during manufacturing due to tolerances in manufacturing. In further alternative arrangements, the posts may have tapered sides such that the cross-section at the bottom portion of the post is larger than the cross-section at the top, or the taper may be reversed such that the top portion is larger in cross-section than the cross-section taken at the bottom of the post.

Each first post 140 is spaced apart from the surrounding second post 150 by an equal gap 160 (see fig. 1B). In an example sensor device, the gap is selected in a range from about 2 μm to about 50 μm. The gap is filled with a dielectric medium 170, as indicated by the dots in fig. 1A.

The dielectric medium 170 has an impedance between the pillars and contains molecules that can be ionized by an electric field. Such an electric field may be generated between the first column (140 in fig. 1B) and the second column (150 in fig. 1B) by applying a voltage difference; such fields alter the impedance of the dielectric medium. The dielectric medium may be air, a gas, a fluid, or a biological fluid, and the ionizable molecules comprise water molecules, gas mixtures, and dissolved molecules.

Fig. 4A-4B summarize steps of a manufacturing process flow for an exemplary semiconductor sensor device for packaging a semiconductor device. Some of the process steps are illustrated in a series of cross-sections in fig. 5A through 5M. These steps are followed by fig. 6A to 6C or fig. 7A to 7D in an alternative method. Referring to the process flow beginning in fig. 4A, during step 401 of the process flow, a substrate of semiconductor material is provided. The semiconductor material may be silicon, silicon germanium, gallium arsenide, gallium nitride, other III-V or II-IV compounds, or any other semiconductor compound used in manufacturing. In fig. 5A to 5M, fig. 6A to 6C, or fig. 7A to 7D, reference numerals similar to those of fig. 1A to 1B are used for ease of explanation. For example, in fig. 5A, the substrate 500 corresponds to the substrate 100 in fig. 1A-1B. The substrate 500 may be a semiconductor wafer having a planar first surface 501 and a parallel second surface 502. An integrated circuit (not shown for clarity of explanation) may be fabricated in one of the substrate surfaces, such as in the first surface 501. For example, the integrated circuit may include circuitry to control the operation of the sensor by applying a voltage to the conductive pillars, measuring the impedance between the conductive pillars, and outputting the observed results as data for use by the system.

The next process step defines the creation and patterning of the first conductor layer (see 510 shown in fig. 5E). During step 402 of the process flow of fig. 4A and illustrated in cross-section in fig. 5A, a first photoresist layer 503 is applied to the first surface 501 and patterned such that the remaining area 503 of the photoresist layer determines a future area (510 in fig. 5E) of the first conductor layer. During step 403 and illustrated in fig. 5B, a recess 509 is etched into the bulk of the substrate 500 from the first surface 501 vertically. In an example process, the recess 509 has an equal depth 511, a flat bottom 512, and sidewalls 513 that are perpendicular relative to the first surface 501 oriented in fig. 5A-5M. As used herein, an element is "flat" if it is horizontal, uniform, and smooth. In other arrangements, the grooves may have different shapes. In an example arrangement, the recess may have sloped sidewalls that intersect the plane of the surface of the substrate at an angle and are etched perpendicularly into the substrate. In an example, the groove may be V-shaped and the sidewalls may intersect each other at the bottom of the groove. In manufacturing, some variation may occur in the surface due to manufacturing tolerances, even in surfaces intended to be smooth and uniform. The term "flat" as used herein means a surface that is intended to be smooth and uniform. The grooves 509 are shaped to define a network of pads and interconnects of protrusions 507 of unetched semiconductor material having a first surface 501, in an example, the protrusions 507 are positioned in zigzag in ordered rows, with sequential rows alternating with a zigzag sequence. In this example, the protrusion 507 may be circular in cross-section. In alternative arrangements, the protrusions may be elliptical in cross-section or have another shape.

Referring again to the process flow of fig. 4A, during step 404 and illustrated in fig. 5C, the first photoresist layer 503 is removed from the protrusion 507. During step 405 and illustrated in fig. 5D, the grooves 509 are filled with the polymer material 523 until the surface 521 of the polymer material 523 is coplanar with the first surface 501 of the protrusion 507.

In the description that follows, certain elements are described as being "coplanar". The coplanar members lie in the same plane. However, in manufacturing, some variation in surface height occurs due to manufacturing tolerances. The term "coplanar" as used herein means that two elements are intended to lie in the same plane, even if the slight difference in one or the other of the manufactured surfaces is slightly out of plane. Elements positioned such that the surfaces of the two elements are intended to lie in a common plane are coplanar.

During step 406 of the process flow in fig. 4A and illustrated in fig. 5E, a first conductor layer 510 is formed by depositing a conductive material having a uniform height onto the first surface 501 of the protrusion 507. The conductive material for the first conductor layer may include metals (e.g., copper and aluminum), metal alloys, graphene, and doped semiconductor materials. During step 407 of the process flow in fig. 4A and illustrated in fig. 5F, the polymeric material 523 in the recess 509 is removed, thereby re-opening the recess 509 and releasing the protrusion 507, with the first conductor layer 510 on the first surface 501.

During step 408 of the process flow in fig. 4A, the plurality of protrusions 507 are classified into a first group and a second group. The sorting is performed such that the protrusions of the first group are spaced apart from the protrusions of the second group by gaps. In the depicted example, the gaps (see 160 in FIG. 1A) are equal. In an alternative arrangement, unequal gaps may be used. In fig. 5F, the protrusions of the first group are marked with the indicator "I" and the protrusions of the second group are marked with the indicator "II". A one-dimensional example of a similar classification is illustrated in fig. 1A by the columns positioned along line a-a. The two-dimensional result of this classification of protrusions is a configuration of protrusions in which the protrusions of the first group are surrounded by a circular polygon formed by the protrusions of the second group. An example is illustrated in fig. 2A by a circular polygon 233.

During step 409 of the process flow in fig. 4A and illustrated in fig. 5G, a second photoresist layer 562 is deposited onto the first conductor layer 510 on top of each protrusion of the second set of protrusions (designated as II). The second photoresist layer has a surface 562a and a thickness 562 b.

During step 410 of the process flow in fig. 4A and illustrated in fig. 5H, the recess (509 in fig. 5G) is filled with a first insulating compound 530. In an example, compound 530 is a dielectric material, such as silicon oxide SiO_x(e.g. SiO)₂). Other insulators used as dielectric materials in semiconductor processing may be used. The filling process continues until the surface 530a of the insulating compound is coplanar with the surface 562a of the second photoresist layer 562. Due to this filling method and simultaneously with this filling process, a coplanar layer 530 of a first insulating compound is formed on the conductor layer 510 across the first set of bumps (designated as I). First insulating compound530 are referred to herein as first insulator layers (the portion of the first layer visible in fig. 1B is designated 130). The first insulator layer 530 has a thickness 530b over the first set of protrusions that is equal to the thickness 562b of the photoresist layer 562 (see fig. 5G).

During step 411 of the process flow in fig. 4A and illustrated in fig. 5I, the second photoresist layer (see 562 in fig. 5H) is removed. Now, the insulator layer has two differently shaped portions; the portions 530 are those portions between the second set of protrusions II and the portions 531 are those portions above the first set of protrusions I. Thus, a height difference corresponding to the thickness 531b is formed between the surface portion occupied by the first insulator layer 531 and the surface portion exhibiting the unprotected surface of the first conductor layer 510. The next process step of the method will amplify these height differences. It should be noted that the process flow of fig. 4A continues in fig. 4B.

To magnify the height difference during step 412 of the process flow in fig. 4B, and illustrated in fig. 5J, a third photoresist layer 553 is created and added on top of all surfaces of the first insulating compound 530 (including on top of the portion of the first insulator layer 531). The third photoresist layer 553 has a thickness 553 b. As illustrated in fig. 5J, the third photoresist layer 553 is combined with the first insulating compound 530 to form sidewalls 541 around each of the conductor layers 510 on the second set of protrusions II. The height of the sidewalls 541 is the sum of the thickness 553b of the third photoresist layer 553 and the thickness 531b of the portion of the first insulator layer labeled 531.

During step 413 of the process flow in fig. 4B and illustrated in fig. 5K, additional conductive material 520 is deposited on the first conductor layer 510 of the second set of bumps (labeled II). The conductive material 520 may include metals, metal alloys, graphene, and doped semiconductor compounds. Conductive material 520 may be identical to conductive material 510; as an example, conductive material 510 and conductive material 520 include copper and/or copper alloys. The deposition continues until the added conductive material 520 achieves a surface 520a that is coplanar with the surface 553a of the third photoresist layer 553. The added conductive material forms a second conductor layer 520 parallel to the first conductor layer 510.

During step 414 of the process flow in fig. 4B and illustrated in fig. 5L, the third photoresist layer 553 is removed. Accordingly, a height difference 520b is formed between the surface 531a of the portion of the first insulator layer 531 and the surface 520a of the conductive material 520. The next process step aims at leveling these height differences.

During step 415 of the process flow in fig. 4B and illustrated in fig. 5M, another insulating material is deposited across the surfaces of the first insulator layer 531 and portions of the conductive material 520, leveling the height difference and additionally covering the entire first substrate surface. In addition, another layer of insulating compound 559 adds a continuous planar insulating layer 561 of thickness 561b, designated as insulator layer 561, across a region of the first substrate surface. The new "first" surface of the substrate 500 is insulating and is designated 561 a. For reasons of mechanical stability and protection, it is advantageous for some applications (see the corresponding layer 161 in fig. 1B) to provide the insulating layer (561 in fig. 5M) with a relatively large thickness.

At this stage of the process flow, there are two options for processes for creating conductive pillars or electrodes of sensor devices: the first method uses a conductive semiconductor of the substrate to create the pillars; this process is illustrated by a series of cross-sections showing the process steps in fig. 6A-6C and corresponds to steps 416A, 417A, 418A in fig. 4B. The second method replaces the conductive semiconductor material by another conductive material, such as a metal. This method is illustrated in cross-section with process steps shown in fig. 7A-7D, and corresponds to process steps 416B-420B in fig. 4B. It should be noted that the reference labels for similar elements in fig. 6A to 6C are similar to those in fig. 5A to 5M for ease of explanation. For example, the substrate 600 corresponds to the substrate 500.

Following the first approach, during step 416A of the process flow in fig. 4B and illustrated in fig. 6A, a layer 675 of etch stop material is deposited in spots on the second surface 602 of the substrate 600, which match the locations and surface areas of the protrusions of the first set (labeled I) and the protrusions of the second set (labeled II). As mentioned above, the surface area of the protrusions may be rounded.

During step 417A of the process flow of fig. 4B and illustrated in fig. 6B, the semiconductor material of the semiconductor substrate 600 (see fig. 6A) is etched in locations not protected by the etch stop spot 675. Preferably, the etching process uses a chemical solution suitable for preferentially etching the selected crystal orientation of the single crystal substrate 600. The etching process proceeds vertically from the second surface 602 into the bulk of the substrate 600 and continues until the insulating compound 630 is reached. At this point, the etching process stops because the remaining unetched semiconductor material is protected by insulator 630. As shown in fig. 6B, the etching process forms elongated first pillars 640 in the locations of the protrusions I of the first set and second pillars 650 in the locations of the protrusions II of the second set. The sidewalls of the pillars (640 a and 650a, respectively) are parallel and smooth due to preferential etching along the crystal orientation. It is also preferred that the post has a circular cross-section.

During step 418A of the process flow in fig. 4B, and illustrated in fig. 6C, the etch stop layer 675 is removed, exposing the tops of the pillars. As a result, all surfaces of the elongated conductive posts (640 for the first set of protrusions, 650 for the second set) are free to participate as electrodes when an electrical bias is applied.

Following the second route, during step 416B of the process flow in fig. 4B, and illustrated in fig. 7A, a layer 771 of etch stop material is deposited in spots on the second surface 702 of the substrate 700, matching the locations and surface areas of the network of pads and interconnects used to create the recesses 509 (in fig. 7A, the recesses 731 are shown filled with a first insulating compound 730). As discussed earlier, since the recesses 709 define the first set I and second set II of rounded protrusions, the etch stop layer leaves the rounded surface area unprotected. The layer 771 of etch stop material has a surface 771 a.

During step 417B of the process flow in fig. 4B, and illustrated in fig. 7B, portions of the semiconductor material of the substrate 700 not protected by the etch stop layer 771 are etched (see fig. 7A). Preferably, the etching process uses a chemical solution suitable to preferentially etch a selected crystal orientation of the single crystal substrate 700. The etching process proceeds vertically from the second surface 702 into the bulk of the substrate 700, etching away the group I and group II protrusions, and continues until reaching the deposited conductor 710. At this point, the etching process is complete. As shown in fig. 7B, the etching process has produced a slot 709 with parallel sidewalls 780a and 780B. Along the length, sidewall portions are composed of the semiconductor material 780 of the substrate 700 and portions are composed of the first insulating compounds 730 and 731. The sidewalls of the slots 709 are smooth due to the way the preferred etchant attacks the crystal orientation. For many products, the slots preferably have a circular cross-section. In alternative arrangements, the cross-section may be elliptical or have other shapes.

During step 418B of the process flow in fig. 4B, and illustrated in fig. 7C, the entire length and width of the slots 709 (see fig. 7B) are filled with conductive material 740 and 750 for the first and second sets of protrusions. The fill process continues until the surface 750a of the conductive material is coplanar with the surface 771a of the etch stop layer 771. As a result, illustrated in fig. 7C, the filling process forms elongated pillars 740, 750 comprised entirely of conductive material; the posts have parallel sidewalls. The conductive material may be a metal, a metal alloy, graphene, and a doped semiconductor compound. Examples of metals are copper and aluminum and alloys of copper and aluminum. Preferably, the conductive material in the pillars 740, 750 is identical to the conductive material 110 (in fig. 1A) and the conductive material 720; as an example, conductive material 750 and conductive materials 7100 and 720 comprise copper.

During step 419B of the process flow in FIG. 4B, and illustrated in FIG. 7D, the etch stop layer 771 is removed. Thereafter, during step 420B of the process flow in fig. 4 and also illustrated in fig. 7D, the semiconductor material 780 previously protected by the etch stop layer 771 is also removed (see fig. 7C), thereby releasing the sidewalls 750B of the conductive material. As a result, elongated pillars 740, 750 have been created, which are all composed of an electrically conductive material (e.g., metal). The plurality of columns 740, 750 includes column 740 designated with label I in place of first column 140 in fig. 1A and 1B, and column 750 designated with label II in place of second column 150 in fig. 1A and 1B. When electrically biased, pillars 740 and 750 may operate as first and second electrodes using group I and group II pillars. When the medium (170 in fig. 1A) is ionized between the electrodes by an electrical bias, a change in impedance can be sensed. In an example, the humidity content of the air may be determined using ionization. Gas concentration, blood gas concentration, fluid chemistry, and other measurements may also be performed similarly.

Fig. 8A-8B illustrate a packaged sensor device in cross-sectional view. In fig. 8A, a wire bond package sensor device arrangement 800 is shown. A substrate 807, such as a copper lead frame or other substrate for an electronic package, is shown having a semiconductor device 801 attached on a first surface by a die attach adhesive 805. Pads 813 on the substrate are coupled to bond pads 815 on the active surface of the semiconductor device 801 by bond wires 811. A molding compound, such as epoxy, polyimide, epoxy, or thermoset epoxy, forms a portion 817 that covers the bonding wire 811 and the first surface of the substrate 807. The remaining portion of the substrate 807 is exposed from the molding compound 817 and may form external terminals (not shown for simplicity of illustration) of the arrangement 800. The sensor 803 is shown formed on an active surface of the semiconductor device 801 and exposed from the molding compound portion 817 to enable the sensor to allow a medium (e.g., ambient environment) to be present in the gaps between the conductive pillars where ionization can occur.

Fig. 8B illustrates in a similar cross-sectional view a packaged sensor device arrangement 802 similar to that of fig. 8A using a flip-chip mounted semiconductor device 801. The package of arrangement 802 has semiconductor device 801 (with respect to package 800) mounted "face down"; such that the sensor 803 extends down towards the system board (not shown) where the packaged sensor device 802 is to be surface mounted. The solder 823, which may be solder balls with solder bumps or conductive pillar bumps, forms a connection between bond pads on the active surface of the semiconductor device 801 and the substrate 819, which may be a printed circuit board, ceramic, laminate, tape, or film, and which may carry a layer of conductors such as a redistribution layer. Solder balls 821 are coupled to pads on the outer surface of substrate 819 to provide electrical terminals of packaged sensor device arrangement 802. The package may be sealed using a molding compound, epoxy, or resin 818 to cover portions of the semiconductor device 801 while exposing the conductive pillars of the sensor 803 to the environment.

Fig. 9A and 9B illustrate two possible arrangements of sensors and semiconductor devices in cross-sectional views. In the arrangement 900 shown in fig. 9A, the sensor 903 includes a conductive post extending toward a system board (not shown), where the semiconductor device 901 is to be mounted using solder balls 923. In fig. 9B, in an alternative arrangement 902, the sensors 903 are oriented on opposite sides of the semiconductor device 901, and the conductive pillars are pointed away from a system board (not shown) to which the semiconductor device 901 is to be surface mounted using solder balls 925.

In each of fig. 8A-8B, 9A-9B, a semiconductor device (801 or 901) may provide a sensor 803, 903. In some example arrangements, the semiconductor device 801 or 901 may include additional integrated circuitry. For example, a controller or processor may be provided on the same semiconductor device 801, 901 as the sensor 803, 903, and a bias voltage may be applied to the conductive pillars. In an additional alternative, the semiconductor devices 801, 901 in figures 8A-8B, 9A-9B may be discrete sensor devices that may be coupled to other integrated circuits (not shown) that provide the control and voltages needed to operate the sensors. The measurement of current, voltage, and/or conductivity enables direct measurement of the dielectric during ionization, which the processor may use to directly measure the moisture or humidity of air or another dielectric in an illustrative example.

Modifications are possible in the described arrangements and other alternative arrangements are possible within the scope of the claims.