阅读说明：本技术 采用混合半导体技术的rcc电路 (RCC circuit using hybrid semiconductor technology ) 是由 王玉雯 雷建明 肖佳伟 庄宗其 王梓人 张文秀 杜佳 于 2021-03-17 设计创作，主要内容包括：本发明公开一种采用混合半导体技术的RCC电路,涉及开关电源领域,电路采用了LDMOS器件和GaN基HEMT器件,提高电路工作频率至数百kHz。两种类型器件采用了同一个硅衬底,三晶体管共用一个晶圆,减小体积、提升可靠性控制。电路通过第三辅助绕组N-a,采用正反馈模式的自激驱动腔自动为Si基LDMOS器件Q3提供驱动信号,无须控制芯片。采用了集成式的高频电流逐周期检测方案,与自激驱动腔共用一个线圈,省去了电流检测电阻,实现了无损耗电流检测。电路还采用了积分反馈法实现原边反馈,通过在关断时间内,对第一GaN HEMT器件Q1漏极电压进行积分计算,间接获取输出电压信息,从而实现对输出电压的实时精确调控。(The invention discloses an RCC circuit adopting a hybrid semiconductor technology, and relates to the field of switching power supplies. The two types of devices adopt the same silicon substrate, and three transistors share one wafer, so that the size is reduced, and the reliability control is improved. The circuit passes through the third auxiliary winding N a The self-excitation driving cavity adopting the positive feedback mode automatically provides a driving signal for the Si-based LDMOS device Q3 without a control chip. The integrated high-frequency current cycle-by-cycle detection scheme is adopted, and the high-frequency current cycle-by-cycle detection scheme and the self-excitation driving cavity share one coil, so that a current detection resistor is omitted, and lossless current detection is realized. The circuit also adopts an integral feedback method to realize primary side feedback, and the voltage of the drain electrode of the first GaN HEMT device Q1 is subjected to integral calculation within the turn-off time to indirectly obtain the output voltage information, so that the real-time accurate regulation and control of the output voltage are realized.)

1. An RCC circuit adopting a hybrid semiconductor technology is characterized by comprising a first GaN HEMT device Q1, a second GaN HEMT device Q2, a Si-based LDMOS device Q3, a power circuit main transformer and a self-excitation driving and cycle-by-cycle detection circuit, wherein the drain electrode of the Si-based LDMOS device Q3 is connected with the source electrode of the first GaN HEMT device Q1, the source electrode of the Si-based LDMOS device Q3 is grounded, the drain electrode of the second GaN HEMT device Q2 is connected with the grid electrode of the Si-based LDMOS device Q3, and the source electrode of the second GaN HEMT device Q2 is also grounded;

the switch control of the first GaN HEMT device Q1 adopts a source electrode driving scheme, the switch of the first GaN HEMT device Q1 is indirectly controlled by controlling the switch of the Si-based LDMOS device Q3 connected in series with the source electrode driving scheme, a driving signal of the Si-based LDMOS device Q3 is provided by a third auxiliary winding Na of a main transformer of a power circuit and a self-excitation driving cavity in a positive feedback mode, and the self-excitation driving and cycle-by-cycle detecting circuit is formed by an integrated high-frequency current cycle-by-cycle detecting circuit and a self-excitation driving cavity which share one coil and is connected with a VCC voltage source.

2. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the Si-based LDMOS device Q3 is connected with a high-voltage starting resistor with the resistance value of 680k omega-3M omega, and the grid electrode of the Si-based LDMOS device Q3 is further connected with a first protection voltage-regulator tube Dz 1.

3. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the driving of the Si-based LDMOS device Q3 is provided by the third auxiliary winding Na via a dc blocking capacitor C1 and a positive feedback resistor R1.

4. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the first GaN HEMT device Q1, the second GaN HEMT device Q2 and the Si-based LDMOS device Q3 share one wafer, and the first GaN HEMT device Q1 and the second GaN HEMT device Q2 adopt the same silicon substrate.

5. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the first GaN HEMT device Q1 adopts a depletion mode device, the threshold voltage is less than 1V, the second GaN HEMT device Q2 adopts an enhancement mode device, and the threshold voltage range is 1-1.5V.

6. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the VCC voltage source first level forms the loop and constitutes by third auxiliary winding Na, second electric capacity C2 and third diode D3, VCC voltage source second level forms the loop and constitutes by second electric capacity C2, fourth diode D4 and third electric capacity C3.

7. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the gate driving signal of the Si-based LDMOS device Q3 is transmitted to the gate of the second GaN HEMT device Q2 through the second voltage regulator Dz2, the third resistor R3 and the fourth resistor R4.

8. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the secondary side output voltage of the main transformer of the power circuit is sent to the grid electrode of the second GaN HEMT device Q2 through an eighth resistor R8 through an isolation feedback network.

9. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the secondary side output voltage of the main transformer of the power circuit does not need to pass through an isolation feedback network, the voltage of the drain electrode voltage of the first GaN HEMT device Q1 in the turn-off time is detected through an integration method through a third voltage regulator Dz3, a sixth resistor R6, a fifth capacitor C5 and a seventh resistor R7, and then the voltage is sent to the grid electrode of the second GaN HEMT device Q2 through an eighth resistor R8.

10. An RCC circuit using hybrid semiconductor technology according to claim 1, wherein: the first GaN HEMT device Q1 and the second GaN HEMT device Q2 adopt an integrated antiparallel diode structure.

Technical Field

The invention relates to the field of switching power supplies, in particular to an RCC circuit adopting a hybrid semiconductor technology.

Background

In low power situations, less than 75W, flyback converters have grown to dominate the market. One particular circuit form in a flyback converter is a self-excited flyback converter, also known as an RCC converter. The RCC converter works through self-excited oscillation, the frequency is not fixed, the influence of the parameters of the device and the stray parameters of the circuit on the RCC converter is large, and the reliability of the circuit is greatly challenged when the switching device works in a quasi-saturation state. With the high-speed development of integrated circuits, the RCC converter is slowly marginalized, and generally, the RCC converter is only used for low-cost applications of 25W or even below 15W, which is difficult to break through.

On the other hand, the development of devices has been restraining the evolution of the switching power supply circuit, and with the appearance of the LDMOS (MOS device with lateral double diffusion structure) and the GaN HEMT device (gallium nitride based high electron mobility transistor), the switching power supply circuit has a new development breakthrough. Due to the high band gap and the large conduction band difference of the GaN/AlGaN material, the GaN HEMT device can bear higher working high pressure than a conventional silicon-based MOS device, has small conduction loss, high working frequency, good temperature resistance stability and the like, and the LDMOS also has the advantages of high pressure resistance, good temperature resistance characteristic, high frequency and the like, is particularly suitable for improving the working reliability of the RCC converter, expanding the power level of the RCC converter and enabling the RCC circuit to be expected again. However, the threshold voltage of the GaN HEMT device is lower than that of the conventional silicon-based MOS device, and is only about 1.0-1.5V, the gate voltage tolerance is also only about 7V, and in addition, the high-frequency operating characteristics of the device greatly increase dv/dt and di/dt of the device operation, so that the driving of the device needs to be redesigned.

Disclosure of Invention

The invention aims to provide an RCC circuit adopting a hybrid semiconductor technology, which has the main part completely the same as that of the traditional RCC circuit, but has innovations in a feedback mode, a nondestructive current detection mode, a main power tube driving mode and a slope compensation mode, improves the working frequency of the RCC circuit, expands the application power level of the circuit, and simultaneously provides a brand-new self-excitation driving scheme for GaN HEMT and LDMOS devices without an additional driving chip; meanwhile, the method has the advantages of realizing lossless and small loop by high-frequency current detection, directly controlling the stability of the secondary output voltage on the primary side, expanding the duty ratio from 0.4 to 0.55, expanding the working frequency from 100kHz to hundreds of kHz, along with low cost, small size and the like.

An RCC circuit adopting a hybrid semiconductor technology comprises a first GaN HEMT device Q1, a second GaN HEMT device Q2, a Si-based LDMOS device Q3, a power circuit main transformer and a self-excitation driving and cycle-by-cycle detection circuit, wherein the drain electrode of the Si-based LDMOS device Q3 is connected with the source electrode of the first GaN HEMT device Q1, the source electrode of the Si-based LDMOS device Q3 is grounded, the drain electrode of the second GaN HEMT device Q2 is connected with the grid electrode of the Si-based LDMOS device Q3, and the source electrode of the second GaN HEMT device Q2 is also grounded;

the switch control of the first GaN HEMT device Q1 adopts a source electrode driving scheme, the switch of the first GaN HEMT device Q1 is indirectly controlled by controlling the switch of the Si-based LDMOS device Q3 connected in series with the source electrode driving scheme, a driving signal of the Si-based LDMOS device Q3 is provided by a third auxiliary winding Na of a main transformer of a power circuit and a self-excitation driving cavity in a positive feedback mode, and the self-excitation driving and cycle-by-cycle detecting circuit is formed by an integrated high-frequency current cycle-by-cycle detecting circuit and a self-excitation driving cavity which share one coil and is connected with a VCC voltage source.

Preferably, the Si-based LDMOS device Q3 is connected with a high voltage starting resistor with a resistance value of 680k Ω -3M Ω, and the gate of the Si-based LDMOS device Q3 is further connected with a first protection voltage regulator Dz 1.

Preferably, the driving of the Si-based LDMOS device Q3 is provided by the third auxiliary coil Na via a dc blocking capacitor C1 and a positive feedback resistor R1.

Preferably, the first GaN HEMT device Q1, the second GaN HEMT device Q2 and the Si-based LDMOS device Q3 share one wafer, and the first GaN HEMT device Q1 and the second GaN HEMT device Q2 use the same silicon substrate.

Preferably, the first GaN HEMT device Q1 is a depletion mode device with a threshold voltage < 1V, and the second GaN HEMT device Q2 is an enhancement mode device with a threshold voltage in the range of 1-1.5V.

Preferably, the first stage of the VCC voltage source forms a loop formed by the third auxiliary winding Na, the second capacitor C2 and the third diode D3, and the second stage of the VCC voltage source forms a loop formed by the second capacitor C2, the fourth diode D4 and the third capacitor C3.

Preferably, the gate driving signal of the Si-based LDMOS device Q3 is transmitted to the gate of the second GaN HEMT device Q2 through the second voltage regulator Dz2, the third resistor R3 and the fourth resistor R4.

Preferably, the secondary side output voltage of the main transformer of the power circuit is sent to the gate of the second GaN HEMT device Q2 through an eighth resistor R8 via an isolation feedback network.

Preferably, the secondary side output voltage of the main transformer of the power circuit is detected by an integration method through a third regulator Dz3, a sixth resistor R6, a fifth capacitor C5 and a seventh resistor R7 without an isolation feedback network, and the voltage of the drain voltage of the first GaN HEMT device Q1 at the turn-off time is sent to the gate of the second GaN HEMT device Q2 through an eighth resistor R8.

The invention has the advantages that:

1. through the on-chip structure design of the double-GaN HEMT + LDMOS device and the adoption of the Si substrate, the difficulty in process realization is reduced;

2. the GaN HEMT depletion type main power tube is connected with the LDMOS in series, so that the driving difficulty of a GaN HEMT device is reduced, the defects of low grid voltage resistance, small threshold voltage and large driving current of the GaN HEMT device are overcome, and the working frequency of the circuit can be increased to hundreds of kHz;

3. the self-excitation driving of the power switch tube is realized through the third auxiliary coil, meanwhile, the closed-loop control function of the circuit is completely realized through discrete components, a third-party driving chip is not needed, and the circuit cost is reduced by at least 20%;

4. the function of high-frequency cycle-by-cycle current detection is multiplexed by the third auxiliary coil, so that the lossless detection of current is realized, the circuit efficiency is improved by at least 0.2%, and more importantly, the loop area in PCB layout is reduced, so that the high-frequency noise is reduced;

5. primary side feedback is realized by adopting an integral feedback method, and the output voltage can be stabilized without secondary side isolation feedback;

6. introducing slope compensation by gate drive expands the duty cycle from 0.4 to 0.55.

Drawings

FIG. 1 is a schematic diagram of the circuit of the present invention;

FIG. 2 is a schematic diagram of a specific circuit of a first embodiment of the present invention;

FIG. 3 is a schematic diagram of a specific circuit of a second embodiment of the present invention;

FIG. 4 is a schematic diagram of a conventional chip + silicon-based MOSFET + Flyback circuit;

FIG. 5 is a schematic diagram of a conventional Si-based bipolar transistor + RCC circuit;

fig. 6 is a conventional Si-based MOSFET + RCC circuit.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.

1-3, an RCC circuit employing hybrid semiconductor technology includes a first GaN HEMT device Q1, a second GaN HEMT device Q2, a Si-based LDMOS device Q3, a power circuit main transformer, and a self-excited drive and cycle-by-cycle detection circuit, the drain of the Si-based LDMOS device Q3 is connected to the source of the first GaN HEMT device Q1, and the HEMT of the Si-based LDMOS device Q3 is grounded, the drain of the second GaN device Q2 is connected to the gate of the Si-based LDMOS device Q3 and the source of the second GaN HEMT device Q2 is also grounded;

the switch control of the first GaN HEMT device Q1 adopts a source electrode driving scheme, the switch of the first GaN HEMT device Q1 is indirectly controlled by controlling the switch of the Si-based LDMOS device Q3 connected in series with the source electrode driving scheme, a driving signal of the Si-based LDMOS device Q3 is provided by a third auxiliary winding Na of a main transformer of a power circuit and a self-excitation driving cavity in a positive feedback mode, and the self-excitation driving and cycle-by-cycle detecting circuit is formed by an integrated high-frequency current cycle-by-cycle detecting circuit and a self-excitation driving cavity which share one coil and is connected with a VCC voltage source.

The Si-based LDMOS device Q3 is connected with a high-voltage starting resistor with the resistance value of 680k omega-3M omega, and the grid electrode of the Si-based LDMOS device Q3 is further connected with a first protection voltage-regulator tube Dz 1.

The driving of the Si-based LDMOS device Q3 is provided by the third auxiliary winding Na via a dc blocking capacitor C1 and a positive feedback resistor R1.

The first GaN HEMT device Q1, the second GaN HEMT device Q2 and the Si-based LDMOS device Q3 share one wafer, and the first GaN HEMT device Q1 and the second GaN HEMT device Q2 adopt the same silicon substrate.

The first GaN HEMT device Q1 adopts a depletion mode device, the threshold voltage is less than 1V, the second GaN HEMT device Q2 adopts an enhancement mode device, and the threshold voltage range is 1-1.5V.

The VCC voltage source first level forms the loop and constitutes by third auxiliary winding Na, second electric capacity C2 and third diode D3, VCC voltage source second level forms the loop and constitutes by second electric capacity C2, fourth diode D4 and third electric capacity C3.

The gate driving signal of the Si-based LDMOS device Q3 is transmitted to the gate of the second GaN HEMT device Q2 through the second voltage regulator Dz2, the third resistor R3 and the fourth resistor R4.

The secondary side output voltage of the main transformer of the power circuit is sent to the grid electrode of the second GaN HEMT device Q2 through an eighth resistor R8 through an isolation feedback network.

The secondary side output voltage of the main transformer of the power circuit does not need to pass through an isolation feedback network, the voltage of the drain electrode voltage of the first GaN HEMT device Q1 in the turn-off time is detected through an integration method through a third voltage regulator Dz3, a sixth resistor R6, a fifth capacitor C5 and a seventh resistor R7, and then the voltage is sent to the grid electrode of the second GaN HEMT device Q2 through an eighth resistor R8.

The specific implementation mode and principle are as follows:

as shown in fig. 4, in a Flyback (Flyback) application circuit, a chip control mode is mainly adopted at present. In the circuit, a field effect transistor (MOSFET) is used as a main switching tube, and the working duty ratio of the field effect transistor (MOSFET) is controlled by an integrated control chip. The control chip mainly collects a cycle-by-cycle Current Signal (CS) passing through a field effect transistor (MOSFET) and a voltage feedback signal (FB) generated by secondary side output, supplies VCC power through an auxiliary winding, and outputs a driving signal (DRV) to control the duty ratio of the field effect transistor (MOSFET). There are many control modes of the chip, such as a continuous working mode (CCM), a discontinuous working mode (DCM), a quasi-resonant working mode (QR), and a hybrid working mode. However, the significant problem is the high cost of the integrated chip.

As shown in fig. 5, in a Flyback (Flyback) application circuit with a small current output of 10W or less, an RCC (self-excited Flyback converter) circuit is often used. In the circuit, a Bipolar Junction Transistor (BJT) Q1 is used as a main switching tube, the driving and working duty ratio of the Q1 are controlled by a peripheral circuit, a control chip is not needed, and the cost is greatly saved. Q1 is first passed through R by the bus voltage_staWhen the current-limiting drive is started, after the Q1 is started, the current flowing through the Q1 is caused by the primary inductance N of the transformer_pWhile the auxiliary winding Na provides a continuous drive to Q1 through the current limiting resistor R1 and the dc blocking capacitor C1. When the current flowing through Q1 is increased to make R_sThe voltage on triggers Q2 to turn on, Q2 pulls the base drive signal of Q1 low, so that Q1 stops turning on and turns to an off state. At the same time, the voltage feedback signal (FB) generated by the secondary output also superimposes the base level of Q2, thereby affecting the timing of Q1 turn-off. After the Q1 is switched off, the level of the auxiliary winding Na is also reversed, and the charge on the base of the Q1 is quickly pumped away by the C1 and the R1, so that the Q1 is switched off in an accelerated way. When the output current drops to 0, no current flows through the D2, so that the Ns coil is automatically decoupled from the output, the primary inductor Np resonates with the output junction capacitance of the Q1, and when the level of Np is inverted, that is, the level of Na is inverted again, the Q1 is triggered to be automatically turned on again through the R1 and the C1. The circuit works in a quasi-resonance mode, realizes zero-current soft switching, has higher working efficiency, and has the defect that Q1 power capability adopting BJT is lower, so that the circuit is not suitable for occasions with higher power.

As shown in fig. 6, this scheme is very similar to the scheme shown in fig. 5, and only uses MOS transistors to replace BJT transistors, and utilizes the characteristics of MOS transistors such as large power and high frequency to expand the power level of the circuit, so that it can be used in applications of 10W or more, and even as high as 50W. In addition, compared with BJT (bipolar junction transistor), the MOS transistor has no problem of secondary breakdown, and the reliability of the MOS transistor is greatly improved.

As shown in fig. 1, the present invention employs a novel LDMOS device (MOS device having a lateral double diffusion structure) and a GaN-based HEMT (high electron mobility transistor) device, increasing the circuit operating frequency to several hundred kHz. The two types of devices adopt the same silicon substrate, and three transistors share one wafer, so that the size is reduced, the cost is reduced, and the reliability control is improved. The on and off control of the first GAN HEMT device Q1 adopts a source driving scheme to indirectly control the on and off of the first GAN HEMT device Q1 by controlling the on and off of the SI-based LDMOS device Q3 connected in series therewith. The circuit passes through a third auxiliary winding N in a main transformer of the power circuit_aThe self-excitation driving cavity adopting the positive feedback mode automatically provides a driving signal for the SI-based LDMOS device Q3 without a control chip. The circuit further adopts an integrated high-frequency current cycle-by-cycle detection scheme, and the high-frequency current cycle-by-cycle detection scheme and the self-excitation driving cavity share one coil, so that a current detection resistor is omitted, and lossless current detection is realized. The circuit also adopts an integral feedback method to realize primary side feedback, and the voltage of the drain electrode of the Q1 of the first GAN HEMT device is subjected to integral calculation within the turn-off time to indirectly obtain the output voltage information, so that the real-time accurate regulation and control of the output voltage are realized.

More specific embodiment is shown in fig. 2, in the embodiment, the first GAN HEMT device Q1 and the second GAN HEMT device Q2 both adopt GAN HEMT devices, and the SI-based LDMOS device Q3 adopts a SI-based LDMOS device. The first GAN HEMT device Q1 and the SI-based LDMOS device Q3 are connected in series, namely the drain electrode of the SI-based LDMOS device Q3 is connected with the source electrode of the first GAN HEMT device Q1, and the source electrode of the SI-based LDMOS device Q3 is grounded; the drain of the second GAN HEMT device Q2 is connected to the gate of the SI-based LDMOS device Q3 and the source is also connected to ground. The GaN HEMT device and the LDMOS device both adopt Si substrates, and on-chip integrated design is realized. In addition, the first GAN HEMT device Q1 is a depletion mode device with a threshold voltage < -1V, while the second GAN HEMT device Q2 is an enhancement mode device with a threshold voltage in the range of 1-1.5V. The series operating principle of the first GAN HEMT device Q1 and the SI-based LDMOS device Q3 is the same as that of the conventional Cascade structure. The driving of the SI-based LDMOS device Q3 is provided by the third auxiliary winding Na via a dc blocking capacitor C1 and a positive feedback resistor R1. The third auxiliary coil Na, the second capacitor C2 and the third diode D3 form a first stage of VCC voltage to form a loop, and the second capacitor C2, the fourth diode D4 and the third capacitor C3 form a second stage of VCC voltage to form a loop. The capacitance value of the second capacitor C2 is much smaller than that of the third capacitor C3C3, and the voltage of the second capacitor C2 is adjusted by charging and discharging through the second resistor R2, so that the voltage fluctuation is large. The voltage fluctuation of the second capacitor C2 reflects the current magnitude of the third auxiliary winding Na, i.e., the current magnitude of the main winding Np and the transistor first GAN HEMT device Q1 and SI-based LDMOS device Q3. Therefore, the voltage on the second capacitor C2 is fed to the gate of the second GAN HEMT device Q2 through the fifth resistor R5 and the sixth capacitor C6, so that the effect of feeding back the peak current flowing through the first GAN HEMT device Q1 and the SI-based LDMOS device Q3 can be achieved, and the sixth capacitor C6 is used for isolating the direct current component and feeding back only the alternating part of the voltage on the second capacitor C2 to the gate of the second GAN HEMT device Q2. The second voltage regulator tube Dz2, the third resistor R3 and the fourth resistor R4 transmit a grid drive signal of the SI-based LDMOS device Q3 to a grid of the second GAN HEMT device Q2, so that a slope compensation effect is achieved, the duty ratio range of the converter is expanded, and sub-harmonic oscillation is avoided. The secondary output voltage is sent to the gate of the second GAN HEMT device Q2 through an isolation feedback network, usually in a feedback manner of a three-terminal regulator plus an optocoupler, through an eighth resistor R8. That is, the gate of the second GAN HEMT device Q2 includes output voltage feedback information, peak current information and slope compensation information of the first GAN HEMT device Q1 and the SI-based LDMOS device Q3, so that three functions of current inner loop, voltage outer loop and sub-harmonic elimination can be realized, and the effects of output voltage stabilization, over-power protection and maximum duty cycle extension are simultaneously satisfied.

Another specific embodiment is shown in fig. 3, and the main part is the same as that shown in fig. 2, except that the secondary output voltage is detected by integrating the voltage of the drain of the first GAN HEMT device Q1 at the turn-off time through the third regulator Dz3, the sixth resistor R6, the fifth capacitor C5 and the seventh resistor R7 without an isolation feedback network. Dz3 allows the circuit to detect only when the device is off, the sixth resistor R6 and the seventh resistor R7 step down the drain voltage, the fifth capacitor C5 integrates, and the information of the drain voltage of the first GAN HEMT device Q1 when it is off is sent to the gate of the second GAN HEMT device Q2 through the eighth resistor R8. Since the drain voltage of the first GAN HEMT device Q1 when turned off is equal to the sum of the input voltage and n times the output voltage (n is the ratio of the number of primary and secondary turns of the main power transformer, that is, Np/Ns, which is a fixed value), the drain voltage of the first GAN HEMT device Q1 when turned off, that is, the gate of the second GAN HEMT device Q2, contains the output voltage feedback information, and the problem is that the input voltage information cannot be stripped off at this time. Since the higher the input voltage is, the smaller the working duty cycle of the circuit is, further, the circuit feeds back the input voltage to the gate of the second GAN HEMT device Q2 through R9, so as to realize the function of stripping the input voltage information. Therefore, the gate of the second GAN HEMT device Q2 includes output voltage feedback information, peak current information and slope compensation information of the first GAN HEMT device Q1 and the SI-based LDMOS device Q3, so that three functions of current inner loop, voltage outer loop and sub-harmonic elimination can be realized, and the effects of output voltage stabilization, over-power protection and maximum duty cycle extension are met.

Based on the above, the main part of the invention is completely the same as that of the traditional RCC circuit, but innovations are made in a feedback mode, a nondestructive current detection mode, a main power tube driving mode and a slope compensation mode, so that the working frequency of the RCC circuit is improved, the application power level of the circuit is expanded, a brand new self-excitation driving scheme is provided for GaN HEMT and LDMOS devices, and no additional driving chip is needed; meanwhile, the method has the advantages of realizing lossless and small loop by high-frequency current detection, directly controlling the stability of the secondary output voltage on the primary side, expanding the duty ratio from 0.4 to 0.55, expanding the working frequency from 100kHz to hundreds of kHz, along with low cost, small size and the like.

It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.