Method for measuring ionized charge particle size of high-energy particles
阅读说明：本技术 一种测量高能粒子离化电荷粒径的方法 (Method for measuring ionized charge particle size of high-energy particles ) 是由 闫薇薇 曾传滨 高林春 李晓静 倪涛 李多力 罗家俊 韩郑生 于 2021-01-06 设计创作，主要内容包括：本发明属于集成电路技术领域,公开了一种测量高能粒子离化电荷粒径的方法,包括：采用单个高能粒子垂直入射设置有多个分页的静态随机存储器电路的方式进行辐照实验；在所述辐照实验中,获取选通的所述多个分页的静态随机存储器电路单粒子翻转阈值；基于所述静态随机存储器电路单粒子翻转阈值以及所述多个分页的串联器件间距确定高能粒子离化电荷粒径。本发明提供的测量高能粒子离化电荷粒径的方法能够实现高能粒子离化电荷粒径的可靠评估。(The invention belongs to the technical field of integrated circuits, and discloses a method for measuring the ionized charge particle size of high-energy particles, which comprises the following steps: performing an irradiation experiment in a manner that a single high-energy particle vertically enters a static random access memory circuit provided with a plurality of pages; in the irradiation experiment, obtaining single event upset thresholds of the gated static random access memory circuits of the multiple pages; and determining the high-energy particle ionization charge particle size based on the single event upset threshold of the static random access memory circuit and the pitches of the plurality of pages of series-connected devices. The method for measuring the ionization charge particle size of the high-energy particles can realize reliable evaluation of the ionization charge particle size of the high-energy particles.)
1. A method for measuring the ionized charge size of energetic particles, comprising:
performing an irradiation experiment in a manner that a single high-energy particle vertically enters a static random access memory circuit provided with a plurality of pages;
in the irradiation experiment, obtaining single event upset thresholds of the gated static random access memory circuits of the multiple pages;
and determining the high-energy particle ionization charge particle size based on the single event upset threshold of the static random access memory circuit and the pitches of the plurality of pages of series-connected devices.
2. The method of claim 1, wherein the sram circuit comprises: four pages;
the four pages are respectively and correspondingly provided with a 6-transistor static storage unit circuit, a first 10-transistor static storage unit circuit, a second 10-transistor static storage unit circuit and a third 10-transistor static storage unit circuit;
wherein the first 10-transistor static memory cell circuit has a series device spacing d1And the distance d between the series devices of the second 10-transistor static memory unit circuit2And a series device spacing d of a third 10-transistor static memory cell circuit3And d is1<d2<d3。
3. The method of claim 2, wherein said obtaining said plurality of gated static random access memory circuit single event upset thresholds for said plurality of pages comprises:
gating the four pages respectively, and obtaining the 6-transistor static memory cell circuit and the first 10-transistor static memory cellThe element circuit, the second 10-transistor static memory cell circuit and the third 10-transistor static memory cell circuit have a single event effect threshold LET0、LET1、LET2And LET3。
4. The method of claim 3, wherein determining the high energy particle ionization charge particle size based on the single event upset threshold of the SRAM circuit and the plurality of paged series device spacings comprises:
when LET0≈LET1≈LET2≈LET3When the particle diameter D of the ionized charge of the high-energy particles is larger than or equal to D3；
When LET0≈LET1≈LET2<<LET3When D is satisfied, the high energy particle ionization charge particle diameter D2≤D<d3；
When LET0≈LET1<<LET2≈LET3The ionization charge particle diameter D of the high-energy particles satisfies D1≤D<d2；
When LET0<<LET1≈LET2≈LET3And then the heavy ion particle diameter D satisfies D<d1。
5. The method of claim 1, wherein the sram circuit is fabricated using an SOI process.
6. The method of claim 2, wherein the 6-transistor static memory cell circuit comprises: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply voltage VDD, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with a second storage node, and the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are connected with a first storage node;
the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected with the first storage node, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube are connected with the second storage node, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded;
the source electrode of the third NMOS tube is connected with the first storage node, the grid electrode of the third NMOS tube is connected with a word line, and the drain electrode of the third NMOS tube is connected with a first bit line;
the source electrode of the fourth NMOS tube is connected with the second storage node, the grid electrode of the fourth NMOS tube is connected with the word line, and the drain electrode of the fourth NMOS tube is connected with the second bit line.
7. The method of claim 2, wherein the first 10-transistor static memory cell circuit comprises: a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube;
the source electrode of the third PMOS tube is connected with a power supply voltage VDD, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with a third storage node, and the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with a fourth storage node;
the source electrode of the fifth PMOS tube is connected with a power supply voltage VDD, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the fourth storage node, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with the third storage node;
the drain electrode of the fifth NMOS tube is connected with the third storage node, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are connected with the fourth storage node;
the drain electrode of the seventh NMOS tube is connected with the fourth storage node, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is grounded, and the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with the third storage node;
the source electrode of the ninth NMOS tube is connected with the third storage node, the drain electrode of the ninth NMOS tube is connected with the first bit line, and the grid electrode of the ninth NMOS tube is connected with the word line;
the source electrode of the tenth NMOS tube is connected with the fourth storage node, the drain electrode of the tenth NMOS tube is connected with the second bit line, and the grid electrode of the tenth NMOS tube is connected with the word line.
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method for measuring the ionized charge particle size of high-energy particles.
Background
Multi-bit flipping refers to the situation where a single particle incident device causes multiple memory cells to flip at corresponding physical addresses. With the development of semiconductor manufacturing processes, the device size is continuously reduced, the critical charge is continuously reduced, and the multi-bit flip specific gravity caused by the high-energy particle vertical incidence device is gradually increased. In order to inhibit multi-bit overturning caused by a high-energy particle vertical incidence circuit, special layout topological design needs to be carried out on circuits such as error correction coding and the like, and therefore the influence range of ionizing charges generated by high-energy particle incidence needs to be obtained; but the prior art lacks a reliable measurement scheme.
Disclosure of Invention
The invention provides a method for measuring the ionization charge particle size of high-energy particles, which solves the technical problem that the ionization charge particle size of the high-energy particles cannot be reliably measured in the prior art.
In order to solve the above technical problem, the present invention provides a method for measuring a particle size of an ionized charge of a high energy particle, comprising:
performing an irradiation experiment in a manner that a single high-energy particle vertically enters a static random access memory circuit provided with a plurality of pages;
in the irradiation experiment, obtaining single event upset thresholds of the gated static random access memory circuits of the multiple pages;
and determining the high-energy particle ionization charge particle size based on the single event upset threshold of the static random access memory circuit and the pitches of the plurality of pages of series-connected devices.
Further, the static random access memory circuit includes: four pages;
the four pages are respectively and correspondingly provided with a 6-transistor static storage unit circuit, a first 10-transistor static storage unit circuit, a second 10-transistor static storage unit circuit and a third 10-transistor static storage unit circuit;
wherein the first 10-transistor static memory cell circuit has a series device spacing d1And the distance d between the series devices of the second 10-transistor static memory unit circuit2And a series device spacing d of a third 10-transistor static memory cell circuit3And d is1<d2<d3。
Further, the obtaining the gated multiple paged sram circuits single event upset threshold comprises:
respectively gating the four pages, and acquiring the single event effect threshold LET of the 6-transistor static memory cell circuit, the first 10-transistor static memory cell circuit, the second 10-transistor static memory cell circuit and the third 10-transistor static memory cell circuit0、LET1、LET2And LET3。
Further, the determining an energetic particle ionized charge particle size based on the single event upset threshold of the sram circuit and the plurality of paged series device pitches comprises:
when LET0≈LET1≈LET2≈LET3When the particle diameter D of the ionized charge of the high-energy particles is larger than or equal to D3；
When LET0≈LET1≈LET2<<LET3When D is satisfied, the high energy particle ionization charge particle diameter D2≤D<d3；
When LET0≈LET1<<LET2≈LET3The ionization charge particle diameter D of the high-energy particles satisfies D1≤D<d2；
When LET0<<LET1≈LET2≈LET3The heavy ion particle diameter D satisfies D<d1。
Further, the static random access memory circuit is prepared by adopting an SOI (silicon on insulator) process.
Further, the 6-transistor static memory cell circuit comprises: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply voltage VDD, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with a second storage node, and the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are connected with a first storage node;
the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are connected with the first storage node, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube are connected with the second storage node, and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded;
the source electrode of the third NMOS tube is connected with the first storage node, the grid electrode of the third NMOS tube is connected with a word line, and the drain electrode of the third NMOS tube is connected with a first bit line;
the source electrode of the fourth NMOS tube is connected with the second storage node, the grid electrode of the fourth NMOS tube is connected with the word line, and the drain electrode of the fourth NMOS tube is connected with the second bit line.
Further, the first 10-transistor static memory cell circuit includes: a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube;
the source electrode of the third PMOS tube is connected with a power supply voltage VDD, the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with a third storage node, and the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with a fourth storage node;
the source electrode of the fifth PMOS tube is connected with a power supply voltage VDD, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the fourth storage node, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with the third storage node;
the drain electrode of the fifth NMOS tube is connected with the third storage node, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are connected with the fourth storage node;
the drain electrode of the seventh NMOS tube is connected with the fourth storage node, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is grounded, and the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with the third storage node;
the source electrode of the ninth NMOS tube is connected with the third storage node, the drain electrode of the ninth NMOS tube is connected with the first bit line, and the grid electrode of the ninth NMOS tube is connected with the word line;
the source electrode of the tenth NMOS tube is connected with the fourth storage node, the drain electrode of the tenth NMOS tube is connected with the second bit line, and the grid electrode of the tenth NMOS tube is connected with the word line.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the method for measuring the particle size of the high-energy particle ionization charge, the value range of the radius of the high-energy particle ionization charge is obtained by comparing single-particle overturning thresholds of paging memory cells with different series intervals based on the phenomenon that the high-energy particle is incident to an SRAM circuit to cause single-particle effect overturning; the whole process is convenient and reliable.
Drawings
FIG. 1 is a flowchart of a method for measuring ionized charge particle size of energetic particles according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a 6-transistor static memory cell circuit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a first 10-transistor static memory cell circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a circuit layout and a heavy ion particle size of a first 10-transistor static memory cell according to an embodiment of the present invention.
Detailed Description
The embodiment of the application provides a method for measuring the ionization charge particle size of high-energy particles, and solves the technical problem that the ionization charge particle size of high-energy particles cannot be reliably measured in the prior art.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and the specific embodiments of the specification, and it should be understood that the embodiments and specific features of the embodiments of the present invention are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and the technical features of the embodiments and examples of the present application may be combined with each other without conflict.
The high-energy particles vertically enter the device, and generated charges can be collected by a plurality of sensitive nodes of the storage unit under the action of drift, diffusion and bipolar effects, so that the device is subjected to multi-bit overturning. The influence range of ionized charges generated after the high-energy particles enter the device can be tested according to a multi-bit overturning mechanism.
Referring to fig. 1, a method for measuring an ionized charge particle size of an energetic particle, comprising:
performing an irradiation experiment in a manner that a single high-energy particle vertically enters a static random access memory circuit provided with a plurality of pages;
in the irradiation experiment, obtaining single event upset thresholds of the gated static random access memory circuits of the multiple pages;
and determining the high-energy particle ionization charge particle size based on the single event upset threshold of the static random access memory circuit and the pitches of the plurality of pages of series-connected devices.
It is worth mentioning that the static random access memory circuit comprises: four pages;
and the four pages are respectively and correspondingly provided with a 6-transistor static storage unit circuit, a first 10-transistor static storage unit circuit, a second 10-transistor static storage unit circuit and a third 10-transistor static storage unit circuit.
Wherein the first 10-transistor static memory cell circuit has a series device spacing d1And the distance d between the series devices of the second 10-transistor static memory unit circuit2And a series device spacing d of a third 10-transistor static memory cell circuit3And d is1<d2<d3。
The 6-tube static storage unit is used as a circuit module with the minimum design size in the static random access memory circuit, and the circuit unit has the largest occupied area, so that the electrical characteristic deviation caused by the influence of radiation effect and process fluctuation is the largest and most obvious. On the basis, three 10-tube static memory unit circuits with different serial distances of three devices are combined, and the heavy ion ionization charge particle size is evaluated through the test comparison of single-particle upset thresholds of SRAMs with different structures according to the multi-bit upset principle.
Specifically, the obtaining the gated multiple paged sram circuits single event upset threshold comprises:
respectively gating the four pages, and acquiring the single event effect threshold LET of the 6-transistor static memory cell circuit, the first 10-transistor static memory cell circuit, the second 10-transistor static memory cell circuit and the third 10-transistor static memory cell circuit0、LET1、LET2And LET3。
In this embodiment, the device realizes all-dielectric isolation based on a silicon-on-insulator process. The static random access memory circuit adopts a four-paging structure, each paging is different except for an internal storage unit, and other decoders, read-write driving circuits and the like are completely the same.
Referring to fig. 2, when high energy particles are incident to the 6-transistor static memory cell circuit, a single event occurs in any one of the first PMOS transistor P31, the second PMOS transistor P41, the first NMOS transistor N41, and the second NMOS transistor N51 in the latch structure, which may cause the potential of the first storage node Q or the second storage node Qn to flip from 0 to 1 or from 1 to 0.
Referring to fig. 3, a first 10-transistor static memory cell circuit is disclosed, that is, the number of series devices is increased on the basis of the 6-transistor static memory cell circuit, and redundant storage nodes are introduced, and only when two series devices in the 10-transistor static memory cell circuit, that is, the third PMOS transistor P11 and the fourth PMOS transistor P12, the fifth PMOS transistor P21 and the sixth PMOS transistor P22, the fifth NMOS transistor N11 and the sixth NMOS transistor N12, or the seventh NMOS transistor N21 and the eighth NMOS transistor N22, are turned on by a single event effect, the potential of the third storage node Q or the fourth storage node Qn is inverted.
Referring to fig. 4, in a layout diagram of the first 10-transistor static memory cell circuit, if the high-energy particle ionization charge particle size D1 can cover two series devices in the layout, taking N11 and N12 as examples, the storage node potential is inverted, and the single event effect inversion threshold of the first 10-transistor static memory cell circuit is equivalent to that of the 6-transistor static memory cell circuit. On the contrary, if the high-energy particle ionization charge particle size D2 can only cover one device in the layout, taking N11 as an example, the potential of the storage node will not flip, so the single event effect flip threshold of the first 10-transistor static memory cell circuit is greater than that of the 6-transistor static memory cell circuit, and the radius of the heavy ion ionization charge can be evaluated by different page flip conditions of the static random access memory circuit.
Determining a high energy particle ionization charge particle size based on the SRAM circuit single event upset threshold and the plurality of paged series device spacings comprises:
when LET0≈LET1≈LET2≈LET3When the particle diameter D of the ionized charge of the high-energy particles is larger than or equal to D3；
When LET0≈LET1≈LET2<<LET3When D is satisfied, the high energy particle ionization charge particle diameter D2≤D<d3；
When LET0≈LET1<<LET2≈LET3The ionization charge particle diameter D of the high-energy particles satisfies D1≤D<d2；
When LET0<<LET1≈LET2≈LET3And then the heavy ion particle diameter D satisfies D<d1。
That is to say that the first and second electrodes,
furthermore, the static random access memory circuit is prepared by adopting an SOI (silicon on insulator) process and is isolated by all media.
Referring to fig. 2, the 6-transistor static memory cell circuit includes: a first PMOS transistor P31, a second PMOS transistor P41, a first NMOS transistor N41, a second NMOS transistor N51, a third NMOS transistor N61, and a fourth NMOS transistor N62.
The source electrode of the first PMOS transistor P31 and the source electrode of the second PMOS transistor P41 are connected with a power supply voltage VDD, the drain electrode of the first PMOS transistor P31 and the gate electrode of the second PMOS transistor P41 are connected with a second storage node, and the gate electrode of the first PMOS transistor P31 and the drain electrode of the second PMOS transistor P41 are connected with a first storage node.
The drain of the first NMOS transistor N41 and the gate of the second NMOS transistor N51 are connected to the first storage node Q, the gate of the first NMOS transistor N41 and the drain of the second NMOS transistor N51 are connected to the second storage node Qn, and the source of the first NMOS transistor N41 and the source of the second NMOS transistor N51 are grounded.
The source of the third NMOS transistor N61 is connected to the first storage node Q, the gate of the third NMOS transistor N62 is connected to the word line WL, and the drain of the third NMOS transistor N61 is connected to the first bit line BL.
The source of the fourth NMOS transistor N62 is connected to the second storage node Qn, the gate of the fourth NMOS transistor N62 is connected to the word line WL, and the drain of the fourth NMOS transistor N62 is connected to the second bit line BLB.
Referring to fig. 3, the first 10-transistor static memory cell circuit includes: a third PMOS transistor P11, a fourth PMOS transistor P12, a fifth PMOS transistor P21, a sixth PMOS transistor P22, a fifth NMOS transistor N11, a sixth NMOS transistor N12, a seventh NMOS transistor N21, an eighth NMOS transistor N22, a ninth NMOS transistor N31, and a tenth NMOS transistor N32.
The source electrode of the third PMOS tube P11 is connected with a power supply voltage VDD, the drain electrode of the third PMOS tube P11 is connected with the source electrode of the fourth PMOS tube P12, the drain electrode of the fourth PMOS tube P12 is connected with a third storage node Q, and the grid electrode of the third PMOS tube P11 and the grid electrode of the fourth PMOS tube P12 are connected with a fourth storage node Qn.
A source of the fifth PMOS transistor P21 is connected to a power voltage VDD, a drain of the fifth PMOS transistor P21 is connected to a source of the sixth PMOS transistor P22, a drain of the sixth PMOS transistor P22 is connected to the fourth storage node Qn, and a gate of the fifth PMOS transistor P21 and a gate of the sixth PMOS transistor P22 are connected to the third storage node Q.
The drain of the fifth NMOS transistor N11 is connected to the third storage node Q, the source of the fifth NMOS transistor N11 is connected to the drain of the sixth NMOS transistor N12, the source of the sixth NMOS transistor N12 is grounded, and the gates of the fifth NMOS transistor N11 and the sixth NMOS transistor N12 are connected to the fourth storage node Qn.
The drain of the seventh NMOS transistor N21 is connected to the fourth storage node Qn, the source of the seventh NMOS transistor N21 is connected to the drain of the eighth NMOS transistor N22, the source of the eighth NMOS transistor N22 is grounded, and the gates of the seventh NMOS transistor N21 and the eighth NMOS transistor N22 are connected to the third storage node Q.
The source of the ninth NMOS transistor N31 is connected to the third storage node Q, the drain of the ninth NMOS transistor N31 is connected to the first bit line WL, and the gate of the ninth NMOS transistor N31 is connected to the word line BL.
The source of the tenth NMOS transistor N32 is connected to the fourth storage node Qn, the drain of the tenth NMOS transistor N32 is connected to the second bit line BLB, and the gate of the tenth NMOS transistor N32 is connected to the word line WL.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the method for measuring the particle size of the high-energy particle ionization charge, the value range of the radius of the high-energy particle ionization charge is obtained by comparing single-particle overturning thresholds of paging memory cells with different series intervals based on the phenomenon that the high-energy particle is incident to an SRAM circuit to cause single-particle effect overturning; the whole process is convenient and reliable.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
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