阅读说明：本技术 一种看门狗集成电路及供电系统 (Watchdog integrated circuit and power supply system ) 是由 周立功 陈家隆 李伟华 于 2021-02-23 设计创作，主要内容包括：本申请实施例公开了一种看门狗集成电路及供电系统,该电路包括线性调整器、电源掉电复位电路、看门狗电路以及与非门,其中：线性调整器包括运算放大器,PMOS功率管、第一电阻和第二电阻,运算放大器的负极输入端连接基准电压VREF,正极输入端连接第一电阻和第二电阻的一端,第二电阻的另一端接地,第一电阻的另一端连接PMOS功率管的漏极,PMOS功率管的源极连接工作电压VDD,PMOS功率管的栅极连接运算放大器的输出端；运算放大器的正极输入端连接电源掉电复位电路的输入端,看门狗电路的输入端接收微控制器发送的喂狗信号；电源掉电复位电路和看门狗电路的输出端连接与非门的输入端,与非门的输出端连接微控制器的复位端。(The embodiment of the application discloses watchdog integrated circuit and power supply system, this circuit includes linear adjuster, power failure reset circuit, watchdog circuit and NAND gate, wherein: the linear regulator comprises an operational amplifier, a PMOS power tube, a first resistor and a second resistor, wherein the negative electrode input end of the operational amplifier is connected with a reference voltage VREF, the positive electrode input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected with the drain electrode of the PMOS power tube, the source electrode of the PMOS power tube is connected with a working voltage VDD, and the grid electrode of the PMOS power tube is connected with the output end of the operational amplifier; the positive input end of the operational amplifier is connected with the input end of the power-down reset circuit, and the input end of the watchdog circuit receives a dog feeding signal sent by the microcontroller; the output ends of the power supply power-down reset circuit and the watchdog circuit are connected with the input end of the NAND gate, and the output end of the NAND gate is connected with the reset end of the microcontroller.)

1. A watchdog integrated circuit, comprising: linear regulator, power down reset circuit, watchdog circuit and NAND gate, wherein:

the linear regulator comprises an operational amplifier, a PMOS power tube, a first resistor and a second resistor, wherein the negative electrode input end of the operational amplifier is connected with a reference voltage VREF, the positive electrode input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected with the drain electrode of the PMOS power tube, the source electrode of the PMOS power tube is connected with a working voltage VDD, and the grid electrode of the PMOS power tube is connected with the output end of the operational amplifier;

the positive input end of the operational amplifier is connected with the input end of the power supply power-down reset circuit, and the input end of the watchdog circuit receives a dog feeding signal sent by the microcontroller;

the output ends of the power supply power-down reset circuit and the watchdog circuit are connected with the input end of the NAND gate, and the output end of the NAND gate is connected with the reset end of the microcontroller.

2. The circuit of claim 1, wherein the drain of the PMOS power transistor is connected to power terminals of the power down reset circuit and the watchdog circuit.

3. The circuit of claim 1, wherein the power down reset circuit comprises a comparator, a first RS flip-flop, a first inverter, and a first and gate, wherein:

the positive input end of the comparator is connected with a threshold voltage VTH, the negative input end of the comparator is connected with the positive input end of the operational amplifier, the output end of the comparator is connected with the input end of the first phase inverter and the reset end of the first RS trigger, the set end of the first RS trigger is connected with a high level, the clock end of the first RS trigger receives a preset clock pulse signal, the output end of the first RS trigger is connected with the first input end of the first AND gate, the output end of the first phase inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate is connected with the first input end of the NAND gate.

4. The circuit of claim 1, wherein the watchdog circuit comprises a multiplexer, an edge detector, a frequency divider, a timer, a second RS flip-flop, a second inverter, and a second and gate, wherein:

the first input end of the multiplexer receives a dog feeding signal sent by the microcontroller, the output end of the multiplexer is connected with the input end of the edge detector, the output end of the edge detector is connected with the input end of the timer, the output end of the timer is connected with the input end of the frequency divider and the clock end of the second RS trigger, the output end of the frequency divider is connected with the input end of the second inverter and the reset end of the second RS trigger, the set end of the second RS trigger is connected with a high level, the output end of the second RS trigger is connected with the first input end of the second AND gate, the second inverter is connected with the second input end of the second AND gate, the output end of the second AND gate is connected with the second input end of the NAND gate, and the frequency divider is used for converting the square wave signal input by the timer into a square wave signal with twice dog feeding time threshold as a period, and the dog feeding time threshold is the maximum time interval of the two dog feeding signals, and if the time interval of the two dog feeding signals is greater than the dog feeding time threshold, the microcontroller is determined to be in error operation.

5. The circuit of claim 4, wherein the watchdog circuit further comprises a divider, an output of the divider is connected to an input of the divider, an output of the divider is connected to the second input of the multiplexer, and the divider is configured to divide the dog feeding interval time output by the divider by a predetermined parameter to reduce the dog feeding interval time.

6. The circuit of claim 5, wherein the multiplexer is configured with a chip select terminal and an enable terminal, the chip select terminal selects the first input terminal of the multiplexer when the enable terminal is connected to a high level, the first input terminal of the multiplexer is an active input terminal, the second input terminal of the multiplexer is an inactive input terminal, the chip select terminal selects the second input terminal of the multiplexer when the enable terminal is connected to a low level, the second input terminal of the multiplexer is an active input terminal, and the first input terminal is an inactive input terminal.

7. The circuit of claim 1, wherein the watchdog integrated circuit further comprises a manual reset circuit, an input of the manual reset circuit receiving a manual reset signal, an output of the manual reset circuit being connected to an input of the nand gate.

8. The circuit of claim 7, wherein the drain of the PMOS power transistor is connected to a power supply terminal of the manual reset circuit.

9. The circuit of claim 7, wherein the manual reset circuit comprises a third RS flip-flop, a third inverter and a third AND gate, a reset terminal of the third RS flip-flop and an input terminal of the third inverter receive the manual reset signal, a set terminal of the third RS flip-flop is connected to a high level, a clock terminal of the third RS flip-flop is connected to a preset clock signal, an output terminal of the third RS flip-flop is connected to a first input terminal of the third AND gate, an output terminal of the third inverter is connected to a second input terminal of the third AND gate, and an output terminal of the third AND gate is connected to a third input terminal of the NAND gate.

10. A power supply system, characterized in that the power supply system comprises:

the watchdog integrated circuit, microcontroller and power supply unit of any one of claims 1-9, said watchdog integrated circuit coupling said microcontroller and said power supply unit.

Technical Field

The embodiment of the application relates to the technical field of power supply systems, in particular to a watchdog integrated circuit and a power supply system.

Background

In some application scenarios requiring a high reliability MCU/MPU (micro controller Unit), an external hardware watchdog circuit is usually used. In the mode, the power supply system and the watchdog circuit are respectively composed of mutually independent hardware, but at the same time, the two circuits are mutually linked, namely, the power supply system supplies power to the watchdog circuit, and the watchdog circuit monitors the voltage stability of the power supply system. The prior art can flexibly select the power supply system and the watchdog circuit respectively, but only considers that the power supply system and the watchdog circuit are independent circuits, but does not consider the matching problem of the power supply system and the watchdog circuit. In contrast, the inventor finds that the material cost is high and the integration is poor when two independent circuits are adopted simultaneously.

Disclosure of Invention

The embodiment of the application provides a watchdog integrated circuit and a power supply system, which can reduce the material cost of the power supply system and improve the integration level of the power supply system.

In a first aspect, an embodiment of the present application provides a watchdog integrated circuit, including: linear regulator, power down reset circuit, watchdog circuit and NAND gate, wherein:

the linear regulator comprises an operational amplifier, a PMOS power tube, a first resistor and a second resistor, wherein the negative electrode input end of the operational amplifier is connected with a reference voltage VREF, the positive electrode input end of the operational amplifier is connected with one end of the first resistor and one end of the second resistor, the other end of the second resistor is grounded, the other end of the first resistor is connected with the drain electrode of the PMOS power tube, the source electrode of the PMOS power tube is connected with a working voltage VDD, and the grid electrode of the PMOS power tube is connected with the output end of the operational amplifier;

the positive input end of the operational amplifier is connected with the input end of the power supply power-down reset circuit, and the input end of the watchdog circuit receives a dog feeding signal sent by the microcontroller;

the output ends of the power supply power-down reset circuit and the watchdog circuit are connected with the input end of the NAND gate, and the output end of the NAND gate is connected with the reset end of the microcontroller.

Furthermore, the drain electrode of the PMOS power tube is connected with the power supply ends of the power supply power-down reset circuit and the watchdog circuit.

Further, the power down reset circuit comprises a comparator, a first RS flip-flop, a first inverter and a first and gate, wherein:

the positive input end of the comparator is connected with a threshold voltage VTH, the negative input end of the comparator is connected with the positive input end of the operational amplifier, the output end of the comparator is connected with the input end of the first phase inverter and the reset end of the first RS trigger, the set end of the first RS trigger is connected with a high level, the clock end of the first RS trigger receives a preset clock pulse signal, the output end of the first RS trigger is connected with the first input end of the first AND gate, the output end of the first phase inverter is connected with the second input end of the first AND gate, and the output end of the first AND gate is connected with the first input end of the NAND gate.

Further, the watchdog circuit includes a multiplexer, an edge detector, a frequency divider, a timer, a second RS flip-flop, a second inverter, and a second and gate, wherein:

the first input end of the multiplexer receives a dog feeding signal sent by the microcontroller, the output end of the multiplexer is connected with the input end of the edge detector, the output end of the edge detector is connected with the input end of the timer, the output end of the timer is connected with the input end of the frequency divider and the clock end of the second RS trigger, the output end of the frequency divider is connected with the input end of the second inverter and the reset end of the second RS trigger, the set end of the second RS trigger is connected with a high level, the output end of the second RS trigger is connected with the first input end of the second AND gate, the second inverter is connected with the second input end of the second AND gate, the output end of the second AND gate is connected with the second input end of the NAND gate, and the frequency divider is used for converting the square wave signal input by the timer into a square wave signal with twice dog feeding time threshold as a period, and the dog feeding time threshold is the maximum time interval of the two dog feeding signals, and if the time interval of the two dog feeding signals is greater than the dog feeding time threshold, the microcontroller is determined to be in error operation.

Furthermore, the watchdog circuit further comprises a divider, an output end of the frequency divider is connected with an input end of the divider, an output end of the divider is connected with a second input end of the multiplexer, and the divider is used for dividing the dog feeding interval time output by the frequency divider by a preset parameter so as to shorten the dog feeding interval time.

Further, the multiplexer is provided with a chip selection end and an enable end, when the enable end is connected to a high level, the chip selection end selects the first input end of the multiplexer, the first input end of the multiplexer is an active input end, the second input end of the multiplexer is an inactive input end, when the enable end is connected to a low level, the chip selection end selects the second input end of the multiplexer, the second input end of the multiplexer is an active input end, and the first input end is an inactive input end.

Furthermore, the watchdog integrated circuit further comprises a manual reset circuit, wherein the input end of the manual reset circuit receives a manual reset signal, and the output end of the manual reset circuit is connected with the input end of the nand gate.

Furthermore, the drain electrode of the PMOS power tube is connected with the power supply end of the manual reset circuit.

Furthermore, the manual reset circuit comprises a third RS flip-flop, a third inverter and a third and gate, wherein a reset end of the third RS flip-flop and an input end of the third inverter receive the manual reset signal, a set end of the third RS flip-flop is connected to a high level, a clock end of the third RS flip-flop is connected to a preset clock signal, an output end of the third RS flip-flop is connected to a first input end of the third and gate, an output end of the third inverter is connected to a second input end of the third and gate, and an output end of the third and gate is connected to a third input end of the nand gate.

In a second aspect, an embodiment of the present application provides a power supply system, including:

the watchdog integrated circuit of the first aspect, a microcontroller and a power supply unit, the watchdog integrated circuit connecting the microcontroller and the power supply unit.

This application embodiment is through with watchdog circuit, power-fail reset circuit and manual reset circuit integration in same circuit, through NAND gate connection watchdog circuit, power-fail reset circuit and manual reset circuit's output, when arbitrary circuit output reset signal, NAND gate sends reset signal to microcontroller, in time resets microcontroller's operating condition to avoid microcontroller to be absorbed in the endless loop, the unable normal work of microcontroller. The voltage of the power supply system is collected through the linear regulator, the voltage of the power supply system is monitored through the power failure reset circuit, when the voltage abnormality is detected, the power failure reset circuit outputs a reset signal, and the NAND gate sends the reset signal to the microcontroller, so that the real-time monitoring of the power supply system is achieved. By the technical means, the linear regulator, the power failure reset circuit, the manual reset circuit and the watchdog circuit are integrated, the reliability of peripheral devices of the power supply system is improved, the high integration of the power supply system is realized, and the material cost of the circuit is saved.

Drawings

Fig. 1 is a schematic structural diagram of a watchdog integrated circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a power down reset circuit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a watchdog circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a manual reset circuit according to an embodiment of the present application;

in the figure, 10, a linear regulator; VDD, operating voltage; VREF, reference voltage; VOUT, output voltage; VFB, sampling voltage; EA. An operational amplifier; PMOS, PMOS power tube; r4, a first resistor; r5, a second resistor; 20. a manual reset circuit; 21. a third RS flip-flop; 22. a third AND gate; 23. a third inverter; s3, a setting end of a third RS trigger; r3 and the reset end of a third RS trigger; CK3, clock terminal of the third RS flip-flop; TPR3, a second clock pulse signal; MR, manual reset signal; q3, the output end of the third RS trigger; 30. a power down reset circuit; 31. a first RS flip-flop; 32. a first AND gate; 33. a first inverter; COMP, comparator; VTH, threshold voltage; s1, a setting end of the first RS trigger; CK1, clock terminal of the first RS flip-flop; r1 and a reset end of the first RS trigger; q1, a first output terminal of the first RS flip-flop; TPR1, a first clock pulse signal; 40. a watchdog circuit; 41. a multiplexer; 42. an edge detector; 43. a timer; 44. a frequency divider; 45. a second RS flip-flop; 46. a divider; 47. a second inverter; 48. a second AND gate; IN1, a first input of a multiplexer; IN2, a second input of the multiplexer; D. an output of the multiplexer; C. a chip select terminal of the multiplexer; ENB, an enable terminal of the multiplexer; WDI, dog feed signal; s2, a setting end of the second RS trigger; r2 and a reset end of the second RS trigger; CK2, clock terminal of the second RS flip-flop; q2, a first output end of the second RS trigger; 50. a NAND gate; y1, a first input end of the NAND gate; y2, a second input end of the NAND gate; y3, a third input end of the NAND gate; 60. a microcontroller; RESET, RESET terminal of microcontroller.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, specific embodiments of the present application will be described in detail with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some but not all of the relevant portions of the present application are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

The application provides a watchdog integrated circuit and power supply system, aim at through with the watchdog circuit, power failure reset circuit and manual reset circuit integration are in same circuit, through NAND gate connection watchdog circuit, power failure reset circuit and manual reset circuit's output, when arbitrary circuit output reset signal, NAND gate sends reset signal to microcontroller, microcontroller's operating condition resets in time, in order to avoid microcontroller to be absorbed in the endless loop, the unable normal work of microcontroller. The voltage of the power supply system is collected through the linear regulator, the voltage of the power supply system is monitored through the power failure reset circuit, when the voltage abnormality is detected, the power failure reset circuit outputs a reset signal, and the NAND gate sends the reset signal to the microcontroller, so that the real-time monitoring of the power supply system is achieved. Compared with the traditional watchdog circuit and the traditional power supply system, the power supply system and the watchdog circuit are respectively composed of mutually independent hardware, only the fact that the power supply system and the watchdog circuit are independent circuits is considered, but the matching problem of the power supply system and the watchdog circuit is not considered, and the material cost is high when two independent circuits are adopted simultaneously. Based on this, the watchdog integrated circuit and the power supply system that this application embodiment provided. The material cost of the power supply system is reduced, and the integration level of the power supply system is improved.

The first embodiment is as follows:

fig. 1 is a schematic structural diagram of a watchdog integrated circuit according to an embodiment of the present application. Referring to fig. 1, a watchdog integrated circuit includes a linear regulator 10, a power-down reset circuit 30, a watchdog circuit 40, a manual reset circuit 20, and a nand gate 50, wherein: the linear regulator 10 comprises an operational amplifier EA, a PMOS power transistor PMOS, a first resistor R4 and a second resistor R5, wherein the negative input end of the operational amplifier EA is connected with a reference voltage VREF, the positive input end of the operational amplifier EA is connected with one ends of the first resistor R4 and the second resistor R5, the other end of the second resistor R5 is grounded, the other end of the first resistor R4 is connected with the drain electrode of the PMOS power transistor PMOS, the source electrode of the PMOS power transistor PMOS is connected with a working voltage VDD, and the gate electrode of the PMOS power transistor PMOS is connected with the output end of the operational amplifier EA; the positive input end of the operational amplifier EA is connected with the input end of the power-down reset circuit 30, the input end of the watchdog circuit 40 receives a dog feeding signal WDI sent by the microcontroller 60, and the input end of the manual reset circuit 20 receives a manual reset signal MR; the output ends of the power-down reset circuit 30, the watchdog circuit 40 and the manual reset circuit 20 are connected to the input end of the nand gate 50, and the output end of the nand gate 50 is connected to the reset end of the microcontroller 60. The drain of the PMOS power tube PMOS is connected with the power supply ends of the power-down reset circuit 30, the watchdog circuit 40 and the manual reset circuit 20.

Illustratively, the first resistor R4 and the second resistor R5 form a voltage dividing resistor network, the output voltage VOUT output by the PM0S power tube is sampled by the voltage dividing resistor network to obtain a sampled voltage VFB, and the sampled voltage VFB is in a linear relationship with the output voltage VOUT. The operational amplifier EA compares a reference voltage VREF input by a negative input end with a sampling voltage VFB input by a positive input end, when the sampling voltage VFB is smaller than the reference voltage VREF, the output voltage VOUT of the operational amplifier EA is reduced, the PMOS power tube PMOS driving capability connected with the output end of the operational amplifier EA is enhanced, the output voltage VOUT is increased, and the sampling voltage VFB in a certain linear relation with the output voltage VOUT is increased. When the sampling voltage VFB is larger than the reference voltage VREF, the output voltage VOUT of the operational amplifier EA is increased, the drive capability of the POMS power tube is weakened, the output voltage VOUT is reduced, and the sampling voltage VFB is reduced. The output voltage VOUT is connected to the power supply terminals of the power down reset circuit 30, the manual reset circuit 20 and the watchdog circuit 40, supplies power to the three reset circuits through the output voltage VOUT, and dynamically adjusts the output voltage VOUT through the linear regulator 10 to realize stable power supply. The output ends of the three reset circuits are connected to the input end of the nand gate 50, when any one of the three reset circuits outputs a low level signal, the nand gate 50 sends a high level signal to the reset end of the microcontroller 60, and the microcontroller 60 responds to the high level signal input by the reset end to execute reset operation. Understandably, the reset signals output by the three reset circuits are low-level signals.

Further, the sampled voltage VFB is connected to the power-down reset circuit 30, and the output voltage VOUT of the linear regulator 10 is monitored by the power-down reset circuit 30, so as to ensure stable output of the output voltage VOUT. Specifically, fig. 2 is a schematic structural diagram of a power down reset circuit 30 according to an embodiment of the present application. Referring to fig. 2, the power down reset circuit 30 includes a comparator COMP, a first RS flip-flop 31, a first inverter 33, and a first and gate 32, wherein: an anode input end of the comparator COMP is connected with the threshold voltage VTH, a cathode input end of the comparator COMP is connected with an anode input end of the operational amplifier EA, an output end of the comparator COMP is connected with an input end of the first inverter 33 and a reset end R1 of the first RS flip-flop 31, a set end S1 of the first RS flip-flop 31 is connected with a high level, a clock end CK1 of the first RS flip-flop 31 receives the first clock pulse signal TPR1, an output end of the first RS flip-flop 31 is connected with a first input end of the first and gate 32, an output end of the first inverter 33 is connected with a second input end of the first and gate 32, and an output end of the first and gate 32 is connected with a first input end Y1 of the nand gate.

Illustratively, the comparator COMP compares a threshold voltage VTH input from the positive input terminal with a sampling voltage VFB input from the negative input terminal, and when the threshold voltage VTH is greater than the sampling voltage VFB, the comparator COMP sends a high-level signal to the input terminal of the first inverter 33. The first inverter converts the high level signal into a low level signal and transmits the low level signal to the first and gate 32, the first and gate 32 responds to the low level signal transmitted by the first inverter 33 and transmits the low level signal to the first input terminal Y1 of the nand gate 50, the nand gate 50 responds to the low level signal and transmits the high level signal to the RESET terminal RESET of the microcontroller 60, and the microcontroller 60 responds to the high level signal of the RESET terminal RESET and performs a RESET operation, thereby implementing a fast trigger RESET. The comparator COMP further sends a high level signal to the reset terminal R1 of the first RS flip-flop 31, and the first RS flip-flop 31 responds to the high level signal from the reset terminal R1 and sets the current flip-flop state to 0 when the first clock pulse signal TPR1 is at a high level, and the output terminal Q1 of the first RS flip-flop 31 outputs the current flip-flop state, i.e., the output terminal Q1 of the first RS flip-flop 31 outputs a low level signal. The output Q1 of the first RS flip-flop sends a low signal to the first and gate, but since the first inverter 33 has sent a low signal to the first and gate 32, a reset has been triggered at this time, whatever signal the first RS flip-flop 31 outputs. When the threshold voltage VTH is smaller than the sampling voltage VFB, the comparator COMP sends a low level signal to the first inverter 33, the first inverter 33 converts the low level signal into a high level signal, and inputs the high level signal to the first and gate 32, and at this time, whether the first and gate 32 outputs the high level signal or the low level signal further needs to be according to the output signal of the first RS flip-flop. The comparator COMP sends a low level signal to the reset terminal R1 of the first RS flip-flop 31, since the low level signal input by the reset terminal R1 is an invalid input signal, and the high level signal is input by the set terminal S1, the first RS flip-flop 31 responds to the high level signal of the set terminal S1, and sets the current flip-flop state to 1 when the first clock pulse signal TPR1 is at a high level, and the output terminal Q1 of the first RS flip-flop 31 outputs a high level signal to the first and gate 32. At this time, both input terminals of the first and gate 32 are high level signals, and the first and gate 32 inputs the high level signal to the nand gate 50. If all other RESET circuits output high level signals at this time, the nand gate 50 sends a low level signal to the RESET terminal RESET of the microcontroller 60 according to the high level signals of all the input terminals, and the microcontroller 60 responds to the low level signal of the RESET terminal RESET, and does not execute the RESET operation or stops executing the RESET operation. It should be noted that, if the first clock pulse signal TPR1 input by the clock terminal CK1 of the first RS flip-flop 31 is at a low level when the reset terminal R1 of the first RS flip-flop 31 inputs a low level, the state of the current flip-flop is kept consistent with the state of the flip-flop at the previous time, that is, if the first RS flip-flop 31 outputs a low level at the previous time, the current first RS flip-flop 31 outputs a low level. When the first clock pulse signal TPR1 changes from a low level signal to a high level signal after a period of time, the first RS flip-flop 31 responds to the high level signal at the set terminal S1, and the output terminal Q1 outputs the high level signal, that is, the first RS flip-flop 31 changes the output signal after a period of time delay. The current time and the last time are two time periods in any period of the clock pulse signal respectively.

Further, the microcontroller 60 sends a dog feeding signal WDI to the input of the watchdog circuit 40, and the operating condition of the microcontroller 60 is monitored by the watchdog circuit 40. Specifically, fig. 3 is a schematic structural diagram of a watchdog circuit 40 according to an embodiment of the present application. Referring to fig. 3, the watchdog circuit 40 includes a multiplexer 41, an edge detector 42, a frequency divider 44, a timer 43, a second RS flip-flop 45, a divider 46, a second inverter 47, and a second and gate 48, wherein: the multiplexer 41 is provided with a first input terminal IN1, a second input terminal IN2, an output terminal D, a chip select terminal C and an enable terminal ENB, the first input terminal IN1 of the multiplexer 41 receives the dog feeding signal WDI sent by the microcontroller 60, the output terminal D of the multiplexer 41 is connected to an input terminal of the edge detector 42, an output terminal of the edge detector 42 is connected to an input terminal of the timer 43, an output terminal of the timer 43 is connected to an input terminal of the frequency divider 44 and a clock terminal CK2 of the second RS flip-flop 45, an output terminal of the frequency divider 44 is connected to an input terminal of the second inverter 47 and a reset terminal R1 of the second RS flip-flop 45, a set terminal S1 of the second RS flip-flop 45 is connected to a high level, an output terminal of the second RS flip-flop 45 is connected to a first input terminal of the second and gate 48, an output terminal of the second and gate 47 is connected to a second input terminal Y2 of the nand gate 50, an output of the frequency divider 44 is connected to an input of a divider 46, and an output of the divider 46 is connected to a second input of the multiplexer 41. The frequency divider 44 is configured to convert the square wave signal input by the timer 43 into a square wave signal with a period of twice the feeding time threshold, where the feeding time threshold is a maximum time interval of two times of feeding signals WDI, and if the time interval of two times of feeding signals WDI is greater than the feeding time threshold, it is determined that the microcontroller 60 is in error. The divider 46 is used for dividing the dog feeding interval time output by the frequency divider 44 by a preset parameter so as to shorten the dog feeding interval time. When the enable terminal ENB is connected to the high level, the chip select terminal C selects the first input terminal IN1 of the multiplexer 41, the first input terminal IN1 of the multiplexer 41 is an active input terminal, and the second input terminal IN2 is an inactive input terminal, and when the enable terminal ENB is connected to the low level, the chip select terminal C selects the second input terminal IN2 of the multiplexer 41, the second input terminal IN2 of the multiplexer 41 is an active input terminal, and the first input terminal IN1 is an inactive input terminal.

Illustratively, when the first input IN1 is an active input, the multiplexer 41 receives the dog feeding signal WDI transmitted by the microcontroller 60 through the first input IN1 and transmits the dog feeding signal WDI to the edge detector 42, and the edge detector 42 transmits a pulse signal to an input of the timer 43 according to a step change of the dog feeding signal WDI and corresponding to an output pulse signal. The timer 43 clears and times again the current timing state according to the pulse signal at the input end, outputs a square wave signal with a preset time period, sends the square wave signal to the input end of the frequency divider 44 and the clock end of the second RS flip-flop 45, and takes the square wave signal output by the timer 43 as the clock pulse signal of the second RS flip-flop 45. The frequency divider 44 converts the square wave signal into a square wave signal with a period of twice the feeding time threshold according to the square wave signal at the input end, and sends the square wave signal to the reset end of the second RS flip-flop 45. Illustratively, the timer 43 outputs a square wave signal with a period of 2ms, and the feeding time threshold is 10ms, then the square wave signal with the period of 2ms is converted into a square wave signal with a period of 20ms by the frequency divider 44. Assuming that the timer 43 receives the pulse signal sent by the edge detector 42 again 8ms after receiving the pulse signal sent by the edge detector 42, that is, the time interval of two consecutive feeding dog signals WDI is 8ms, the timer 43 generates a square wave signal with a length of 4 time periods according to the pulse signals sent before and after the edge detector 42, and the frequency divider 44 converts the square wave signal into a low level signal with a length of 8 ms. Assuming that the time interval of two consecutive feeding dog signals WDI is 12ms, timer 43 generates a square wave signal of 6 time period lengths, and frequency divider 44 converts the square wave signal into a low level signal of 10ms first and a high level signal of 2ms then. Understandably, if the time interval of two consecutive feeding dog signals WDI is greater than the feeding dog time threshold, the frequency divider 44 will send high signals to the second RS flip-flop 45 and the second inverter 47 at the time node spaced by the feeding dog time threshold after the timer 43 starts counting to trigger the reset output.

Further, when the second inverter 47 receives the high level signal, it converts the high level signal into a low level signal and sends the low level signal to the second and gate 48, and the second and gate 48 responds to the low level signal sent by the second inverter 47 and sends the low level signal to the second input terminal Y2 of the nand gate 50. The nand gate 50 responds to the low level signal and sends a high level signal to the RESET terminal RESET of the microcontroller 60, and the microcontroller 60 responds to the high level signal of the RESET terminal RESET and performs a RESET operation, thereby implementing a fast trigger RESET. When the reset terminal R2 of the second RS flip-flop 45 receives a high level signal, and when the first clock signal TPR1 is at a high level, the current state of the flip-flop is set to 0, and the output terminal Q2 of the second RS flip-flop 45 outputs the current state of the flip-flop, that is, the output terminal Q2 outputs a low level signal. The output Q2 of the second RS flip-flop 45 sends a low signal to the second and gate, but since the second inverter 47 has sent a low signal to the second and gate 48, a reset has been triggered at this time, whatever signal the second RS flip-flop 45 outputs.

When the second inverter 47 receives the low level signal, the second inverter 47 converts the low level signal into a high level signal, and inputs the high level signal to the second and gate 48, and at this time, whether the first and gate 48 outputs the high level signal or the low level signal further needs to be according to the output signal of the second RS flip-flop. When the reset terminal R2 of the second RS flip-flop 45 receives a low level signal, since the low level signal inputted by the reset terminal R2 is an invalid input signal, and the high level signal inputted by the set terminal S2, the second RS flip-flop 45 responds to the high level signal of the set terminal S2, and when the square wave signal is at a high level, the current state of the flip-flop is set to 1, and the output terminal Q2 of the second RS flip-flop 45 outputs the current state of the flip-flop, that is, the output terminal Q2 outputs a high level signal to the second and gate 48. At this time, both input terminals of the second and gate 48 are high level signals, and the second and gate 48 inputs a high level signal to the nand gate 50. If all other RESET circuits output high level signals at this time, the nand gate 50 sends a low level signal to the RESET terminal RESET of the microcontroller 60 according to the high level signals of all the input terminals, and the microcontroller 60 responds to the low level signal of the RESET terminal RESET, and does not execute the RESET operation or stops executing the RESET operation. It should be noted that if the square wave signal output by the timer 43 and input by the clock terminal CK2 of the second RS flip-flop 45 is at a low level when the reset terminal of the second RS flip-flop 45 inputs a low level, the state of the current flip-flop is kept consistent with the state of the flip-flop at the previous time, and if the second RS flip-flop 45 outputs a low level at the previous time, the current second RS flip-flop 45 outputs a low level. After a period of time, the square wave signal is converted from low level to high level, the second RS flip-flop 45 responds to the high level signal at the set terminal S2, and the Q2 outputs high level signal, i.e. the second RS flip-flop 45 is delayed for a period of time and then converts the output information.

Further, when the second input terminal IN2 is an active input terminal, the multiplexer 41 receives the internal dog feeding signal output from the divider 46 through the second input terminal IN2 and sends the internal dog feeding signal to the edge detector 42. Assuming that the frequency divider 44 outputs a low-level signal with a length of 8ms, the divider 46 converts the low-level signal with a length of 8ms into a low-level signal with a length of 8ms/k (k is a real number and k >1) according to preset parameters, the dog feeding time interval is shortened to ensure automatic dog feeding before the dog feeding time threshold is reached, the frequency divider 44 outputs the low-level signal, the trigger state of the second RS flip-flop 45 is set to 1, the output terminal Q2 of the second RS flip-flop 45 maintains the high level, and the watchdog circuit 40 does not trigger the reset output. It is understood that when the second input terminal IN2 and the first input terminal IN1 are multiplexed as active input terminals, the whole operation process of the watchdog circuit 40 is the same except that the input dog feeding signals are different, and the process from the edge detector 42 to the third and gate 48 is not described herein again, and reference may be made to the above embodiment for details.

Further, the manual reset signal MR is input to the input terminal of the manual reset circuit 20, and when other reset circuits fail to operate normally or fail, the manual reset circuit 20 forcibly resets the microcontroller 60. Specifically, fig. 4 is a schematic structural diagram of the manual reset circuit 20 according to an embodiment of the present application. Referring to fig. 4, the manual reset circuit 20 includes a third RS flip-flop 21, a third inverter 23 and a third and gate 22, a reset terminal R3 of the third RS flip-flop 21 and an input terminal of the third inverter 23 receive the manual reset signal MR, a set terminal S3 of the third RS flip-flop 21 is connected to a high level, a clock terminal CK3 of the third RS flip-flop 21 receives the second clock signal TPR3, an output terminal of the third RS flip-flop 21 is connected to a first input terminal of the third and gate 22, an output terminal of the third inverter is connected to a second input terminal of the third and gate 22, and an output terminal of the third and gate 22 is connected to a third input terminal Y3 of the nand gate 50.

Illustratively, when the manual RESET signal MR is a high-level signal, the third inverter 23 receives the high-level signal, converts the high-level signal into a low-level signal, and sends the low-level signal to the third and gate 22, the third and gate 22 responds to the low-level signal sent by the third inverter 23 and sends the low-level signal to the third input terminal Y3 of the nand gate 50, the nand gate 50 responds to the low-level signal and sends a high-level signal to the RESET terminal RESET of the microcontroller 60, and the microcontroller 60 responds to the high-level signal of the RESET terminal RESET and performs a RESET operation, thereby implementing a fast-triggered RESET. The reset terminal R3 of the third RS flip-flop 21 receives the high level signal, the third RS flip-flop 21 responds to the high level signal at the reset terminal R3, and sets the current flip-flop state to 0 when the second clock signal TPR3 is at a high level, and the output terminal Q3 of the third RS flip-flop 21 outputs the current flip-flop state, i.e., the output terminal Q3 outputs a low level signal. The output Q3 of the third RS flip-flop sends a low signal to the third and gate 22, but since the third inverter 23 has sent a low signal to the third and gate 22, a reset has been triggered at this time, whatever signal the third RS flip-flop 21 outputs. When the manual reset signal MR is a low-level signal, the third inverter 23 receives the low-level signal, converts the low-level signal into a high-level signal, and inputs the high-level signal to the third and gate 33, where whether the third and gate 33 outputs the high-level signal or the low-level signal further needs to be determined according to an output signal of the third RS flip-flop. The reset terminal of the third RS flip-flop 21 receives the low level signal, the third RS flip-flop 21 responds to the low level signal of the reset terminal R3, since the low level signal input by the reset terminal R3 is an invalid input signal, and the set terminal S3 inputs a high level signal, the third RS flip-flop 21 responds to the high level signal of the set terminal S3, and sets the current flip-flop state to 1 when the second clock pulse signal TPR3 is at a high level, and the output terminal Q3 sends a high level signal to the third and gate 22. At this time, both input terminals of the third and gate 22 are high level signals, and the third and gate 22 inputs a high level signal to the nand gate 50. If all other reset circuits output high level signals at this time, the nand gate 50 sends low level signals to the reset terminal of the microcontroller 60 according to the high level signals of all the input terminals, and the microcontroller 60 responds to the low level signals of the reset terminal, and does not execute the reset operation or stops executing the reset operation. It should be noted that, if the second clock pulse signal TPR3 input by the clock terminal CK3 of the third RS flip-flop 21 is at a low level when the reset terminal R3 of the third RS flip-flop 21 inputs a low level, the state of the current flip-flop is kept consistent with the state of the flip-flop at the previous time, that is, if the third RS flip-flop 21 outputs a low level at the previous time, the current third RS flip-flop 21 outputs a low level. When the second clock signal TPR3 changes from a low level signal to a high level signal after a period of time, the third RS flip-flop 21 responds to the high level signal at the set terminal S3, and the output terminal Q3 outputs the high level signal, that is, the third RS flip-flop 21 changes the output signal after a period of time delay.

IN one embodiment, a power supply system includes a watchdog integrated circuit, a microcontroller 60, and a power supply unit, wherein a first input IN1 of a multiplexer 41 of a watchdog circuit 40 of the watchdog integrated circuit is connected to a dog feed signal WDI output of the microcontroller 60, an output of a nand gate 50 is connected to a RESET terminal RESET of the microcontroller 60, and a power supply output of the power supply unit is connected to a source of a PMOS power transistor PMOS of a linear regulator 10 of the watchdog integrated circuit, i.e., the power supply unit provides an operating voltage VDD for the watchdog integrated circuit.

The foregoing is considered as illustrative of the preferred embodiments of the invention and the technical principles employed. The present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the claims.