阅读说明：本技术 振荡电路 (Oscillating circuit ) 是由 佐野稔 于 2020-11-20 设计创作，主要内容包括：振荡电路具备第1电流源电路、第2电流源电路、电阻器、第1电容、第2电容、第1比较电路、第2比较电路及RS闩锁器,根据RS闩锁器的输出信号的信号电平,将第2电流源电路的输出电流输入到第1电容或第2电容,将由第1电流源电路的输出电流和电阻器的电阻值确定的基准电压和第1电容的电压输入到第1比较电路,将基准电压和第2电容的电压输入到第2比较电路,将从第1比较电路输出的信号和从第2比较电路输出的信号输入到RS闩锁器。(The oscillation circuit includes a1 st current source circuit, a2 nd current source circuit, a resistor, a1 st capacitor, a2 nd capacitor, a1 st comparator circuit, a2 nd comparator circuit, and an RS latch, and inputs an output current of the 2 nd current source circuit to the 1 st capacitor or the 2 nd capacitor according to a signal level of an output signal of the RS latch, inputs a reference voltage determined by the output current of the 1 st current source circuit and a resistance value of the resistor and a voltage of the 1 st capacitor to the 1 st comparator circuit, inputs the reference voltage and a voltage of the 2 nd capacitor to the 2 nd comparator circuit, and inputs a signal output from the 1 st comparator circuit and a signal output from the 2 nd comparator circuit to the RS latch.)

1. An oscillating circuit characterized in that a voltage is applied to a power supply,

includes a1 st current source circuit, a2 nd current source circuit, a resistor, a1 st capacitor, a2 nd capacitor, a1 st comparator, a2 nd comparator, and an RS latch,

inputting an output current of the 2 nd current source circuit to the 1 st capacitor or the 2 nd capacitor according to a signal level of an output signal of the RS latch,

inputting a reference voltage determined by an output current of the 1 st current source circuit and a resistance value of the resistor and a voltage of the 1 st capacitance to the 1 st comparison circuit,

inputting the reference voltage and the voltage of the 2 nd capacitor to the 2 nd comparator circuit,

the signal output from the 1 st comparison circuit and the signal output from the 2 nd comparison circuit are input to the RS latch.

2. The oscillation circuit of claim 1, wherein: with respect to the 1 st current source circuit and the 2 nd current source circuit, a change in output current with respect to a temperature change is the same.

3. The oscillation circuit of claim 2, wherein: the 1 st current source circuit and the 2 nd current source circuit are provided with a micro current source having a transistor that operates in a weak inversion region.

4. The oscillation circuit of claim 1, wherein: the 1 st current source circuit and the 2 nd current source circuit have an enable signal input terminal and a start-up circuit.

5. The oscillation circuit of claim 4, wherein: the start signal of the start circuit of the 1 st current source circuit is output before the start circuit of the 2 nd current source circuit outputs the start signal.

Technical Field

The present invention relates to an oscillation circuit.

Background

Conventionally, a relaxation type oscillation circuit has been known as an oscillation circuit not using a quartz vibrator. Fig. 9 is a circuit diagram of a relaxation type oscillation circuit 801 as an example of a conventional oscillation circuit. The relaxation type oscillation circuit 801 includes: a CR oscillation circuit 802 having a resistor RV, a capacitor C1, a capacitor C2, an inverter INV1, an inverter INV2, and a comparator COMP; a band gap Reference (Bandgap Reference) circuit 803; and a voltage-to-current conversion circuit 804. The oscillation frequency of the relaxation oscillation circuit 801 is determined by comparing the voltage of the capacitor C1 and the capacitor C2 charged via the resistor RV connected to the output terminal of the inverter INV1 with the reference voltage Vref in the comparison circuit COMP.

The bandgap reference circuit 803 outputs a temperature-independent reference voltage to the voltage-current conversion circuit 804. The voltage-current conversion circuit 804 converts the voltage output from the bandgap reference circuit 803 into a current and supplies a bias current to the comparison circuit COMP. The comparison circuit COMP controls the response speed of the comparison circuit COMP according to the amount of bias current supplied.

[ Prior art documents ]

[ patent document ]

[ patent document 1 ] Japanese patent laid-open No. 2013-005109.

Disclosure of Invention

[ problem to be solved by the invention ]

The present invention is directed to provide an oscillation circuit with low power consumption.

[ MEANS FOR solving PROBLEMS ] A method for solving the problems

The oscillation circuit of the present invention has the following configuration: the circuit includes a1 st current source circuit, a2 nd current source circuit, a resistor, a1 st capacitance, a2 nd capacitance, a1 st comparison circuit, a2 nd comparison circuit, and an RS latch, and inputs an output current of the 2 nd current source circuit to the 1 st capacitance or the 2 nd capacitance, a reference voltage determined by the 1 st current source circuit and the resistor and a voltage of the 1 st capacitance to the 1 st comparison circuit, the reference voltage and a voltage of the 2 nd capacitance to the 2 nd comparison circuit, and a signal output from the 1 st comparison circuit and a signal output from the 2 nd comparison circuit to the RS latch, according to a signal level of an output signal of the RS latch.

[ Effect of the invention ]

According to the oscillation circuit of the present invention, an oscillation circuit with low power consumption can be realized.

Drawings

Fig. 1 is a circuit diagram of an oscillation circuit according to embodiment 1 of the present invention.

Fig. 2 is a circuit diagram of the 1 st current source circuit according to embodiment 1 of the present invention.

Fig. 3 is a timing chart for explaining the operation of the startup circuit according to embodiment 1 of the present invention.

Fig. 4 is a circuit diagram of the 2 nd current source circuit according to embodiment 1 of the present invention.

Fig. 5 is a circuit diagram of a comparison circuit according to embodiment 1 of the present invention.

Fig. 6 is a timing chart for explaining the overall operation of embodiment 1 of the present invention.

Fig. 7 is a circuit diagram of the 1 st current source circuit according to embodiment 2 of the present invention.

Fig. 8 is a circuit diagram of a2 nd current source circuit according to embodiment 2 of the present invention.

Fig. 9 is a circuit diagram of a conventional oscillation circuit.

Detailed Description

[ embodiment 1 ]

Fig. 1 shows a circuit diagram of an oscillator circuit 1 as an example of the oscillator circuit according to embodiment 1 of the present invention.

The oscillation circuit 1 includes: an enable signal input terminal ENINP; an output terminal OSCOUT; 10-15 of switches; inverters 20, 21; a three-input NAND circuit 22; a resistor 25; capacitors 30, 31; an RS-latch 40; current source circuits 100, 200; and comparison circuits 300, 400. Here, the switches 10 to 15 are turned on (connected state) when the control signal applied to the control terminal is at a High level, and turned off (disconnected state) when the control signal applied to the control terminal is at a Low level.

The current source circuits 100 and 200 respectively have a power supply terminal, an output terminal IOUT, an enable signal input terminal ENIN, and a start signal output terminal STUP. The comparator circuits 300 and 400 have a non-inverting input terminal INP, an inverting input terminal INN, an output terminal OUT, and an enable signal input terminal EN, respectively. The RS latch 40 has a two-input NAND circuit 23 and a three-input NAND circuit 24, and has three input terminals Ta1, Ta2, Ta3, and one output terminal Ta 4. Note that, the power supply VDD and the power supply GND will not be partially described.

In the current source circuit 100, a power supply terminal is connected to a power supply VDD, and an output terminal IOUT is connected to a power supply GND via a resistor 25. In the current source circuit 200, a power supply terminal is connected to a power supply VDD, an output terminal IOUT is connected to a power supply GND via a switch 14 and a capacitor 30, and is connected to the power supply GND via a switch 15 and a capacitor 31.

The non-inverting input terminal INP of the comparator circuit 300 is connected to the output terminal IOUT of the current source circuit 100. The inverting input terminal INN of the comparison circuit 300 is connected to the connection point P1 between the switch 14 and the capacitor 30. When the voltage input to the inverting input terminal INN is greater than the voltage input to the non-inverting input terminal INP, the comparator circuit 300 outputs a Low-level voltage from the output terminal OUT. When the voltage input to the non-inverting input terminal INP is higher than the voltage input to the inverting input terminal INN, a High-level voltage is output from the output terminal OUT.

The non-inverting input terminal INP of the comparison circuit 400 is connected to the output terminal IOUT of the current source circuit 100. The inverting input terminal INN of the comparison circuit 400 is connected to a connection point P2 between the switch 15 and the capacitor 31. The comparator circuit 400 outputs a Low-level voltage from the output terminal OUT when the voltage input to the inverting input terminal INN is greater than the voltage input to the non-inverting input terminal INP, as in the comparator circuit 300. When the voltage input to the non-inverting input terminal INP is higher than the voltage input to the inverting input terminal INN, a High-level voltage is output from the output terminal OUT.

The output terminal OUT of the comparison circuit 300 is connected to the input terminal Ta1 of the RS latch 40. The output terminal OUT of the comparison circuit 400 is connected to the input terminal Ta2 of the RS latch 40. The output terminal Ta4 of the RS latch 40 is connected to the control terminal of the switch 12, the control terminal of the switch 14, and the input terminal of the inverter 21. The output terminal of the inverter 21 is connected to the control terminal of the switch 10, the control terminal of the switch 15, and the output terminal OSCOUT.

The internal connection of the RS latch 40 is explained. The input terminal Ta1 is connected to the 1 st input terminal of the two-input NAND circuit 23. The output terminal of the two-input NAND circuit 23 is connected to the 1 st input terminal of the three-input NAND circuit 24. The input terminal Ta2 is connected to the 2 nd input terminal of the three-input NAND circuit 24. The output terminal of the three-input NAND circuit 24 is connected to the 2 nd input terminal and the output terminal Ta4 of the two-input NAND circuit 23. The input terminal Ta3 is connected to the 3 rd input terminal of the three-input NAND circuit 24.

The connection of the switches 10 to 13 will be described. The 1 st terminal of the switch 10 and the 1 st terminal of the switch 11 are connected to the 1 st terminal of the capacitor 30. The 2 nd terminal of the switch 10 and the 2 nd terminal of the switch 11 are connected to the 2 nd terminal of the capacitor 30. The 2 nd terminal of the capacitor 30 is connected to the power supply GND. The 1 st terminal of the switch 12 and the 1 st terminal of the switch 13 are connected to the 1 st terminal of the capacitor 31, and the 2 nd terminal of the switch 12 and the 2 nd terminal of the switch 13 are connected to the 2 nd terminal of the capacitor 31. The 2 nd terminal of the capacitor 31 is connected to the power supply GND.

The enable signal input terminal ENINP is connected to the enable signal input terminal ENIN of the current source circuit 100, the enable signal input terminal ENIN of the current source circuit 200, and the 1 st input terminal of the three-input NAND circuit 22. The start signal output terminal STUP of the current source circuit 100 is connected to the 2 nd input terminal of the three-input NAND circuit 22. The start signal output terminal STUP of the current source circuit 200 is connected to the 3 rd input terminal of the three-input NAND circuit 22. The output terminal of the three-input NAND circuit 22 is connected to the control terminal of the switch 11, the control terminal of the switch 13, and the input terminal of the inverter 20 via a connection point P0. The output terminal of the inverter 20 is connected to the input terminal Ta3 of the RS latch 40, the EN input terminal of the comparison circuit 300, and the EN input terminal of the comparison circuit 400.

Fig. 2 shows a circuit diagram of the current source circuit 100 as the 1 st current source circuit.

The current source circuit 100 includes: an enable signal input terminal ENIN; an output terminal IOUT; a start signal output terminal STUP; p-channel MOS transistors MP100, MP101, and MP102 (hereinafter referred to as "PMOS transistors"); n-channel MOS transistors MN100 and MN101 (hereinafter referred to as "NMOS transistors"); switches 101, 102; an inverter 103; a resistor 104; and a start-up circuit 110. The current source circuit 100 is configured as a minute current source circuit that operates in the weak inversion region by including NMOS transistors MN100 and MN101 as transistors that operate in the weak inversion region. The resistor 104 is set to a large resistance value so that the transistors MN100 and MN101 operate in a weak inversion region.

The switches 101 and 102 are turned on when a control signal applied to the control terminal is at a High level and turned off when the control signal is at a Low level. The correspondence between the control signal applied to the control terminal and on/off can be adjusted by inverting the control signal applied to the control terminal using an inverter.

The startup circuit 110 includes: an input terminal Ta 10; two output terminals Ta11, Ta 12; PMOS transistors MP110, MP 111; inverters 114, 115, 116; switches 111, 112; and a capacitor 113. The switches 111 and 112 are turned on when the control signal applied to the control terminal is at a High level, and turned off when the control signal applied to the control terminal is at a Low level.

The connection of the current source circuit 100 will be explained. The enable signal input terminal ENIN is connected to the input terminal Ta10 and the input of the inverter 103. The output of the inverter 103 is connected to the control terminal of the switch 101 and the control terminal of the switch 102. The source terminal of the PMOS transistor MP100 is connected to a power supply VDD. The drain terminal of the PMOS transistor MP100 is connected to the drain terminal of the NMOS transistor MN100, the gate terminal of the NMOS transistor MN100, the output terminal Ta11, the gate terminal of the NMOS transistor MN101, and the 1 st terminal of the switch 101. The gate terminal of the PMOS transistor MP100 is connected to the gate terminal of the PMOS transistor MP101, the drain terminal of the NMOS transistor MN101, the gate terminal of the PMOS transistor MP102, and the 2 nd terminal of the switch 102. The source terminal of the NMOS transistor MN100 is connected to the power supply GND. The source terminal of the PMOS transistor MP101 is connected to the power supply VDD. The source terminal of the NMOS transistor MN101 is connected to the power supply GND via a resistor 104. The source terminal of the PMOS transistor MP102 is connected to the power supply VDD. The drain terminal of the PMOS transistor MP102 is connected to the output terminal IOUT. The 2 nd terminal of the switch 101 is connected to the power supply GND. The 1 st terminal of the switch 102 is connected to a power supply VDD.

The connection of the start-up circuit 110 will be explained. The input terminal Ta10 is connected to the input terminal of the inverter 114 and the control terminal of the switch 112. The output of the inverter 114 is connected to the gate terminal of the PMOS transistor MP110 and the control terminal of the switch 111 via a connection point P11. The source terminal of the PMOS transistor MP110 is connected to a power supply VDD. The drain terminal of the PMOS transistor MP110 is connected to the gate terminal of the PMOS transistor MP111, the input terminal of the inverter 115, the 1 st terminal of the capacitor 113, and the 1 st terminal of the switch 111 via a connection point P12. The source terminal of the PMOS transistor MP111 is connected to the 2 nd terminal of the switch 112. The drain terminal of the PMOS transistor MP111 is connected to the output terminal Ta 11. The output of inverter 115 is connected to the input of inverter 116. The output of the inverter 116 is connected to the start signal output terminal STUP via the 2 nd output terminal Ta 12. The 2 nd terminal of the capacitor 113 is connected to the power supply GND. The 1 st terminal of the switch 112 is connected to the power supply VDD and the source terminal of the PMOS transistor MP 110. The 2 nd terminal of the switch 111 is connected to the power supply GND.

Fig. 3 is a timing chart showing the operation of the startup circuit 110 and the startup circuit 210. In fig. 3, the horizontal axis represents time, and the vertical axis represents signal levels of the respective parts of the start-up circuit. Fig. 3 is a timing chart showing the operation of the startup circuit 110 in the upper half and the operation of the startup circuit 210 in the lower half.

The operation of the startup circuit 110 will be described with reference to fig. 3. When a Low-level signal is input to the input terminal Ta10 of the starter circuit 110 (e.g., T0 in fig. 3), the connection point P11 is at a High level, the switch 111 is turned on (connected state), the switch 112 is turned off (disconnected state), and the PMOS transistor MP110 is turned off. Since both ends of the capacitor 113 are short-circuited by the switch 111, the voltage at the connection point P12 becomes the voltage of the power supply GND level. The PMOS transistor MP111 is turned on, but the switch 112 is turned off, and therefore the voltage of the output terminal Ta11 becomes the voltage of the power supply GND level. Further, a Low level signal is output from the output terminal Ta 12.

When a High-level signal is input to the input terminal Ta10 of the starter circuit 110 (e.g., T1 in fig. 3), the connection point P11 becomes Low, the switch 111 is turned off, the switch 112 is turned on, and the PMOS transistor MP110 is turned on. The capacitor 113 is charged by the current from the PMOS transistor MP110, and the voltage at the connection point P12 rises from the power supply GND level. At T15, the voltage at the connection point P12 exceeds the threshold voltage Vth (MP 111) of the PMOS transistor MP 111. In the period from T1 to T15 in fig. 3, that is, in the period in which the switch 112 and the PMOS transistor MP111 are turned on, a voltage as an activation signal is output from the output terminal Ta 11.

When the voltage at the connection point P12 exceeds the threshold voltage Vth (MP 111) of the PMOS transistor MP111, the PMOS transistor MP111 is turned off, and no voltage serving as an activation signal is output from the output terminal Ta 11. While the voltage at the connection point P12 exceeds the threshold voltage Vth (MP 111) of the PMOS transistor MP111, a High-level signal is output from the output terminal Ta12 as an activation signal.

Fig. 4 shows a circuit diagram of a current source circuit 200 as a2 nd current source circuit.

The current source circuit 200 is configured as a minute current source circuit that operates in the weak inversion region by including NMOS transistors MN200 and MN201 (transistors that operate in the weak inversion region) as in the current source circuit 100. The current source circuit 200 differs from the current source circuit 100 in that a start-up circuit 210 is provided instead of the start-up circuit 110, and other components are substantially the same. Therefore, a description overlapping with the current source circuit 100 is omitted.

The starting circuit 210 differs from the starting circuit 110 in that a capacitor 213 having a different capacitance value from that of the capacitor 113 is provided in place of the capacitor 113, and other components are substantially the same. That is, the start-up circuit 210 includes, similarly to the start-up circuit 110: an input terminal Ta 20; two output terminals Ta21, Ta 22; a PMOS transistor; an inverter; and a switch having a capacitor 213 in place of the capacitor 113.

As described above, the current source circuit 100 and the current source circuit 200 have substantially the same circuit configuration except for the capacitor 113 of the current source circuit 100 and the capacitor 213 of the current source circuit 200. Therefore, the change of the output current with respect to the temperature change of the current source circuit 200 is the same as the change of the output current with respect to the temperature change of the current source circuit 100. The capacitor 213 as the 2 nd capacitor has a capacitance value larger than that of the capacitor 113 as the 1 st capacitor.

The operation of the startup circuit 210 will be described with reference to fig. 3. The startup circuit 210 operates in the same manner as the startup circuit 110 except for the time required until the threshold voltage Vth (211) of the PMOS transistor MP211 is exceeded after the capacitor 213 starts to be charged. In the start-up circuit 210, since the capacitance value of the capacitor 213 is set to be larger than that of the capacitor 113, the time required from when the capacitor 213 starts to be charged until the threshold voltage Vth (211) of the PMOS transistor MP211 is exceeded is longer than the time required from when the capacitor 113 starts to be charged until the threshold voltage Vth (111) of the PMOS transistor MP111 is exceeded. Therefore, the period (T1 to T2) during which the start signal is output from the output terminal Ta21 is longer than the period (T1 to T15) during which the start signal is output from the output terminal Ta11 of the start circuit 110. The time until the threshold voltage of the inverter 215 in the startup circuit 210 is exceeded (not shown) and the High-level startup signal is output from the output terminal Ta22 is longer than the time until the threshold voltage of the inverter 115 in the startup circuit 110 is exceeded (not shown) and the High-level startup signal is output from the output terminal Ta 12.

Fig. 5 shows a circuit diagram of a comparison circuit 300 as a1 st comparison circuit.

The comparison circuit 300 includes: a non-inverting input terminal INP; an inverting input terminal INN; an enable signal input terminal EN; an output terminal OUT; PMOS transistors MP300, MP 301; NMOS transistors MN300, MN301, MN 302; inverters 305, 306, 307; current source circuits I300, I301; and switches 301, 302, 303, 304. The switches 301 to 304 are turned on when the control signal applied to the control terminal is at a High level, and turned off when the control signal applied to the control terminal is at a Low level.

The connection of the comparison circuit 300 will be explained. The non-inverting input terminal INP is connected to the gate terminal of the PMOS transistor MP 300. The inverting input terminal INN is connected to the gate terminal of the PMOS transistor MP 301. In the current source circuit I300, the 1 st terminal is connected to the power supply VDD, and the 2 nd terminal is connected to the 1 st terminal of the switch 303. The 2 nd terminal of the switch 303 is connected to the source terminal of the PMOS transistor MP300 and the source terminal of the PMOS transistor MP 301. The drain terminal of the PMOS transistor MP300 is connected to the drain terminal and the gate terminal of the NMOS transistor MN300, the gate terminal of the NMOS transistor MN301, and the 1 st terminal of the switch 301. The drain terminal of the PMOS transistor MP301 is connected to the drain terminal of the NMOS transistor MN301, the gate terminal of the NMOS transistor MN302, and the 1 st terminal of the switch 302.

In the current source circuit I301, the 1 st terminal is connected to the power supply VDD, and the 2 nd terminal is connected to the drain of the NMOS transistor MN302, the input terminal of the inverter 306, and the 2 nd terminal of the switch 304. The 1 st terminal of the switch 304 is connected to the power supply VDD. An output terminal of the inverter 306 is connected to an input terminal of the inverter 307. The output terminal of the inverter 307 is connected to the output terminal OUT. The source terminal of the NMOS transistor MN300, the source terminal of the NMOS transistor MN301, the source terminal of the NMOS transistor MN302, the 2 nd terminal of the switch 301, and the 2 nd terminal of the switch 302 are connected to the power supply GND, respectively.

The enable signal input terminal EN is connected to a control terminal of the switch 303 and an input terminal of the inverter 305. An output terminal of the inverter 305 is connected to a control terminal of the switch 301, a control terminal of the switch 302, and a control terminal of the switch 304.

The comparator circuit 300 outputs a High-level signal from the output terminal OUT when a Low-level signal is input to the enable signal input terminal EN, and outputs a High-level or Low-level signal from the output terminal OUT based on signals input to the non-inverting input terminal INP and the inverting input terminal INN when a High-level signal is input to the enable signal input terminal EN.

The comparator circuit 400 as the 2 nd comparator circuit has the same configuration as the comparator circuit 300, and therefore, the description thereof is omitted.

The operation of the oscillation circuit 1 will be described with reference to fig. 1, 2, 4, and 6. In fig. 6, the horizontal axis represents Time (Time) and the vertical axis represents the signal level of each signal.

< when ENINP ═ Low >)

In a state where a Low-level signal is input to the enable signal input terminal ENINP (T0 in fig. 6), the current source circuits 100 and 200 output a Low-level signal from the start signal output terminal STUP. A Low-level signal is input to each input terminal of the three-input NAND circuit 22. Since the three-input NAND circuit 22 outputs a High-level signal from the output terminal, the connection point P0 is at a High level. Thus, the switches 11 and 13 are turned on. Further, a Low-level signal is input to the enable signal input terminal EN of the comparison circuits 300 and 400 and the input terminal Ta3 of the RS latch 40. The comparator circuits 300 and 400 output signals of High level from the output terminal OUT, respectively. A High-level signal is input to each of the input terminal Ta1 and the input terminal Ta2 of the RS latch 40.

Since a Low-level signal is input to the input terminal Ta3, the RS latch 40 outputs a High-level signal from the output terminal Ta 4. The oscillation circuit 1 outputs a Low-level signal from OSCOUT. Switches 12 and 14 are turned on, and switches 13 and 15 are turned off.

< when ENINP ═ High >, a

Next, an operation in a state where a signal of a High level is input to the enable signal input terminal ENINP will be described. At time T1, a High-level signal is input to enable signal input terminal ENINP. Since the capacitance 113 of the start circuit 110 is smaller than the capacitance 213 of the start circuit 210, between times T1 and T2, a current is first output from the output terminal IOUT of the current source circuit 100, and a High-level signal is output from the start signal output terminal STUP of the current source circuit 100.

Since the output terminal IOUT of the current source circuit 100 is connected to the power supply GND via the resistor 25, a voltage determined by the current value output from the current source circuit 100 and the resistor 25 appears at both ends of the resistor 25. The voltage across both ends of the resistor 25 is input to the non-inverting input terminal INP of the comparator circuits 300 and 400 as the reference voltage Vref.

As long as the resistor 25 and the resistor 104 of the current source circuit 100 are formed of the same material, the reference voltage Vref is determined only by the size ratio of the NMOS transistor MN100 and the NMOS transistor MN101, and the reference voltage Vref shows a first order proportional relationship with respect to temperature.

Next, in the start circuit 210, the voltage of the 1 st terminal of the capacitor 213 exceeds a predetermined voltage, a current is output from the output terminal IOUT of the current source circuit 200, and a High-level signal is output from the start signal output terminal STUP of the current source circuit 200 (time T2).

At time T2, all signals input to the input terminals of the three-input NAND circuit 22 are High-level signals, and the signal at the connection point P0 changes from a High-level signal to a Low-level signal. Thus, the switches 11, 13 are turned off. The signal at the connection point P0 is inverted by the inverter 20. The signal input to the enable signal input terminal EN of the comparator circuits 300 and 400 changes from a Low level to a High level signal. A High-level signal is output from the output terminal OUT of the comparator circuits 300 and 400.

In the two-input NAND circuit 23, a High-level signal is input to two input terminals, and a Low-level signal is output from an output terminal. In the three-input NAND circuit 24, a Low-level signal output from the two-input NAND circuit 23 is input to the 1 st input terminal. The signal level of the signal output from the output terminal Ta4 maintains the High level. The signal level of the signal output from the output terminal OSCOUT maintains a Low level.

At time T2, since the switch 14 is turned on and the switches 10 and 11 are turned off, the capacitor 30 is charged by the current of the current source circuit 200, and the voltage at the connection point P1 starts to rise. When the voltage at the connection point P1 exceeds the reference voltage Vref (time T3), the comparator circuit 300 changes the signal at the output terminal OUT from High level to Low level. The signal at the input terminal Ta1 of the RS latch 40 changes from Low level to High level. The signal level of the signal output from the RS latch 40 changes from a High level to a Low level. The signal level of the signal output from the output terminal OSCOUT changes from Low level to High level.

The switches 12 and 14 are turned off and the switches 10 and 15 are turned on by a change in the signal level of the output signal of the RS latch 40. The voltage at the connection point P1 becomes zero, and the output of the comparator circuit 300 becomes a High-level signal (time T4).

At time T4, the capacitor 31 is charged by the current of the current source circuit 200, and the voltage at the connection point P2 starts to rise. When the voltage at the connection point P2 exceeds the reference voltage Vref (time T5), the comparator circuit 400 changes the signal at the output terminal OUT from a High level to a Low level. The signal level of the signal input to the input terminal Ta2 of the RS latch 40 changes from High level to Low level. The signal level of the signal output from the RS latch 40 changes from Low level to High level. The signal level of the signal output from the output terminal OSCOUT changes from a High level to a Low level.

The switches 12 and 14 are turned on and the switches 10 and 15 are turned off in response to a change in the signal level of the output signal of the RS latch 40. The voltage at the connection point P2 becomes zero, and the signal level of the signal output from the comparator circuit 400 becomes High (time T6). At time T6, the capacitor 30 is charged by the current of the current source circuit 200, and the voltage at the connection point P1 starts to rise. This state is the same as the state at time T2 described earlier. Thereafter, the oscillation circuit 1 repeats the oscillation operation from the state at time T2 to the state at time T6.

Here, the current source circuit 100 and the current source circuit 200 are micro-current source circuits. The known micro-current source circuit generally has two stable action points. One stable operating point is an operating point at which the output current becomes zero, and the other stable operating point is an operating point at which a desired output current is obtained.

In order to avoid the point at which the output current becomes zero from becoming a stable operating point, the current source circuits 100 and 200 include the start-up circuits 110 and 210.

Here, the oscillation circuit 1 is configured to start the current source circuit 100 before the current source circuit 200 is started. At time T2 in fig. 6, the switches 10 and 13, which short-circuit the both ends of the capacitors 30 and 31 shown in fig. 1, are opened, and charging of the capacitor 30 is started. At time T3, the voltage P1 (the voltage at the inverting input terminal INN) of the capacitor 30 exceeds the reference voltage Vref (the voltage at the non-inverting input terminal INP), and the voltage Ta1 (the voltage at the output terminal of the comparator circuit 300) is inverted, thereby starting the oscillation operation. On the other hand, when the current source circuit 200 is activated and the charging of the capacitor 30 or the capacitor 31 is started before the current source circuit 100 is activated, the voltage of the non-inverting input terminal INP does not become the reference voltage Vref. In this case, the voltage of the output terminal OUT of the comparator circuits 300 and 400 is not inverted and the oscillation operation is not started.

In the oscillation circuit 1, in order to reliably start the oscillation operation, the capacitance value of the capacitor 213 of the start circuit 210 is set to be larger than the capacitance value of the capacitor 113 of the start circuit 110 so that the current source circuit 100 starts before the current source circuit 200.

According to the oscillation circuit of the present embodiment, an oscillation circuit with a small circuit scale and low power consumption can be obtained.

[ 2 nd embodiment ]

The oscillation circuit of the present embodiment is substantially the same as the oscillation circuit of embodiment 1, except that the configuration of the current source circuit is different. Therefore, in the present embodiment, a description will be given mainly on a current source circuit having a different configuration.

Fig. 7 is a circuit diagram of a current source circuit 100a included in the oscillation circuit according to embodiment 2 of the present invention, and fig. 8 is a circuit diagram of a current source circuit 200a included in the oscillation circuit according to embodiment 2 of the present invention.

The current source circuit 100a is substantially the same as the current source circuit 100 except for the following differences. The different aspects are: a short circuit between the source terminal of the NMOS transistor MN101 and the power supply GND; the resistor 104a is connected between the drain terminal and the gate terminal of the NMOS transistor MN 100; and the gate terminal of the NMOS transistor MN101 is connected to the gate terminal of the NMOS transistor MN100 via the drain terminal of the NMOS transistor MN100 and the resistor 104 a.

The current generated by the current source circuit 100 is affected by the substrate bias effect of the NMOS transistor MN 101. This is because: due to the current flowing through the resistor 104 connected between the source terminal of the NMOS transistor MN101 and the power supply GND, the voltage of the back gate becomes lower than the voltage of the source terminal. The threshold voltage Vth of the NMOS transistor MN100 and the threshold voltage Vth of the NMOS transistor MN101 are not completely equal due to the influence of the substrate bias effect of the NMOS transistor MN 101.

The current source circuit 100a as the 1 st current source circuit has the following configuration: without the resistor 104 connected between the source terminal of the NMOS transistor MN101 and the power supply GND, a substrate bias effect is not generated in the NMOS transistor MN 101. The current source circuit 100a including the configuration in which the NMOS transistor MN101 does not generate the substrate bias effect can cancel the threshold voltages of the NMOS transistor MN100 and the NMOS transistor MN 101.

The differences between the current source circuit 200a and the current source circuit 100a as the 2 nd current source circuit are the same as those between the current source circuit 200 and the current source circuit 100, and therefore, the description thereof is omitted. The oscillation circuit according to the present embodiment includes: a current source circuit 100a including an NMOS transistor MN101 which does not generate a substrate bias effect; and a current source circuit 200a having an NMOS transistor MN201 which does not generate a substrate bias effect, and therefore, the influence of temperature can be reduced.

As described above, according to the oscillation circuit of the present embodiment, an oscillation circuit with a small circuit scale and low power consumption can be obtained.

The present invention is not limited to the above-described embodiments, and various other embodiments than the above-described examples may be implemented in the implementation stage, and various omissions, substitutions, and changes may be made without departing from the gist of the present invention. For example, each switch described in the embodiment of the present invention may be formed of a PMOS transistor or an NMOS transistor. These embodiments and modifications thereof are included in the scope or gist of the invention, and are included in the invention described in the claims and the scope of equivalents thereof.

[ Mark Specification ]

1 an oscillation circuit; 25 resistors; 30. 31 a capacitor; a 40 RS latch; 100. 100a, 200a current source circuits; 110. 210 starting the circuit; 300. 400 a comparison circuit; the ENIN enables the signal input terminal.