阅读说明：本技术 在升华的sic基底上使用碳缓冲的外延生长模板 (Epitaxial growth template using carbon buffering on sublimed SIC substrates ) 是由 金知桓 孔玮 于 2019-10-16 设计创作，主要内容包括：一般地描述了用于形成半导体材料(例如,使用纳米制造)的装置、系统和方法。在一个实例中,方法包括通过硅升华在第一基底上形成碳缓冲层以及在碳缓冲层上形成石墨烯层,随后将石墨烯层移除以便使碳缓冲层暴露并形成制造平台。(Apparatus, systems, and methods for forming semiconductor materials (e.g., using nano-fabrication) are generally described. In one example, a method includes forming a carbon buffer layer on a first substrate by sublimation of silicon and forming a graphene layer on the carbon buffer layer, followed by removing the graphene layer to expose the carbon buffer layer and form a fabrication platform.)

1. A method, comprising:

forming a carbon buffer layer on a first substrate and forming a graphene layer on the carbon buffer layer; and

the graphene layer is removed to expose the carbon buffer layer and form a fabrication platform.

2. The method of claim 1, wherein the first substrate comprises silicon carbide and the graphene layer comprises a single crystal graphene layer.

3. The method of any of claims 1-2, further comprising:

forming a first epitaxial layer on the carbon buffer layer; and

transferring the first epitaxial layer from the carbon buffer layer to a second substrate.

4. The method of claim 3, wherein forming the first epitaxial layer comprises epitaxially growing the first epitaxial layer using the first substrate as a seed.

5. The method of any of claims 3 to 4, further comprising:

forming a second epitaxial layer on the carbon buffer layer after transferring the first epitaxial layer to the second substrate.

6. The method of any of claims 3-5, wherein transferring the first epitaxial layer comprises stripping the first epitaxial layer.

7. The method of any of claims 3-6, wherein transferring the first epitaxial layer comprises:

forming a metal stressor on the first epitaxial layer;

disposing a flexible band over the metal stressor; and

pulling the first epitaxial layer and the metal stressor away from the carbon buffer layer with the flexible strap.

8. The method of any of claims 3-7, wherein the first epitaxial layer comprises a semiconductor.

9. The method of any of claims 3 to 8, wherein the first epitaxial layer comprises a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, and/or a II-VI semiconductor.

10. A method according to any of claims 3 to 9, wherein the first epitaxial layer is fabricated as a semiconductor device.

11. A semiconductor device comprising the first epitaxial layer formed by the method of any one of claims 3 to 9.

Technical Field

Apparatus, systems, and methods for forming semiconductor materials (e.g., using nano-fabrication) are generally described.

Background

In advanced electronic and photonic technology, devices are often fabricated from functional semiconductors such as III-N semiconductors, III-V semiconductors, II-VI semiconductors, and Ge. The lattice constant of these functional semiconductors is typically mismatched with the lattice constant of the silicon substrate. As understood in the art, the lattice constant mismatch between the substrate and the epitaxial layers on the substrate may introduce strain into the epitaxial layers, thereby preventing epitaxial growth of thicker layers without defects. Therefore, a non-silicon substrate is generally employed as a seed for epitaxial growth of most functional semiconductors. However, non-Si substrates having lattice constants that match the lattice constant of the functional material can be expensive, thus limiting the development of non-Si electronic/photonic devices.

Disclosure of Invention

Embodiments of the invention include apparatuses, systems, and methods for nanofabrication. In one example, a method of fabricating a semiconductor device includes forming a carbon buffer layer on a first substrate by sublimation of silicon and forming a graphene layer on the carbon buffer layer. The method also includes removing the graphene layer to expose the carbon buffer layer and form a fabrication platform.

It should be understood that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (so long as such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It is also to be understood that the terms explicitly employed herein, which may also appear in any disclosure incorporated by reference, are to be accorded the meanings most consistent with the specific concepts disclosed herein.

Drawings

The skilled artisan will appreciate that the drawings are primarily for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The figures are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of various features. In the drawings, like reference numbers generally refer to like features (e.g., functionally similar and/or structurally similar elements).

Fig. 1A-1D illustrate methods of fabricating semiconductor devices using layer transfer techniques, according to some embodiments.

Fig. 2A-2C illustrate a method of fabricating a semiconductor device using a fabrication platform fabricated by the method illustrated in fig. 1A-1D, according to some embodiments.

Fig. 3A-3F illustrate methods of pseudo-graphene-based layer transfer according to some embodiments.

Fig. 4 is a photograph of a semiconductor material made according to certain methods of the present invention.

Detailed Description

One approach to addressing the high cost of non-silicon substrates is the "layer transfer" technique, in which a functional device layer is grown on a lattice-matched substrate, and then removed and transferred to another substrate. The remaining lattice matched substrate may then be reused to fabricate another device layer, thereby reducing cost. In order to significantly reduce manufacturing costs, it may be desirable for the layer transfer method to have the following characteristics: 1) substrate reusability; 2) a minimum substrate refurbishment step after layer release; 3) a fast release rate; and 4) precise control of release thickness.

Conventional methods of removing and transferring device layers from lattice-matched substrates include chemical lift-off (also known as epitaxial lift-off or ELO), optical lift-off (also known as laser lift-off or LLO), and mechanical lift-off (also known as controlled lift-off). Unfortunately, none of these approaches have all four of the desirable characteristics described above.

Chemical lift-off techniques can be used to lift off device layers made of III-V semiconductors from GaAs wafers. A sacrificial layer of AlAs is typically epitaxially inserted between the device layer and the substrate. Chemical lift-off techniques selectively etch the sacrificial layer in a wet chemical solution to release the device layer.

While chemical stripping has been progressing over the past thirty years, it still has several drawbacks. For example, the release rate is slow (e.g., typically a few days releasing a single 8 inch wafer) due to the slow permeation of the chemical etchant through the sacrificial layer. Second, after release, the etch residue tends to become a surface contaminant. Third, chemical stripping has limited reusability due to Chemical Mechanical Planarization (CMP) performed after release to restore the rough substrate surface to an epitaxy-ready surface. Fourth, treating the released epitaxial layers in chemical solutions can be challenging.

Optical lift-off techniques typically use a high power laser to illuminate the backside of a lattice-matched substrate (e.g., a transparent sapphire or SiC substrate) and selectively heat the device-substrate interface, thereby causing decomposition of the interface and release of the device layers (e.g., III-N films). This technique can reduce the cost of manufacturing III-N based Light Emitting Diodes (LEDs) and address the problem of heat accumulation from the device by transferring the released III-N to a substrate with high thermal conductivity.

However, optical lift-off has its own limitations. First, because the melted III-N/substrate interface can roughen the substrate, a repair step is typically performed before reuse, reducing reusability to less than five times. Second, local pressurization at the interface caused by high power thermal irradiation may induce cracks or dislocations. Third, the laser scanning speed may be too slow to allow high throughput.

Controlled exfoliation may have a higher throughput than optical exfoliation. In this technique, a high stress film (also referred to as a "stressor") is deposited on the epitaxial film, inducing fracture beneath the epitaxial layer and resulting in active material and radicalsAnd (4) separating the bottom. When sufficient tensile stress is applied to the interface, K_IIThe shear mode may initiate cracks, and K_IThe open mode may allow crack propagation parallel to the interface between the epitaxial layer and the substrate. By controlling the internal stress and thickness of the stressor, it is possible to provide a stress that is sufficient to reach the critical K_IStrain energy of value, resulting in fracture of the film/substrate interface. Because peeling occurs through crack propagation, the peeling process may cause rapid release of the film.

However, controlled exfoliation is not mature enough to be commercially useful for at least the following reasons. First, because crack propagation typically occurs through cleavage planes that are not always aligned perpendicular to the surface, the surface may need to be polished for reuse. Second, thick stressors are often used to provide sufficient energy to dissociate strong covalent bonds, especially when used with high young's modulus materials such as III-N semiconductors. Third, the internal stress of the stressor may only be controlled within a narrow range, which limits the achievable thickness of the resulting spall film. For example, because the maximum internal stress in a typical Ni stressor is about 1GPa, the critical Ni thickness at 1GPa tensile stress that induces spallation of a GaAs film is about 1.5 μm, which may induce spallation of the GaAs film itself if the GaAs is about 10 μm thick. Thus, when using Ni stressors, it can be challenging to fabricate GaAs films less than 10 μm thick, but typically most devices use much thinner films.

The systems and methods described herein according to certain embodiments employ a pseudo-graphene-based layer transfer method to fabricate devices. Which may address one or more of the disadvantages of the layer transfer methods described above. In certain embodiments, the functional device is fabricated on a carbon buffer layer (also referred to as a pseudo graphene layer), which in turn is formed on a SiC substrate. The fabricated functional device may then be removed from the lattice-matched substrate by, for example, a stressor attached to the functional device.

In certain embodiments, the carbon buffer layer serves as a reusable and versatile platform for growing device layers, and also serves as a release layer that allows for rapid, precise, and repeatable release at the graphene surface. The methods described herein may provide one or more advantages over conventional methods. First, the weak interaction between the carbon buffer layer and the device layer can significantly mitigate the lattice mismatch rules of epitaxial growth, potentially allowing the growth of most semiconductor films with low defect densities. Second, due to the weak van der waals interactions between the carbon buffer layer and the epitaxial layer, the epitaxial layer (e.g., functional device) grown on the carbon buffer layer may be released from the substrate easily and accurately, which allows for rapid mechanical release of the epitaxial layer without the need for post-release repair of the release surface. Third, the carbon buffer layer is typically mechanically robust and therefore highly reusable for multiple growth/release cycles.

Fig. 1A-1D illustrate a method 100 of fabricating a semiconductor device by a pseudo graphene layer transfer technique, according to some embodiments. FIG. 1A shows a first substrate 110 (e.g., a SiC substrate) having a first surface 115 that may not be polished. In some embodiments, the first surface 115 can be characterized by a surface roughness substantially equal to or greater than about 100nm (e.g., about 100nm, about 200nm, about 500nm, or greater, including any values and subranges therebetween).

Fig. 1B shows that the first surface 115 of the first substrate 110 is planarized. For example, a Chemical Mechanical Planarization (CMP) process and/or a high temperature hydrogen etch may be employed to reduce the surface roughness of the first substrate. In fig. 1C, the topmost silicon layer is sublimated, and a carbon buffer layer 120 is formed on the first substrate 110 to form a graphene layer 130 on the carbon buffer layer 120 (also referred to as a layer forming step). According to certain embodiments, the graphene layer 130 may interact with the carbon buffer layer 120 by van der waals forces. In some embodiments, the carbon buffer layer 120 may be formed during an early stage of growth of the graphene layer 130. The carbon buffer layer 120 may include, for example, carbon clusters and/or a carbon network. In some embodiments, the carbon buffer layer 120 includes a crystalline structure. In certain embodiments, the crystal structure may be the same or similar to graphene. In some embodiments, the carbon buffer layer is covalently bonded to the underlying substrate. For example, in some embodiments, the carbon buffer layer 120 may be covalently bonded to the first surface 115 of the substrate 110.

In fig. 1D, the graphene layer 130 is removed from the carbon buffer layer 120, thus forming a platform 140 including the first substrate 110 and the carbon buffer layer 120. The platform 140 may be used and reused to fabricate different types of semiconductor devices (as shown in more detail in fig. 2A-2C and the related description below). The carbon buffer layer 120 has a stronger bond to the underlying substrate 110 than the graphene layer 130, allowing for more stable device fabrication in subsequent processes.

The layer forming step shown in fig. 1C may be performed by various methods. In some embodiments, the graphene layer 130 may comprise epitaxial graphene having a single crystal orientation, and the substrate 110 may comprise a (0001)4H-SiC wafer having a silicon surface. The fabrication of the graphene layer 130 may include multiple annealing steps. Can be at H₂A first annealing step is performed in gas for surface etching and a second annealing step may be performed in Ar for graphitization at high temperatures (e.g., at least about 1000 c, such as about 1575 c, or higher).

In some embodiments, the carbon buffer layer 120 and the graphene layer 130 may be grown on the first substrate 110 by a Chemical Vapor Deposition (CVD) process. The substrate 110 may include a nickel substrate or a copper substrate. Alternatively, the substrate 110 may comprise SiO₂、HfO₂、Al₂O₃、Si₃N₄And virtually any other planar material compatible with high temperature CVD. In some embodiments, the carbon buffer layer 120 and the graphene layer 130 may be grown on the first substrate 110 by a Molecular Beam Epitaxy (MBE) technique.

Various methods may also be used to remove the graphene layer 130 from the carbon buffer layer 120 and the first substrate 110. For example, the carrier film may be attached to the graphene layer 130. The carrier film may comprise a thick film of poly (methyl methacrylate) (PMMA) or a thermal release tape, and attachment may be achieved by spin coating.

Fig. 2A-2C illustrate a method 200 of fabricating an epitaxial layer (e.g., which may be used to form a portion of a semiconductor device) using a fabrication platform fabricated by the method illustrated in fig. 1A-1D, according to some embodiments. Fig. 2A shows a schematic view of a fabrication platform 240 including a first substrate 210 and a carbon buffer layer 220 disposed on the first substrate 210. The manufacturing platform may be the same as or substantially similar to the manufacturing platform 140 shown in fig. 1D and described above. In fig. 2B, an epitaxial layer 250 is formed on carbon buffer layer 220 (e.g., by epitaxial growth or any other suitable method). As described below, in some embodiments, epitaxial layer 250 may be epitaxially matched to carbon buffer layer 220. In some embodiments, the epitaxial layer 250 may also be epitaxially matched to the substrate 210.

In fig. 2C, the epitaxial layer 250 is removed from the carbon buffer layer 220. For example, the epitaxial layer 250 may be transferred to another substrate for further processing. After the epitaxial layer 250 is removed, the fabrication platform 240 may be used for another round of fabrication (e.g., forming a second epitaxial layer on the carbon buffer layer 220).

Epitaxial layer 250 may comprise a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor, among others. In one example, the lattice of first substrate 210 is matched to the lattice of epitaxial layer 250, in which case first substrate 210 serves as a seed for growth of epitaxial layer 250 if carbon buffer layer 220 is porous or sufficiently thin. For example, in some cases, carbon buffer layer 220 includes holes and the material forming epitaxial layer 250 may contact underlying first substrate 210 through the holes, allowing the first substrate to seed the growth of epitaxial layer 250. As another example, seeding of the epitaxial layer 250 through the first substrate 210 may occur even when there is no direct contact between the epitaxial layer 250 and the first substrate 210. For example, according to some embodiments, first substrate 210 may have a potential field (e.g., generated by van der waals forces and/or other atomic or molecular forces), and carbon buffer layer 220 may be so thin that the potential field of first substrate 210 reaches beyond carbon buffer layer 220 to interact with the region in which epitaxial layer 250 is formed. Thus, in some embodiments, the potential field from the first substrate 210 affects the growth of the epitaxial layer 250.

Sandwiching the carbon buffer layer 220 between the first substrate 210 and the epitaxial layer 250 may facilitate rapid and damage-free release and transfer of the epitaxial layer 250.

In another example, carbon buffer layer 220 may be thick enough (e.g., several layers thick) to serve as a seed for growing epitaxial layer 250, in which case epitaxial layer 250 may be lattice matched to carbon buffer layer 220. This example also allows for reuse of the first substrate 210. In yet another example, the first substrate 210 together with the carbon buffer layer 220 may serve as a seed for growing the epitaxial layer 250.

In one example, epitaxial layer 250 comprises a 2D material system. In another example, epitaxial layer 250 comprises a 3D material system. The flexibility to fabricate both 2D and 3D material systems allows for the fabrication of a wide range of optical, optoelectronic and photonic devices known in the art.

The fabrication of the epitaxial layer 250 may be performed using any of a variety of semiconductor fabrication techniques known in the art. For example, low pressure metal-organic chemical vapor deposition (MOCVD) may be used to grow an epitaxial layer 250 (e.g., a GaN film) on the carbon buffer layer 220, which in turn is disposed on the first substrate 210 (e.g., a SiC substrate). In this example, the carbon buffer layer 220 and the first substrate 210 may be baked (e.g., at H)₂Is arranged below>Sustained at 1100 deg.C>15 minutes) to clean the surface. The deposition of the epitaxial layer 250 comprising GaN may then be performed at, for example, 200 mbar. Trimethylgallium, ammonia and hydrogen may be used as the Ga source, nitrogen source and carrier gas, respectively. A modified two-step growth may be employed to obtain a flat GaN epitaxial film on the carbon buffer layer 220. The first step may be performed at a growth temperature of 1100 ℃ for several minutes, in which step guided nucleation at the edges of the platform may be promoted. The second growth step may be performed at an elevated temperature of 1250 ℃ to promote lateral growth. The vertical GaN growth rate in this case may be about 20 nm/min.

Fig. 3A-3F illustrate a method 300 of layer transfer according to some embodiments. Fig. 3A shows a carbon buffer layer 320 formed on a donor wafer (donor wafer)310, which may be a single crystal wafer. For example, carbon buffer layer 320 may be grown directly on donor wafer 310, e.g., using any of the methods described above with respect to fig. 1A-1D. Fig. 3B shows epitaxial growth of an epitaxial layer 330 on carbon buffer layer 320. Epitaxial layer 330 may include an electronic layer, a photonic layer, or any other functional device layer. The method of fabricating epitaxial layer 330 may include any of the methods and techniques described above with respect to fig. 2A-2C.

Fig. 3C shows placing stressor 340 on epitaxial layer 330. For example, the stressor 340 may include a high stress metal film, such as a Ni film. In this example, it may be at 1 × 10^-5The vacuum level of torr deposits a Ni stressor in the evaporator.

Fig. 3D illustrates placing a tape layer 350 over the stressor 340 for operating the stressor 340. The use of ribbons 350 and stress sources 340 can mechanically strip the epitaxial layer 330 from the carbon buffer layer 320 at a rapid release rate by applying high strain energy to the interface between the epitaxial layer 330 and the carbon buffer layer 320. The release rate may be rapid due at least to weak van der waals bonding between the carbon buffer layer 320 and other materials, such as the epitaxial layer 330.

In fig. 3E, the released epitaxial layer 330 is disposed on a host wafer (host wafer)360 along with a stressor 340 and a tape layer 350. In fig. 3F, ribbons 350 and stress source 340 are removed, leaving epitaxial layer 330 for further processing such as forming more complex devices on epitaxial layer 330 or depositing additional materials. In one example, tape layer 350 and stress source 340 can be formed by FeCl-based₃The solution of (a) is etched away.

In this method 300, after the epitaxial layer 330 is released as shown in fig. 3D, the remaining donor wafer 310 and carbon buffer layer 320 can be reused for the next cycle of epitaxial layer fabrication. Alternatively, the carbon buffer layer 320 may also be released. In this case, a new carbon buffer layer may be provided and/or formed on the donor wafer 310 prior to the next cycle of epitaxial layer fabrication. In either case, the carbon buffer layer 320 protects the donor wafer 310 from damage, allowing multiple uses and reducing costs. More details can be found in U.S. patent application No. 15/914,295, filed on 7/2018, published on 12/7/2018 as U.S. patent application publication No. 2018/0197736 and entitled "SYSTEMS AND METHODS FOR category BASED LAYER TRANSFER," which is incorporated herein by reference in its entirety.

Fig. 4 is a photograph of a GaN thin film epitaxially grown on a carbon buffer layer, after which the GaN thin film is removed from the surface of the carbon buffer layer by lift-off using a flexible mechanical manipulator. Briefly, a 4 inch diameter (0001)4H-SiC wafer was used as the substrate, where growth was on the silicon face. By first at 1575 ℃ in H₂Annealing in gas, followed by a graphitization step in Ar at 1575 ℃, sublimes the top surface of the SiC wafer, and grows the carbon buffer layer and graphene layer. The graphene layer (which is over the carbon buffer layer and substrate) is then removed using a mechanical release layer, leaving the carbon buffer layer on the SiC substrate. Subsequently, a GaN thin film was grown on the carbon buffer layer using MOCVD. Trimethyl gallium, ammonia and hydrogen were used in a two step growth process, the first step being performed at 1100 ℃ for several minutes and the second step being performed at 1250 ℃. The GaN film was then peeled off the carbon buffer layer using a flexible mechanical manipulator. In fig. 4, the GaN film is shown as a free standing GaN film suspended on a flexible mechanical manipulator (which is used to strip GaN from the carbon buffer layer and substrate).

U.S. provisional application No. 62/746,072, filed 2018, 10, 16 and entitled "epiaxial Growth Template Using Carbon Buffer on coated SiC Substrate," is incorporated by reference in its entirety for all purposes.

While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings of the present invention is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, embodiments of the invention may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

The above-described embodiments may be implemented in any of a variety of ways. For example, embodiments of the design and implementation techniques disclosed herein may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

Further, it should be appreciated that a computer may be embodied in any of a number of forms (e.g., a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer). Further, a computer may be embedded in a device not normally considered a computer but with appropriate processing power, including a Personal Digital Assistant (PDA), a smart phone, or any other suitable portable or fixed electronic device.

In addition, a computer may have one or more input and output devices. These devices may be used, inter alia, to present a user interface. Examples of output devices that may be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound producing devices for audible presentation of output. Examples of input devices that may be used for the user interface include keyboards, as well as pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible form.

Such computers may be interconnected by one or more networks IN any suitable form, including as a local area network or a wide area network, such as an enterprise network, an Intelligent Network (IN), or the internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol, and may include wireless networks, wired networks, or fiber optic networks.

The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

In this regard, the various inventive concepts may be embodied as a computer-readable storage medium (or multiple computer-readable storage media) (e.g., a computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memories, circuit configurations in field programmable gate arrays or other semiconductor devices, or other non-transitory or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media may be transportable, such that the one or more programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

The terms "program" or "software" are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of the embodiments discussed above. Furthermore, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.

Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments.

In addition, the data structures may be stored in any suitable form on a computer readable medium. To simplify the illustration, the data structure may be shown with fields that are related by location in the data structure. Such relationships may also be implemented by allocating storage for fields that convey locations in computer-readable media for relationships between the fields. However, any suitable mechanism may be used to establish relationships between information in fields of a data structure, including through the use of pointers, tags, or other mechanisms that establish relationships between data elements.

Furthermore, various inventive concepts may be embodied as one or more methods, examples of which have been provided. The actions performed as part of the methods may be ordered in any suitable way. Thus, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

All definitions, as defined and used herein, should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and/or general meanings of the defined terms.

Unless explicitly indicated to the contrary, objects modified by no numerical terms as used herein in the specification and claims should be understood to mean "at least one".

The phrase "and/or" as used herein in the specification and claims should be understood to mean "either or both" of the elements so combined, i.e., the elements that are present together in some cases and separately in other cases. Multiple elements listed with "and/or" should be construed in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements specifically identified by the "and/or" clause, other elements may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, when used in conjunction with open-ended language such as "comprising," reference to "a and/or B" may refer in one embodiment to a alone (optionally including elements other than B); may refer to B alone (optionally including elements other than a) in another embodiment; and in yet another embodiment may refer to both a and B (optionally including other elements); and so on.

As used herein in the specification and claims, "or" should be understood to have the same meaning as "and/or" as defined above. For example, when separating items in a list, "or" and/or "should be understood as being inclusive, i.e., including at least one of the number of elements or list of elements, but also including more than one, and optionally including additional unlisted items. To the contrary, terms such as "only one of" or "exactly one of," or "consisting of," when used in a claim, are intended to include exactly one of a number or list of elements. In general, when preceding an exclusive term (e.g., "any," "one," "only one," or "exactly one"), the term "or" as used herein should only be understood to mean an exclusive alternative (i.e., "one or the other but not both"). "consisting essentially of, when used in a claim, shall have its ordinary meaning as used in the patent law field.

As used herein in the specification and claims, the phrase "at least one," when referring to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of each and every element specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. The definition also allows that elements may optionally be present other than the elements specifically identified in the list of elements referred to by the phrase "at least one," whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, "at least one of a and B" (or, equivalently, "at least one of a or B," or, equivalently "at least one of a and/or B") can refer, in one embodiment, to at least one a, optionally including more than one a, with no B present (and optionally including elements other than B); in another embodiment, it may refer to at least one B, optionally including more than one B, with no a present (and optionally including elements other than a); in yet another embodiment, it may refer to at least one a, optionally including more than one a, and at least one B, optionally including more than one B (and optionally including other elements); and so on.

In the claims, as well as in the specification above, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "including," and the like are to be understood to be open-ended, i.e., to mean including but not limited to. The transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively, as set forth in section 2111.03 of the patent examination program manual of the U.S. patent office.