阅读说明：本技术 一种跨时钟域处理电路 (Cross-clock domain processing circuit ) 是由 白玉晶 刘旭辉 于 2018-12-29 设计创作，主要内容包括：一种跨时钟域处理电路,用于以较低的延时实现数据在异步时钟域之间的处理。该跨时钟域处理电路包括相位对齐电路(330)和同步电路(340),其中相位对齐电路(330)用于根据输入数据恢复出的、包含输入数据时钟的相位变化信息的控制信号来调整来自本地的工作时钟的相位,使得该工作时钟与输入数据时钟相位对齐,并将上述输入数据时钟和工作时钟作为同步电路的时钟以同步上述输入数据。以输入数据时钟恢复出的控制信号来调整本地的工作时钟的相位,使得输入数据时钟和调整后的工作时钟可以以较低的延迟同步输入数据,使得数据经过跨时钟域处理电路的时延变小。(A clock domain crossing processing circuit is used for realizing the processing of data between asynchronous clock domains with low delay. The clock domain crossing processing circuit comprises a phase alignment circuit (330) and a synchronization circuit (340), wherein the phase alignment circuit (330) is used for adjusting the phase of a local working clock according to a control signal which is recovered by input data and contains phase change information of an input data clock, so that the working clock is aligned with the phase of the input data clock, and the input data clock and the working clock are used as clocks of the synchronization circuit to synchronize the input data. The phase of the local working clock is adjusted by the control signal recovered by the input data clock, so that the input data clock and the adjusted working clock can synchronously input data with lower delay, and the time delay of the data passing through the clock domain crossing processing circuit is reduced.)

A cross-clock-domain processing circuit for cross-clock-domain processing of received input data, the cross-clock-domain processing circuit comprising a phase alignment circuit and a synchronization circuit, wherein:

the phase alignment circuit is configured to receive an input data clock and a first working clock, adjust a phase of the first working clock according to a first control signal, output the phase-adjusted first working clock to the synchronization circuit as an output data clock, align a phase of the output data clock with a phase of the input data clock, where the input data clock is a clock recovered according to the input data, the first working clock is a working clock of the clock domain crossing processing circuit, a frequency of the first working clock is equal to a frequency of the input data clock, the first control signal is a control signal recovered according to the input data, and the first control signal includes phase change information of the input data clock;

the synchronization circuit is configured to perform clock domain crossing synchronization on the input data according to the input data clock and the output data clock to generate synchronization data, where the synchronization data is in a clock domain of the output data clock.

The cross-clock-domain processing circuit of claim 1, wherein the phase alignment circuit comprises a phase detector, a digital filter, and a phase interpolator, wherein:

the phase discriminator is used for discriminating the phase of the input data clock and the output data clock and outputting a phase discrimination result;

the digital filter is used for filtering jitter of the phase discrimination result and the first control signal and outputting the filtered jitter result to the phase interpolator as a second control signal;

the phase interpolator is configured to adjust a phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with a phase of the input data clock, and output the phase-adjusted first working clock to the synchronization circuit and the phase discriminator as the output data clock.

The cross-clock-domain processing circuit of claim 2, wherein the phase interpolator is further to:

generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

adjusting phases of the first operating clock and the second intermediate clock according to the second control signal such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The phase detector is further to:

performing phase discrimination on the output data clock, the second intermediate clock and the input data clock, and determining a phase relationship among the output data clock, the second intermediate clock and the input data clock to output the phase discrimination result.

The cross-clock-domain processing circuit of claim 3, wherein the phase interpolator is further to:

the second control signal is for instructing the phase interpolator to hold the phases of the first operating clock and the second intermediate clock when the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock;

when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first working clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock;

when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is in a state for instructing the phase interpolator to adjust the phases of the first operating clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The cross-clock-domain processing circuit of any of claims 2 to 4, wherein the digital filter is configured to filter jitter of the first control signal and the phase detection result to a high frequency jitter, wherein the filtered first control signal includes phase change information corresponding to a low frequency jitter of the input data clock.

The cross-clock domain processing circuit of claim 5, wherein the phase change information comprises independent clock spread spectrum information, independent clock non-spread spectrum information, or homologous clock information.

The cross-clock domain processing circuit of any of claims 1 to 6, further comprising a first clock circuit to provide the first operating clock to the phase alignment circuit.

The cross-clock domain processing circuit of claims 1-7, further comprising a clock recovery circuit, wherein:

the clock recovery circuit is configured to receive the input data, recover a clock in the input data to obtain the input data clock and the first control signal, and output the input data, the input data clock, and the first control signal.

The cross-clock-domain processing circuit of any of claims 1 to 8, wherein the synchronization circuit comprises a first sub-synchronization circuit and a second sub-synchronization circuit, wherein:

the first sub-synchronization circuit is used for synchronizing the input data according to the input data clock to obtain first temporary data;

the second sub-synchronization circuit is used for synchronizing the first temporary data according to the output data clock to obtain the synchronous data.

The cross-clock-domain processing circuit of claim 9, wherein the first sub-synchronization circuit and the second sub-synchronization circuit are registers, wherein the first operating clock of the first sub-synchronization circuit is the input data clock and the first operating clock of the second sub-synchronization circuit is the output data clock.

The cross-clock-domain processing circuit of any of claims 1 to 10, wherein the input data is serial data, wherein:

the clock domain crossing processing circuit further comprises a serial-to-parallel circuit, and the serial-to-parallel circuit is used for performing serial-to-parallel conversion on the input data and outputting the converted input data to the synchronous circuit.

A retimer for relaying N input data in a transmission link, comprising: the circuit comprises a phase alignment circuit and N synchronous circuits, wherein N is more than or equal to 1 and is a positive integer, wherein:

the phase alignment circuit is used for receiving an input data clock and a first working clock, adjusting the phase of the first working clock according to a first control signal, outputting the first working clock after phase adjustment to the N synchronous circuits as an output data clock, the phase of the output data clock is aligned with the phase of the input data clock, the input data clock is one of N recovered data clocks recovered from the N paths of input data, the first working clock is a working clock of the retimer, the frequency of the first working clock is equal to the frequency of the input data clock, the first control signal is one of N control signals recovered according to the N paths of input data, and the first control signal comprises phase change information of the input data clock;

each of the N synchronization circuits is configured to perform clock domain crossing synchronization on each of the N input data according to the input data clock and the output data clock to generate one of N synchronization data, where the N synchronization data is in a clock domain of the output data clock.

The retimer of claim 12, wherein the phase alignment circuit comprises a phase detector, a digital filter, and a phase interpolator, wherein:

the phase discriminator is used for discriminating the phase of the input data clock and the output data clock and outputting a phase discrimination result;

the digital filter is used for filtering jitter of the phase discrimination result and the first control signal and outputting the filtered jitter result to the phase interpolator as a second control signal;

the phase interpolator is configured to adjust a phase of the first working clock according to the second control signal, so that the phase of the first working clock is aligned with a phase of the input data clock, and output the phase-adjusted first working clock to the N synchronization circuits and the phase discriminator as the output data clock.

The retimer of claim 13, wherein the phase interpolator is further to:

generating a second intermediate clock according to the first working clock, wherein the phase difference between the first working clock and the second intermediate clock is a preset phase difference;

adjusting phases of the first operating clock and the second intermediate clock according to the second control signal such that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The phase detector is further to:

performing phase discrimination on the output data clock, the second intermediate clock and the input data clock, and determining a phase relationship among the output data clock, the second intermediate clock and the input data clock to output the phase discrimination result.

The retimer of claim 14, wherein the phase interpolator is further to:

the second control signal is for instructing the phase interpolator to hold the phases of the first operating clock and the second intermediate clock when the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock;

when the phase of the input data clock lags the phase of the first working clock and lags the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first working clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first working clock and lags the phase of the second intermediate clock;

when the phase of the input data clock leads the phase of the first operating clock and leads the phase of the second intermediate clock, the second control signal is used for instructing the phase interpolator to adjust the phases of the first operating clock and the second intermediate clock so that the phase of the input data clock leads the phase of the first operating clock and lags the phase of the second intermediate clock.

The retimer of any of claims 13 to 15, wherein filtering of the first control signal and the phase detection result by the digital filter is high frequency filtering, wherein the filtered first control signal comprises phase change information corresponding to low frequency jitter of the input data clock.

The retimer of claim 16, wherein the phase change information comprises independent clock spread spectrum information, independent clock non-spread spectrum information, or homologous clock information.

The retimer of any of claims 12 to 17, further comprising a first clock circuit to provide the first operating clock to the phase alignment circuit.

The retimer of claims 12 to 18, further comprising N clock recovery circuits, wherein:

the N clock recovery circuits are configured to receive the N input data, recover clocks in the N input data, obtain the N recovered data clocks and the N first control signals, and output the N input data, the N recovered data clocks, and the N control signals.

The retimer of any of claims 12 to 19, wherein the synchronization circuit comprises a first subsynchronization circuit and a second subsynchronization circuit, wherein:

the first sub-synchronization circuit is used for synchronizing the input data according to the input data clock to obtain first temporary data;

the second sub-synchronization circuit is used for synchronizing the first temporary data according to the output data clock to obtain the synchronous data.

The retimer of claim 20, wherein the first subsynchronous circuit and the second subsynchronous circuit are registers, wherein the first operating clock of the first subsynchronous circuit is the input data clock, and wherein the first operating clock of the second subsynchronous circuit is the output data clock.

The retimer of any of claims 12 to 21, wherein the N input data are N serial data, wherein:

the retimer further includes N serial-parallel circuits, and is characterized in that the N serial-parallel circuits are configured to respectively perform serial-parallel conversion on the N paths of input data, and respectively output the converted N paths of input data to the N synchronization circuits.

The retimer of any of claims 12 to 22, wherein the N ways of synchronization data are N ways of parallel data, wherein:

the retimer further includes N parallel-to-serial circuits, and is characterized in that the N parallel-to-serial circuits are configured to convert the N paths of synchronous data into N paths of serial output data, and output the converted N paths of serial output data.

The retimer of any of claims 19 to 23, further comprising N data processing circuits and N data selectors, wherein:

the input ends of the N data processing circuits are respectively coupled with the output ends of the N clock recovery circuits, the output ends of the N data processing circuits are respectively coupled with the input ends of the N data selectors, and the N data processing circuits are used for respectively decoding, descrambling, synchronizing, scrambling and encoding the received N paths of input data;

for each of the data processing circuits, the clock recovery circuits, and the data selector coupled to each other, wherein:

two input ends of the data selector are respectively coupled with the output end of the clock recovery circuit and the output end of the data processing circuit, and the output end of the data selector is coupled with the output end of the synchronous circuit.

The retimer of any of claims 12 to 24, wherein the retimer is a multi-channel retimer, wherein N ≧ 2, and N is a positive integer.