阅读说明：本技术 一种跨时钟域处理电路 (Cross-clock domain processing circuit ) 是由 白玉晶 刘旭辉 于 2018-12-29 设计创作，主要内容包括：一种跨时钟域处理电路,用于以较低的延时实现数据在异步时钟域之间的处理。该跨时钟域处理电路包括相位对齐电路(330)和同步电路(340),其中相位对齐电路(330)用于根据输入数据恢复出的、包含输入数据时钟的相位变化信息的控制信号来调整来自本地的工作时钟的相位,使得该工作时钟与输入数据时钟相位对齐,并将上述输入数据时钟和工作时钟作为同步电路的时钟以同步上述输入数据。以输入数据时钟恢复出的控制信号来调整本地的工作时钟的相位,使得输入数据时钟和调整后的工作时钟可以以较低的延迟同步输入数据,使得数据经过跨时钟域处理电路的时延变小。(A clock domain crossing processing circuit is used for realizing the processing of data between asynchronous clock domains with low delay. The clock domain crossing processing circuit comprises a phase alignment circuit (330) and a synchronization circuit (340), wherein the phase alignment circuit (330) is used for adjusting the phase of a local working clock according to a control signal which is recovered by input data and contains phase change information of an input data clock, so that the working clock is aligned with the phase of the input data clock, and the input data clock and the working clock are used as clocks of the synchronization circuit to synchronize the input data. The phase of the local working clock is adjusted by the control signal recovered by the input data clock, so that the input data clock and the adjusted working clock can synchronously input data with lower delay, and the time delay of the data passing through the clock domain crossing processing circuit is reduced.)