阅读说明：本技术 半导体封装件及制造方法 (Semiconductor package and manufacturing method ) 是由 陈玮佑 庄钧智 何冠霖 梁裕民 吴俊毅 于 2020-10-28 设计创作，主要内容包括：本申请的实施例提供一种半导体封装件包括：没有任何有源器件的插件结构。插件结构包括：互连器件；介电膜,围绕互连器件；以及第一金属化图案,接合至互连器件。封装件还包括：第一器件管芯,接合至第一金属化图案的与互连器件相反的一侧；以及第二器件管芯,接合至第一金属化图案的与第一器件管芯相同的一侧。互连器件将第一器件管芯电连接至第二器件管芯。本申请的实施例还提供一种制造半导体封装件的方法。(An embodiment of the present application provides a semiconductor package including: there is no plug-in structure for any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package further includes: a first device die bonded to a side of the first metallization pattern opposite the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. An interconnect device electrically connects the first device die to the second device die. Embodiments of the present application also provide a method of manufacturing a semiconductor package.)

1. A semiconductor package, comprising:

an interposer structure without any active devices, the interposer structure comprising:

an interconnect device;

a dielectric film surrounding the interconnect device; and

a first metallization pattern bonded to the interconnect device;

a first device die bonded to a side of the first metallization pattern opposite the interconnect device; and

a second device die bonded to the same side of the first metallization pattern as the first device die, wherein the interconnect device electrically connects the first device die to the second device die.

2. The semiconductor package of claim 1, wherein the interposer structure further comprises: a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die.

3. The semiconductor package of claim 1, wherein the interconnect device is a flip chip bonded to the first metallization pattern.

4. The semiconductor package of claim 1, wherein the interconnect device comprises:

a semiconductor substrate; and

a first interconnect structure on the semiconductor substrate, wherein the first interconnect structure includes electrical routing of circuitry signals between the first device die and the second device die.

5. The semiconductor package of claim 4, wherein the pitch of the electrical wires is in the range of 0.1 μm to 5 μm.

6. The semiconductor package of claim 1, wherein the interposer structure further comprises:

a second interconnect structure on a side of the dielectric film opposite the first metallization pattern; and

a through via extending through the dielectric film, wherein the through via electrically connects the second interconnect structure to the first metallization pattern.

7. The semiconductor package of claim 1, wherein the first device die and the second device die are each directly bonded to the first metallization pattern.

8. A semiconductor package, comprising:

an interposer, without active devices, the interposer comprising:

an interconnect device, the interconnect device comprising:

a semiconductor substrate; and

a first interconnect structure on the semiconductor substrate;

a passive device;

a dielectric film burying the interconnect device and the passive device; and

a first metallization pattern over the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to a first surface of the first metallization pattern by a first solder region, and the passive device is bonded to the first surface of the first metallization pattern by a second solder region;

a first device die directly bonded to a second surface of the first metallization pattern through a third solder region, wherein the first surface of the first metallization pattern is opposite the second surface of the first metallization pattern;

a second device die directly bonded to the second surface of the first metallization pattern through a fourth solder region, wherein electrical routing in the first interconnect structure routes signals between the first device die and the second device die; and

a central substrate directly bonded to a side of the interposer opposite the first device die and the second device die.

9. The semiconductor package of claim 8, wherein the passive device is electrically connected to the first device die or the second device die.

10. A method of fabricating a semiconductor package, comprising:

bonding an interconnect device to the first surface of the first metallization pattern, the interconnect device being devoid of any active devices;

bonding a passive device to the first surface of the first metallization pattern, the passive device being devoid of any active device;

burying the interconnect device and the passive device in a dielectric film;

bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite the first surface; and

bonding a second device die to the second surface of the first metallization pattern, wherein the interconnect device routes signals between the first device die and the second device die.

Technical Field

Embodiments of the present application provide a semiconductor package and a method of manufacturing the same.

Background

The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, iterative reduction of minimum feature size can increase integration density, allowing more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need has arisen for smaller and more inventive semiconductor die packaging techniques. One example of such a packaging system is package on package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and small footprint on a Printed Circuit Board (PCB).

Disclosure of Invention

According to some embodiments, a package comprises: there is no plug-in structure for any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package further includes: a first device die bonded to a side of the first metallization pattern opposite the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. An interconnect device electrically connects the first device die to the second device die. In some embodiments, the insert structure further comprises: a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die.

According to some embodiments, a package comprises: a plug-in without an active device; the plug-in includes: an interconnect device, the interconnect device comprising: a semiconductor substrate; and a first interconnect structure on the semiconductor substrate; a passive device; dielectric films, buried interconnect devices and passive devices; and a first metallization pattern over the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to the first surface of the first metallization pattern by a first solder region, and the passive device is bonded to the first surface of the first metallization pattern by a second solder region; a first device die directly bonded to a second surface of the first metallization pattern through a third solder region, wherein a first surface of the first metallization pattern is opposite the second surface of the first metallization pattern; a second device die directly bonded to the second surface of the first metallization pattern through a fourth solder region, wherein electrical routing in the first interconnect structure routes signals between the first device die and the second device die; and a central substrate directly bonded to a side of the interposer opposite the first device die and the second device die.

According to some embodiments, a method comprises: bonding an interconnect device to the first surface of the first metallization pattern, the interconnect device being devoid of any active devices; bonding a passive device to the first surface of the first metallization pattern, the passive device being devoid of any active device; burying the interconnect device and the passive device in a dielectric film; bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite the first surface; a second device die is bonded to the second surface of the first metallization pattern, wherein the interconnect device is to route signals between the first device die and the second device die.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of an interconnect device according to some embodiments;

fig. 2, 3, 4, 5A, 5B, 6, 7, 8, 9, 10, and 11 illustrate cross-sectional views of intermediate steps in fabricating an interposer structure incorporating an interconnect device, in accordance with some embodiments;

12A, 12B, 13A, 13B, 14A, 14B, and 16 show variations of intermediate steps in fabricating a package incorporating an interposer structure, according to some embodiments;

fig. 15 illustrates a cross-sectional view of a device die in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) elements or components as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the present disclosure, various aspects of packages and their formation are described. Various embodiments may use heterogeneous integration to provide a package with device dies, interconnect devices, and passive devices. Three-dimensional (3D) packages include interposer structures with internal interconnection devices. The interconnect device provides electrical interconnections between device dies (e.g., system on a chip (SoC), other functional dies, hybrid memory data Sets (HBMs), other memory dies, multifunction dies, etc.) that are directly bonded to the interposer fabric. The interposer structure may further include a passive device (e.g., an Integrated Passive Device (IPD)). In various embodiments, the interposer structure electrically connects the device die to another component (e.g., a motherboard, etc.) through the central substrate. By bonding the device die directly to the interposer structure, yield loss of separately packaged expensive device die may be reduced. Additionally, by integrating passive devices within the package structure, power/insertion loss may be reduced, and/or circuit speed may be increased, thereby improving the performance of the package. Gain may also be achieved by placing the passive device die closer to the device die. According to some embodiments, an intermediate stage of forming a package is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements formed using like processes.

Fig. 1 illustrates a cross-sectional view of an interconnect device 50 according to some embodiments. The interconnect device 50 will be incorporated into the interposer structure 200 (see fig. 11) in a subsequent process to form a semiconductor package 250 (see fig. 14A and 14B). Interconnect device 50 provides electrical connections between devices that are directly bonded to interposer structure 200 in semiconductor package 250, for example, between logic die 54A and memory die 54B (see fig. 14A and 14B). The interconnect device 50 may be formed using an applicable manufacturing process. The interconnect device 50 may have no active devices and/or no passive devices. For example, interconnect device 50 may be devoid of any transistors, diodes, and/or the like. Additionally, interconnect device 50 may be devoid of, or devoid of, any capacitors, resistors, inductors, and/or the like. In some embodiments, interconnect device 50 may have a thickness between about 10 μm and about 300 μm. In some embodiments, interconnect device 50 may have lateral dimensions between about 1mm by 1mm and about 10mm by 100 mm.

Still referring to fig. 1, interconnect device 50 may include an interconnect structure 62 formed on a substrate 60. The substrate 60 may be, for example, a glass substrate, a ceramic substrate, a semiconductor substrate, or the like. In some embodiments, the substrate 60 may be a silicon wafer or an active layer of a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 60 may comprise a semiconductor material such as doped or undoped silicon, or may comprise other semiconductor materials, for example: germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, a plurality of interconnect devices 50 may be formed on a single substrate 60 and singulated to form individual interconnect devices 50, such as the individual interconnect devices 50 shown in fig. 1. Substrate 60 may be referred to as having a front or front surface (e.g., the side facing upward in fig. 1), and a back or back surface (e.g., the side facing downward in fig. 1). In embodiments where substrate 60 comprises silicon, interconnect device 50 may also be referred to as a silicon bus or a silicon bridge.

In some embodiments, interconnect device 50 includes one or more layers of electrical wiring 64 (e.g., wires and/or vias) formed in interconnect structure 62 over substrate 60. The electrical wiring 64 may be formed by one or more layers of conductive lines in a dielectric (e.g., low-k dielectric material) material and have conductive vias interconnecting the layers of conductive lines. For example, the electrical wiring 64 may include one to three conductor layers. In other embodiments, the electrical wiring 64 may include a different number of conductor layers. Conductive vias may extend through the dielectric to provide vertical connections between the wire layers. The electrical wiring 64 may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

In some embodiments, the electrical wiring 64 is formed using a damascene process in which a corresponding dielectric layer is patterned and etched using photolithographic techniques to form trenches corresponding to the desired pattern of metallization layers and/or vias. An optional diffusion barrier layer and/or an optional adhesion layer may be deposited and the trench may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum nitride, titanium oxide, or other alternatives; while suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In one embodiment, the metallization layer may be formed by depositing a seed layer of copper or copper alloy and filling the trench by electroplating. A Chemical Mechanical Planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the respective dielectric layer and to planarize the surface for subsequent processing.

In some embodiments, the use of a damascene or dual damascene process may allow for the formation of electrical wires 64 with smaller pitches (e.g., "fine pitch wires"), which may increase the density of the electrical wires 64, and may also allow for improved conduction and connection reliability within the interconnect device 50. For example, the electrical wiring 64 may have a pitch (e.g., spacing between adjacent wires) in a range of about 0.1 μm to about 5 μm. In some cases, during high speed operations (e.g., greater than about 2 Gbit/sec), electrical signals may be conducted near the surface of the conductive component. The fine pitch wiring may have a smaller surface roughness than other types of wiring, and thus may reduce resistance experienced by high speed signals, and may also reduce signal loss (e.g., insertion loss) during high speed operations. This may improve the high speed operational performance of, for example, a serializer/deserializer ("SerDes") circuit or other circuit that may operate at higher speeds. In this way, when interconnect structure 50 is integrated in package device 200, interconnect structure 50 can provide high-speed signal routing between device dies that are bonded to package structure 200 (see fig. 14A and 14B).

In some embodiments, interconnect device 50 also includes pads 68, such as aluminum pads, to which external connections are made. The pads 68 may be formed on the interconnect structure 62 and electrically connected to the electrical wiring 64. In some embodiments, one or more passivation films 66 are formed on portions of the interconnect structure 62 and the pads 68. An opening extends through the passivation film 66 to the pad 68, and a conductive connector 71 extends through the opening in the passivation film 66 to contact the pad 68.

In some embodiments, the conductive connector 71 includes a metal pad or metal pillar (e.g., copper pillar) 70 on which a solder region 72 is disposed. In some embodiments, the metal pillar 70 may have substantially vertical sidewalls. Alternatively, the metal post 70 may be omitted and the solder region 72 may be disposed directly on the pad 68. The solder regions 72 may facilitate testing of the interconnect device 50.

In some embodiments, the conductive connector 71 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, a metal cap layer is formed on top of the metal pillar 70. The metal capping layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connectors 71 are formed using a plating process.

Fig. 2-11 illustrate cross-sectional views of intermediate steps during a process for forming an interposer structure 200 incorporating an interconnect device 50, in accordance with some embodiments. In fig. 2, a carrier substrate 100 is provided. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. As shown in fig. 2, a exfoliation layer 102 may be formed over a carrier substrate 100. The release layer 102 may be formed of a polymer-based material that may be removed with the carrier substrate 100 from an overlying structure to be formed in a subsequent step. In some embodiments, release layer 102 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In further embodiments, the release layer 102 may be an Ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The peel-off layer 102 may be dispensed in fluid form and cured, may be a laminated film laminated to the first carrier substrate 100, or may be the like. The top surface of the exfoliation layer 102 may be horizontal and may have a high degree of planarity.

Still referring to fig. 2, a seed layer 104 is formed on the lift-off layer 102. In some embodiments, the seed layer 104 is a metal layer, which may be a single layer, or may be a composite layer comprising multiple sub-layers formed of different materials. In a particular embodiment, the seed layer 104 includes a titanium layer and a copper layer over the titanium layer. The seed layer 104 may be formed using, for example, Physical Vapor Deposition (PVD) or the like.

In fig. 3, an optional dielectric layer 106 may be formed on the seed layer 104. A bottom surface of the dielectric layer 106 may contact a top surface of the seed layer 104. In some embodiments, the dielectric layer 106 is formed from a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In further embodiments, the dielectric layer 106 is formed by a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 106 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, the like, or combinations thereof.

The dielectric layer 106 is then patterned to form an opening 108 that exposes a portion of the seed layer 104. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer 106 to light when the dielectric layer 106 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 106 is a photosensitive material, the dielectric layer 106 may be developed after exposure. After forming the opening 108, a curing process may be applied to harden the dielectric layer 106. Alternatively, another method, such as etching, laser drilling, etc., may be used to pattern the dielectric layer 106.

In fig. 4, an optional pre-solder region 110 is formed in the opening 108. In some embodiments, the pre-solder region 110 may include Sn-Ag, Sn-Cu, Sn-Ag-Cu, combinations thereof, or the like. The pre-solder region 110 may be formed by electroplating in the opening 108 using the exposed portion of the seed layer 104. Alternatively, the pre-solder region 110 may be formed using a pick-and-place tool using a ball drop process, a mounting process, or the like. In such embodiments, the seed layer 104 may be omitted.

In fig. 5A, a dielectric layer 112 and a metallization pattern 114 are formed over the dielectric layer 106 and the pre-solder region 110. The metallization pattern 114 may include conductive pillars 114A within the dielectric layer 112 and conductive pads 114B over the dielectric layer 112. In some embodiments, metallization pattern 114 also includes redistribution lines (RDLs) electrically connected to the conductive pads. In such embodiments, the RDL of the metallization pattern 114 redistributes the electrical signal, the power signal, or the ground signal over the top surface of the dielectric layer 112.

In some embodiments, the dielectric layer 112 is formed by a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. In further embodiments, the dielectric layer 112 is formed by a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 112 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, the like, or combinations thereof. The material of the dielectric layer 112 may be the same as or different from the material of the dielectric layer 106.

After formation, the dielectric layer 112 may then be patterned to form openings that expose portions of the pre-solder region 110. Patterning may be performed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure. After forming the openings, a curing process may be applied to harden the dielectric layer 112. Alternatively, another method, such as etching, laser drilling, etc., may be used to pattern the dielectric layer 112.

A metallization pattern 114 is then formed. As an example to form metallization pattern 114, a seed layer (not shown) is formed over dielectric layer 112. A seed layer may further be formed on the sidewalls and bottom surface of the opening in the dielectric layer 112. In some embodiments, the seed layer is a metal layer, which may be a single layer, or may be a composite layer comprising multiple sub-layers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 114. The patterning forms openings through the photoresist, exposing the seed layer. A conductive material is formed in the opening in the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. And removing the photoresist and the part of the seed layer where the conductive material is not formed. The photoresist may be removed by an acceptable ashing process or a stripping process such as using an oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer may be removed, for example, by using an acceptable etching process, such as by wet or dry etching. The seed layer and the remaining portion of the conductive material form the metallization pattern 114.

Fig. 5B shows an alternative embodiment in which the dielectric layer 106 and the pre-solder region 110 are omitted. In such embodiments, the dielectric layer 112 and the metallization pattern 114 may be formed directly on the seed layer 104. The metallization pattern 114 may be formed as described above with respect to fig. 5A. Alternatively, the dielectric layer 106 may be formed directly on the lift-off layer 102, and after deposition and patterning of the dielectric layer 112, the seed layer 104 may be deposited over and within the dielectric layer 112. In such embodiments, the seed layer 104 serves as a seed layer to form the metallization pattern 114, such that a separate seed layer is not required.

In fig. 6, one or more interconnect devices 50 (see, e.g., fig. 1) are bonded to metallization pattern 114 through conductive connectors 71. For example, the solder regions of the conductive connectors 71 may be bonded to the metallization patterns 114 using a flip-chip bonding process. A reflow process may be applied to adhere the solder regions of the conductive connectors 71 to the metallization pattern 114. Although fig. 6 illustrates the conductive connector 71 as including only solder regions, in further embodiments, the conductive connector 71 may have a different configuration. For example, the conductive connector 71 may include a solder region disposed on the conductive post (see, e.g., solder region 72 on conductive post 70 of fig. 1 and 14B). Interconnect device 50 may be used to provide electrical connections between device dies that are subsequently bonded to interposer structure 200 (see fig. 14A and 14B).

As also shown in fig. 6, the passive devices 52 may also be bonded to the metallization pattern 114 by conductive connectors 116. For example, the conductive connectors 116 may include solder regions that are bonded to the metallization patterns 114 using a flip-chip bonding process. A reflow process may be applied to adhere the solder regions of the conductive connectors 116 to the metallization pattern 114.

The passive devices 52 may be similar to the interconnect device 50. For example, passive device 52 may include a substrate (e.g., similar to substrate 60), an interconnect structure formed on the substrate (e.g., similar to interconnect structure 62), and a conductive connector 116 (e.g., similar to conductive connector 71). Conductive connector 116 may provide electrical routing in the interconnect structure that is electrically connected to passive device 52. Electrical wiring in the interconnect structure of passive device 52 may be patterned to provide one or more passive circuit elements, such as capacitor(s), resistor(s), inductor(s), etc., or a combination thereof. The passive devices 52 may be devoid of any active devices (e.g., transistors).

Although only one interconnect device 50 and one passive device 52 are shown in fig. 6, any number of interconnect devices 50 and/or passive devices 52 may be bonded to metallization pattern 114. In addition, the passive device 52 is optional and may be omitted depending on the configuration of the package. For example, in further embodiments, the passive devices 52 may be replaced with further interconnect devices 50.

Still referring to fig. 6, an underfill 118 may be deposited around the conductive connectors 71 and 116. Underfill 118 may be formed by a capillary flow process after interconnect device 50 and passive device 52 are connected, or may be formed by a suitable deposition method before interconnect device 50 and passive device 52 are connected. Underfill 118 may be disposed between interconnect device 50 and metallization pattern 114/dielectric layer 112. Underfill 118 may also be disposed between passive device 52 and metallization pattern 114/dielectric layer 112. Although fig. 6 shows spaced apart portions of underfill 118 between each interconnect device 50 and passive device 52, in further embodiments, underfill 118 may extend continuously under interconnect device 50 and passive device 52.

In fig. 7, through vias 120 are formed over metallization pattern 114. As an example to form the through via 120, a photoresist is formed and patterned on the metallization pattern 114. The photoresist may bury the interconnect devices 50 and the passive devices 52. The photoresist may be formed by spin coating or the like, and may be exposed for patterning. The pattern of the photoresist corresponds to the through holes 120. The patterning forms openings through the photoresist, exposing the metallization pattern 114. A conductive material is formed in the openings of the photoresist, as well as on the exposed portions of the metallization pattern 114. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The photoresist is then removed. The photoresist may be removed by an acceptable ashing process or a stripping process such as using an oxygen plasma. The conductive material forms the through via 120. In fig. 7, through vias 120 extend above the top surfaces of interconnect device 50 and passive device 52. Additional configurations are also possible.

In fig. 8, a dielectric film 122 is formed over and around interconnect device 50, passive device 52, and through via 120. The dielectric film 122 may fill gaps between the interconnect devices 50, the passive devices 52, and the through holes 120, and the dielectric film 122 may also bury the interconnect devices 50, the passive devices 52, and the through holes 120. In some embodiments, the dielectric film 122 is formed by a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In further embodiments, the dielectric film 122 is an underfill, which may or may not include a filler material (e.g., silicon oxide). In further embodiments, the dielectric film 122 is formed by a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric film 122 may be formed by any acceptable deposition process such as lamination, spin coating, CVD, the like, or combinations thereof. Alternatively, the dielectric film 122 may be cured after deposition. In further embodiments, the dielectric film 122 may be replaced with a molding compound, epoxy, or the like, which may be applied by compression molding, transfer molding, lamination, or the like.

In fig. 9, a planarization process is performed on the dielectric film 122 to expose the through via 120. The planarization process may also remove material through the holes 120. The top surfaces of the through via 120 and the dielectric film 122 may be coplanar after the planarization process. The planarization process may be, for example, Chemical Mechanical Polishing (CMP), an abrasive process, or the like. In some embodiments, planarization may be omitted, for example, if the through via 120 has been exposed after depositing the dielectric film 122.

In fig. 10, interconnect structure 136 is formed over dielectric film 122, through via 120, interconnect device 50, and passive device 52. In the illustrated embodiment, the interconnect structure 136 includes dielectric layers 124, 128, 132, and 138, and metallization patterns 126, 130, and 134 (sometimes referred to as redistribution layers or redistribution lines). Specifically, the dielectric layer 124 is formed over the dielectric film 122; a dielectric layer 128 is formed over dielectric layer 124 and metallization pattern 126; a dielectric layer 132 is formed over the dielectric layer 128 and the metallization pattern 130; a dielectric layer 138 is formed over dielectric layer 132 and metallization pattern 134. In addition, the via portions of metallization pattern 134 extend through dielectric layer 132; the via portions of metallization pattern 130 extend through dielectric layer 128; the via portion of metallization pattern 126 extends through dielectric layer 124.

The dielectric layers 124, 128, 132, and 138 may be formed using similar materials and similar processes as the dielectric layer 112, and further description of the dielectric layers 124, 128, and 132 is omitted for the sake of brevity.

Metallization patterns 126, 130, and 134 may be formed using similar materials and similar processes as metallization pattern 114, and further description of metallization patterns 126, 130, and 134 is omitted for the sake of brevity. Metallization patterns 126, 130, and 134 may be electrically connected to through vias 120, which electrically connect metallization patterns 126, 130, and 134 to metallization pattern 114, interconnect device 50, and passive device 52. The metallization patterns 126, 130, and 134 may provide conductive lines that provide signal routing, power lines, and/or ground lines in the completed package 250 (see fig. 14A and 14B). In some embodiments, one or more metallization patterns 126, 130, or 134 may provide fine pitch conductive lines for fine pitch routing. For example, the pitch of one or more metallization patterns 126, 130, or 134 may be in the range of 20 μm to 100 μm.

It should be understood that the second interconnect structure 136 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, steps and processes similar to those discussed above may be repeated. The metallization pattern may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming a seed layer and a conductive material of the metallization pattern in openings of the underlying dielectric layer. Thus, the conductive vias may interconnect and electrically connect various wires.

In fig. 11, an Under Bump Metallization (UBM)140 and a conductive connector 142 are formed for external connection to the second interconnect structure 136, in accordance with some embodiments. In an example of forming UBM140, dielectric layer 138 is first patterned to form an opening that exposes a portion of metallization pattern 134. Patterning may be performed by an acceptable process, such as by exposing the dielectric layer 138 to light when the dielectric layer 138 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 138 is a photosensitive material, the dielectric layer 138 may be developed after exposure.

UBM140 has a bump portion located on and extending along a major surface of dielectric layer 138, and also has a via portion extending through dielectric layer 138 to physically and electrically connect metallization pattern 134. As a result, UBM140 is electrically connected to metallization pattern 134. UBM140 may be formed from the same material as metallization pattern 134 and may be formed using a similar process (e.g., plating). In some embodiments, UBM140 has a different dimension (e.g., width, thickness, etc.) than metallization pattern 134.

According to some embodiments, conductive connector 142 is then formed on UBM 140. The conductive connectors 142 may be, for example, Ball Grid Array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. The conductive connectors 142 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connectors 142 are formed by first forming a solder layer by evaporation, plating, printing, solder transfer, solder ball placement, or the like. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connectors 142 include metal posts (e.g., copper posts) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connectors 142 may be larger than the solder regions 72 (e.g., have a larger pitch than the solder regions 72). Thus, interposer structure 200 is formed that combines interconnect device 50 and passive device 52. In some embodiments, the entire interposer structure 200 may be free of active devices.

Fig. 12A-14B illustrate intermediate steps in bonding the interposer structure 200 to the central substrate 152 and the device die to the interposer structure 200. Thus, the semiconductor package 250 is formed.

In fig. 12A and 12B, carrier substrate lift-off is performed to separate (or "lift-off") the carrier substrate 100 from the interposer structure 200. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto the peeling layer 102 such that the peeling layer 102 decomposes under the heat of the light and the carrier substrate 100 may be removed.

The structure is then flipped over and bonded to the central substrate 152. The central substrate 152 may be a metal clad insulating base material such as a copper clad epoxy impregnated glass cloth laminate, a copper clad polyimide impregnated glass cloth laminate, or the like. For example, the central substrate 152 may include metal cladding layers 146 and 148 on opposite sides of the base material 144. Metal cladding layers 146 and 148 may be patterned to provide electrical routing on the top and bottom surfaces of base material 144. Patterning the metal cladding layers 146 and 148 may be performed using any suitable process, such as wet etching, laser etching, and the like. The conductive connectors 142 may be bonded directly to the metal cladding 146 using, for example, a flip-chip bonding process. In some embodiments, no intermediate layers (e.g., build-up layers) are formed between the metal cladding layer 146 of the center substrate 152 and the conductive connectors 142 of the interposer structure 200.

The center substrate 152 may further include a through via 150 extending through the base material 144. As an example to form the through via 150, forming an opening through the base material includes using a mechanical drilling or milling process. Next, the openings may be plated with a metallic material, for example, using an electrochemical plating process. In some embodiments, the metallic material may include copper. Plating of the openings may be formed through the vias 150 for providing electrical connections from one side of the central substrate 152 to the other. After plating, the remaining portion of the opening through the base material may optionally be filled with an insulating material.

The flipped plug structure 200 exposes the seed layer 104. Fig. 12A shows an embodiment in which dielectric layer 106 and pre-solder region 110 are incorporated into an interposer structure 200. Fig. 12B shows an alternative embodiment in which the dielectric layer 106 and the pre-solder region 110 are omitted so that the seed layer 104 contacts the dielectric layer 112 and the metallization pattern 114.

In fig. 13A and 13B, the seed layer 104 and the dielectric layer 106 (if present) are removed using a suitable process, such as a plasma etch process, a wet etch process, and the like. In fig. 13A, which corresponds to the embodiment of fig. 12A, dielectric layer 106 is removed to expose pre-solder region 110. In this embodiment, removing the dielectric layer 106 may use an etching process that selectively etches the dielectric layer 106 at a faster rate than the pre-solder region 110. In fig. 13B, which corresponds to the embodiment of fig. 12B, the seed layer 104 is removed to expose the metallization pattern 114.

In fig. 14A and 14B, device dies 54A and 54B are bonded to metallization pattern 114 by conductive connectors 99. For example, the conductive connectors 99 may include solder regions that are bonded to the metallization patterns 114 using a flip-chip bonding process. A reflow process may be applied to adhere the solder regions of the conductive connectors 99 to the metallization pattern 114. In some embodiments, the conductive connectors 99 may be the same size as the solder regions 72 (e.g., have the same pitch as the solder regions 72). In some embodiments, the conductive connectors 99 may be smaller than the conductive connectors 142 (e.g., have a smaller pitch than the conductive connectors 142). Fig. 14A shows an embodiment in which the electrically conductive connectors 71 of the interconnect device 50 comprise only solder regions 72. Fig. 14B illustrates an alternative embodiment in which the conductive connector 71 of the interconnect device includes a solder region 72 disposed on the conductive post 70.

Device dies 54A and 54B may be similar to interconnect device 50. For example, fig. 15 shows a detailed view of device die 54 (e.g., device dies 54A and 54B). Device die 54 may include a substrate 82 (e.g., similar to substrate 60), an interconnect structure 90 (e.g., similar to interconnect structure 62) formed on substrate 82, a pad 92 (e.g., similar to pad 68), a passivation layer 94 (e.g., similar to passivation layer 66), and a conductive connector 99 (e.g., similar to conductive connector 71). Unlike interconnect device 50, however, device die 54 includes active devices 84 (e.g., transistors) on the top surface of substrate 82. Active device 84 is formed in dielectric layer 86, and active device 84 is electrically connected to electrical wiring 91 through conductive via 88. Electrical wiring 91 in interconnect structure 90 may provide a circuit structure. For example, the device die 54 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), an Application Processor (AP), a microcontroller, etc.), a memory die (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), a power management die (e.g., a Power Management Integrated Circuit (PMIC) die), a Radio Frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., a Digital Signal Processing (DSP) die), a front end die (e.g., an Analog Front End (AFE) die), etc.), a multifunction die, or a combination thereof.

Referring back to fig. 14A, logic die 54A and memory die 54B are flip chips bonded to metallization pattern 114. Interconnect device 50 is electrically connected to both logic die 54A and memory die 54B, and interconnect device 50 provides fine-pitch electrical interconnection between logic die 54A and memory die 54B. In various embodiments, interconnect device 50 may allow for high speed routing between adjacent device dies 54 bonded to interposer structure 200. In addition, passive devices 52 are electrically coupled to logic die 54A and/or memory die 54B. By placing passive devices 52 within interposer structure 200, the distance between passive devices 52 and device die 54 may be reduced, thereby improving electrical performance in the finished package.

Although only one logic die 54A and one memory die 54B are shown in fig. 14A and 14B, any number of device dies 54 may be bonded to the metallization pattern 114. In addition, other types of device dies 54 may also be bonded to the metallization pattern 114. For example, fig. 16 shows a top view of die 54 bonded to interposer structure 200. The die 54 includes a logic die 54A, a memory die 54B, a multifunction die 54C, and the like. In further embodiments, other configurations are possible. One or more interconnect devices 50 may provide electrical interconnection between adjacent device dies 54 bonded to interposer structure 200.

Referring back to fig. 14A and 14B, underfill 156 may be deposited around the conductive connectors 99. Underfill 156 may be formed by a capillary flow process after device die 54 is connected, or may be formed by a suitable deposition method before device die 54 is connected. Underfill 156 may be disposed between device die 54 and interposer structure 200. Although fig. 14A and 14B show separate portions of underfill 156 under each device die 54, in further embodiments, underfill 156 may extend continuously under multiple device dies 54.

As also shown in fig. 14A and 14B, a conductive connector 154 is formed on the metal cladding 148 of the center substrate 152. Conductive connectors 154 may be used to bond the completed package 250 to another structure, such as a package substrate, motherboard, or the like. The conductive connectors 154 may be, for example, BGA connectors, solder balls, metal posts, C4 bumps, micro bumps, ENEPIG formed bumps, or the like. The conductive connectors 154 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connectors 154 are formed by first forming a solder layer by evaporation, plating, printing, solder transfer, solder ball placement, or the like. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connectors 154 include metal posts (e.g., copper posts) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by a plating process. In some embodiments, the conductive connectors 154 may be larger than the conductive connectors 142 (e.g., have a larger pitch than the conductive connectors 142). Thus, the package 250 may be formed according to various embodiments.

Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate that allow testing of the 3D package or the 3DIC using a probe and/or a probe card, etc. Verification tests may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

Package 250 allows for the bonding of interconnect device 50 to provide improved high speed transmission of electrical signals between components (e.g., device die 54) bonded to the interposer structure. The incorporation of interconnect device 50 may improve the high speed operation of package 250. By bonding the device die directly to the interposer structure, yield loss of separately packaged expensive device die may be reduced. Additionally, by integrating passive devices within the package structure, power/insertion loss may be reduced, and/or circuit speed may be increased, thereby improving the performance of the package. Gain may also be achieved by placing the passive device die closer to the device die.

According to some embodiments, a package comprises: there is no plug-in structure for any active devices. The plug-in structure includes: an interconnect device; a dielectric film surrounding the interconnect device; and a first metallization pattern bonded to the interconnect device. The package further includes: a first device die bonded to a side of the first metallization pattern opposite the interconnect device; and a second device die bonded to the same side of the first metallization pattern as the first device die. An interconnect device electrically connects the first device die to the second device die. In some embodiments, the insert structure further comprises: a passive device bonded to the same side of the first metallization pattern as the interconnect device, wherein the passive device is electrically connected to the first device die or the second device die. In some embodiments, the interconnect device is a flip chip bonded to the first metallization pattern. In some embodiments, an interconnect device comprises: a semiconductor substrate; and a first interconnect structure on the semiconductor substrate, wherein the first interconnect structure includes electrical routing of circuitry routing signals between the first device die and the second device die. In some embodiments, the pitch of the electrical wiring is in the range of 0.1 μm to 5 μm. In some embodiments, the insert structure further comprises: a second interconnect structure on a side of the dielectric film opposite the first metallization pattern; and a through via extending through the dielectric film, wherein the through via electrically connects the second interconnect structure to the first metallization pattern. In some embodiments, the first device die and the second device die are each directly bonded to the first metallization pattern.

According to some embodiments, a package comprises: a plug-in without an active device; the plug-in includes: an interconnect device, the interconnect device comprising: a semiconductor substrate; and a first interconnect structure on the semiconductor substrate; a passive device; dielectric films, buried interconnect devices and passive devices; and a first metallization pattern over the dielectric film, the interconnect device, and the passive device, wherein the interconnect device is bonded to the first surface of the first metallization pattern by a first solder region, and the passive device is bonded to the first surface of the first metallization pattern by a second solder region; a first device die directly bonded to a second surface of the first metallization pattern through a third solder region, wherein a first surface of the first metallization pattern is opposite the second surface of the first metallization pattern; a second device die directly bonded to the second surface of the first metallization pattern through a fourth solder region, wherein electrical routing in the first interconnect structure routes signals between the first device die and the second device die; and a central substrate directly bonded to a side of the interposer opposite the first device die and the second device die. In some embodiments, the passive device is electrically connected to the first device die or the second device die. In some embodiments, the insert further comprises: a second interconnect structure on a side of the dielectric film opposite the first metallization pattern; a first via extending through the dielectric film, wherein the first via electrically connects the second interconnect structure to the first metallization pattern; and a fifth solder region on a side of the second interconnect structure opposite the first through via. In some embodiments, the central substrate comprises: an insulating core material; a first metal cladding layer on a first side of the insulating core material; a second metal cladding layer on a second side of the insulating core material opposite the first side of the insulating core material; a second through via extending through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer. In some embodiments, the fifth solder region of the interposer is directly bonded to the first metal cladding layer. In some embodiments, the package further comprises: and the sixth solder region is directly contacted with the second metal cladding layer. In some embodiments, the insert further comprises: a first underfill surrounding the first solder region; and a second underfill surrounding the second solder region. In some embodiments, the first underfill is physically separated from the second underfill. In some embodiments, the package further comprises: a third underfill surrounding the third solder region; and a fourth underfill surrounding the fourth solder region.

According to some embodiments, a method comprises: bonding an interconnect device to the first surface of the first metallization pattern, the interconnect device being devoid of any active devices; bonding a passive device to the first surface of the first metallization pattern, the passive device being devoid of any active device; burying the interconnect device and the passive device in a dielectric film; bonding a first device die to a second surface of the first metallization pattern, the second surface being opposite the first surface; a second device die is bonded to the second surface of the first metallization pattern, wherein the interconnect device is to route signals between the first device die and the second device die. In some embodiments, the method further comprises: forming through vias on the first metallization pattern; burying a through via in the dielectric film; an interconnect structure over the dielectric film is formed, wherein the first metallization pattern is electrically connected to the interconnect structure through the via. In some embodiments, the method further comprises: a center substrate is bonded to a side of the interconnect structure opposite the dielectric film. In some embodiments, the central substrate comprises: an insulating core material; a first metal cladding layer on a first side of the insulating core material, wherein the interconnect structure is directly bonded to the first metal cladding layer; a second metal cladding layer on a second side of the insulating core material opposite the first side of the insulating core material; a second through via extending through the insulating core material, wherein the second through via electrically connects the first metal cladding layer to the second metal cladding layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.