GaN HEMT integrated device and preparation method thereof

文档序号：618188 发布日期：2021-05-07 浏览：240次中文

阅读说明：本技术 GaN HEMT集成器件及其制备方法 (GaN HEMT integrated device and preparation method thereof ) 是由许明伟李海滨樊晓兵于 2020-12-31 设计创作，主要内容包括：本申请实施例公开了一种GaNHEMT集成器件及其制备方法,该方法包括：在衬底上制备缓冲层,并在缓冲层上外延形成第一外延层和第二外延层；在第二外延层的上表面沉积第一介质层和盖帽层,该盖帽层用于制备所述GaNHEMT器件的参考栅极；在参考栅极的外侧形成栅极外墙,并根据参考栅极和栅极外墙为掩膜外延形成重掺杂的第三外延层；将参考栅极制备为栅极以及制备源漏极。可见,本申请实施例,有利于制备低成本高产量的GaN射频HEMT集成器件,缩小集成器件尺寸,实现全自对准和小尺寸结构的栅极工艺集成方法,减小源漏极到栅极的寄生电阻,提升GaN HEMT集成器件在射频和毫米波应用中的性能。(The embodiment of the application discloses a GaNHEMT integrated device and a preparation method thereof, wherein the method comprises the following steps: preparing a buffer layer on a substrate, and epitaxially forming a first epitaxial layer and a second epitaxial layer on the buffer layer; depositing a first dielectric layer and a cap layer on the upper surface of the second epitaxial layer, wherein the cap layer is used for preparing a reference gate of the GaNHEMT device; forming a grid outer wall on the outer side of the reference grid, and forming a heavily doped third epitaxial layer by epitaxy according to the reference grid and the grid outer wall as masks; and preparing a reference grid as a grid and preparing a source drain. Therefore, the embodiment of the application is beneficial to preparing the GaN radio frequency HEMT integrated device with low cost and high yield, reducing the size of the integrated device, realizing the grid electrode process integration method of a full self-alignment and small-size structure, reducing the parasitic resistance from a source electrode to a drain electrode, and improving the performance of the GaN radio frequency HEMT integrated device in radio frequency and millimeter wave application.)

1. A method for preparing a GaN HEMT integrated device of a gallium nitride high electron mobility transistor is characterized by comprising the following steps:

preparing a buffer layer on a substrate, and epitaxially forming a first epitaxial layer and a second epitaxial layer on the buffer layer, wherein the forbidden band of the second epitaxial layer is wider than the forbidden band of the first epitaxial layer, a two-dimensional electron gas conducting channel is formed between the first epitaxial layer and the second epitaxial layer, and the buffer layer, the first epitaxial layer and the second epitaxial layer are sequentially arranged on the upper surface of the substrate from bottom to top;

depositing a first dielectric layer and a cap layer on the upper surface of the second epitaxial layer, wherein the cap layer is used for preparing the reference grid of the GaN HEMT device, the cap layer comprises a first thin layer and a second dielectric layer, the first thin layer and the second dielectric layer are sequentially arranged on the upper surface of the second epitaxial layer from bottom to top, and the first thin layer comprises at least one of the following layers: a polysilicon layer, an amorphous silicon layer, a silicon dioxide layer, a silicon nitride layer and a silicon oxynitride layer;

forming a grid outer wall on the outer side of the reference grid, and forming a heavily doped third epitaxial layer by epitaxy according to the reference grid and the grid outer wall as masks, wherein the grid outer wall is used for protecting the reference grid, the grid outer wall is arranged on the upper surface of the first medium layer, the third epitaxial layer is used for forming a low-resistance source-drain contact region so as to reduce parasitic resistance of a source-drain electrode, and the source-drain contact region is positioned on two sides of the reference grid;

preparing the reference grid electrode into a grid electrode and preparing a source drain electrode in the source drain contact area; the grid electrode and the first medium layer form a metal-insulator-semiconductor structure or the grid electrode and the second epitaxial layer form Schottky contact, and the source electrode and the drain electrode form ohmic contact with the third epitaxial layer.

2. The fabrication method according to claim 1, wherein the capping layer fabricating the reference gate comprises the operations of:

obtaining a first mask layer on the second dielectric layer by using a photoetching process;

and etching the second dielectric layer and the first thin film layer by taking the first mask layer as a mask, and stopping on the upper surface of the first dielectric layer to form the reference grid, wherein the reference grid is positioned on the upper surface of the first dielectric layer.

3. The method according to claim 1, wherein the forming of the gate outer wall outside the reference gate comprises:

depositing a third dielectric layer on the upper surface and the outer side of the reference grid and the upper surface of the first dielectric layer;

etching the third dielectric layer, and stopping at the second dielectric layer and the first dielectric layer to form the gate outer wall;

etching the first dielectric layer of the source-drain contact region to reserve the first dielectric layer on the lower surface of the reference gate and the lower surface of the gate outer wall and stop on the upper surface of the second epitaxial layer;

and epitaxially forming the third epitaxial layer by taking the reference grid and the outer wall of the grid as masks.

4. The method of claim 1, wherein the epitaxially forming a heavily doped third epitaxial layer for the mask according to the reference gate and the outer wall of the gate comprises:

extending the upper surface of the second epitaxial layer to form a third epitaxial layer according to the reference gate and the gate outer wall as masks to form the source-drain contact region; alternatively, the first and second electrodes may be,

etching the second epitaxial layer back by taking the reference gate and the outer wall of the gate as masks; extending the upper surface of the second epitaxial layer after back etching to form the third epitaxial layer and the source-drain contact region; the thickness of the second epitaxial layer positioned in the source-drain contact region is thinner than that of the second epitaxial layer positioned in the gate groove region; alternatively, the first and second electrodes may be,

back-etching the second epitaxial layer by taking the reference gate and the outer wall of the gate as masks to penetrate through the second epitaxial layer and stop at the first epitaxial layer; and epitaxially forming the third epitaxial layer on the upper surface of the first epitaxial layer to form the source/drain contact region.

5. The manufacturing method according to claim 1, wherein the manufacturing of the reference gate as a gate and the source and drain electrodes in the source and drain contact region comprises:

depositing a fourth dielectric layer on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall;

obtaining a second mask layer on the fourth dielectric layer by using a photoetching process;

etching the fourth dielectric layer and the second dielectric layer in the reference grid by taking the second mask layer as a mask to expose the first thin film layer in the reference grid;

etching the first thin film layer by taking the second mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the second mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form the gate trench;

depositing a grid metal layer on the upper surfaces of the grid groove and the fourth dielectric layer to prepare the grid; the transverse part of the grid electrode is arranged on the upper surface of the fourth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer;

depositing a fifth dielectric layer on the transverse part of the grid and the upper surface of the fourth dielectric layer, wherein the fourth dielectric layer and the fifth dielectric layer are sixth dielectric layers;

etching the sixth dielectric layer to form a source drain groove, and depositing a source drain metal layer on the upper surfaces of the source drain groove and the sixth dielectric layer to prepare a source drain; the transverse part of the source and drain electrode is transversely arranged on the upper surface of the sixth dielectric layer, the longitudinal part of the source and drain electrode penetrates through the sixth dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer.

6. The manufacturing method according to claim 1, wherein the manufacturing of the reference gate as a gate and the source and drain electrodes in the source and drain contact region comprises:

depositing a seventh dielectric layer on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall;

etching the seventh dielectric layer to form a source drain groove, and depositing a source drain metal layer on the upper surfaces of the source drain groove and the seventh dielectric layer to prepare a source drain; the transverse part of the source and drain electrode is transversely arranged on the upper surface of the seventh dielectric layer, the longitudinal part of the source and drain electrode penetrates through the seventh dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer;

forming an eighth dielectric layer, wherein the eighth dielectric layer covers the source and drain electrodes and the upper surface of the seventh dielectric layer, and the seventh dielectric layer and the eighth dielectric layer are ninth dielectric layers;

obtaining a third mask layer on the ninth dielectric layer by using a photoetching process;

etching the ninth dielectric layer and the second dielectric layer in the reference grid by taking the third mask layer as a mask to expose the first thin film layer in the reference grid;

etching the first thin film layer by taking the third mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the third mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form the gate trench;

forming a grid metal layer to prepare a grid, wherein the grid metal layer covers the grid groove and the upper surface of the ninth dielectric layer; the transverse part of the grid electrode is arranged on the upper surface of the ninth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer.

7. The production method according to any one of claims 1 to 6, wherein the substrate is a single crystal structure composed of one material of silicon Si, gallium nitride GaN, silicon carbide SiC, sapphire, or diamond; and/or the presence of a gas in the gas,

the buffer layer is of a single-layer or multi-layer structure formed by at least one material of AlN, GaN and AlGaN, and the thickness of the buffer layer is 0.5-4 um; and/or the presence of a gas in the gas,

the first epitaxial layer is of a single-layer structure formed by GaN materials or a multi-layer structure formed by AlGaN, indium gallium nitride (InGaN) and GaN materials, the second epitaxial layer is of a single-layer or multi-layer structure formed by at least one of AlGaN, indium gallium nitride (InGaN), indium aluminum nitride (InAlN), AlN and indium aluminum nitride (InAlGaN), the thickness of the first epitaxial layer is 10-500nm, and the thickness of the second epitaxial layer is 5-30 nm; and/or the presence of a gas in the gas,

the first dielectric layer is silicon oxide SiO₂Silicon nitride SiN_xAlumina, aluminaAl₂O₃AlN, AlON, SiO_xN_yHafnium oxide HfO₂Ga (i) gallium oxide₂O₃The thickness of the first dielectric layer is 5-30 nm; and/or the presence of a gas in the gas,

the thickness of the first thin film layer is 100-300 nm; and/or the presence of a gas in the gas,

the second dielectric layer is SiO₂、SiN_x、SiO_xN_yOr Al₂O₃The thickness of the second dielectric layer is 20-100 nm; and/or the presence of a gas in the gas,

the third epitaxial layer is of a single-layer structure formed by one of n-type GaN, AlGaN or InGaN, and the thickness of the third epitaxial layer is 10-50 nm.

8. A gallium nitride high electron mobility transistor (GaN HEMT) integrated device, comprising: the device comprises a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, a first dielectric layer, a grid outer wall, a heavily doped third epitaxial layer, a grid and a source drain; wherein the content of the first and second substances,

the forbidden band of the second epitaxial layer is wider than the forbidden band of the first epitaxial layer, a two-dimensional electron gas conducting channel is formed between the first epitaxial layer and the second epitaxial layer, and the buffer layer, the first epitaxial layer and the second epitaxial layer are sequentially arranged on the upper surface of the substrate from bottom to top;

the upper surface of the second epitaxial layer is sequentially overlapped with the first dielectric layer and the cap layer, the cap layer is used for preparing a reference grid of the GaNHEMT device, the cap layer comprises a first thin layer and a second dielectric layer, the first thin layer and the second dielectric layer are sequentially arranged on the upper surface of the first dielectric layer from bottom to top, and the first thin layer comprises at least one of the following components: a polysilicon layer, an amorphous silicon layer, SiO2, SiNx, SiON, or the like;

the grid outer wall is positioned on the outer side of the reference grid and is arranged on the upper surface of the first dielectric layer, and the grid outer wall is used for protecting the reference grid;

the third epitaxial layer is formed by taking the reference grid and the outer wall of the grid as masks in an epitaxial mode, the third epitaxial layer is used for forming a low-resistance source-drain contact area so as to reduce the contact resistance of the source-drain electrode, and the source-drain contact area is located on two sides of the reference grid;

the grid electrode is formed by the reference grid electrode, the source and drain electrodes are formed by the source and drain contact region, the grid electrode and the first dielectric layer form a metal-insulator-semiconductor structure or the grid electrode and the second epitaxial layer form Schottky contact, and the source and drain electrodes and the third epitaxial layer form ohmic contact.

9. The GaN HEMT integrated device of claim 8, further comprising a third dielectric layer; wherein the content of the first and second substances,

the third dielectric layer is used for forming the grid outer wall and covers the upper surface of the first dielectric layer and the upper surface and the outer side of the reference grid; the gate outer wall is formed by the following operations: and etching the third dielectric layer, and stopping at the second dielectric layer and the first dielectric layer to form the outer wall of the grid electrode.

10. The GaN HEMT integrated device of claim 8, wherein said third epitaxial layer is formed by:

etching the second epitaxial layer back by taking the reference gate and the outer wall of the gate as masks; extending the upper surface of the second epitaxial layer after back etching to form a third epitaxial layer so as to form a source-drain contact region; the thickness of the second epitaxial layer positioned in the source drain groove region is thinner than that of the second epitaxial layer positioned in the gate groove region; alternatively, the first and second electrodes may be,

11. The GaN HEMT integrated device of claim 8, further comprising a sixth dielectric layer, said sixth dielectric layer comprising a fourth dielectric layer and a fifth dielectric layer; wherein the content of the first and second substances,

the fourth dielectric layer is arranged on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall;

the gate is prepared by: obtaining a second mask layer on the fourth dielectric layer by using a photoetching process; etching the fourth dielectric layer and the second dielectric layer in the reference grid by taking the second mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the second mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the second mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form the gate trench; depositing a grid metal layer on the upper surfaces of the grid groove and the fourth dielectric layer to prepare the grid; the transverse part of the grid electrode is arranged on the upper surface of the fourth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer;

the fifth dielectric layer covers the transverse part of the grid and the upper surface of the fourth dielectric layer;

the source and drain electrodes are prepared by etching the sixth dielectric layer to form a source and drain groove and depositing a source and drain electrode metal layer on the upper surfaces of the source and drain groove and the sixth dielectric layer; the transverse part of the source and the drain is transversely arranged on the upper surface of the sixth dielectric layer, the longitudinal part of the source and the drain penetrates through the sixth dielectric layer, and the lower surface of the longitudinal part of the source and the drain is in contact with the third epitaxial layer.

12. The GaN HEMT integrated device of claim 8, further comprising a ninth dielectric layer, said ninth dielectric layer comprising a seventh dielectric layer and an eighth dielectric layer; wherein the content of the first and second substances,

the seventh dielectric layer covers the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall;

the source and drain electrodes are prepared by etching the seventh dielectric layer to form a source and drain groove and depositing a source and drain electrode metal layer on the upper surfaces of the source and drain groove and the seventh dielectric layer; the transverse part of the source and drain electrode is transversely arranged on the upper surface of the seventh dielectric layer, the longitudinal part of the source and drain electrode penetrates through the seventh dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer;

the eighth dielectric layer covers the upper surfaces of the source and drain electrodes and the seventh dielectric layer;

the gate is prepared by: obtaining a third mask layer on the ninth dielectric layer by using a photoetching process; etching the ninth dielectric layer and the second dielectric layer in the reference grid by taking the third mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the first mask layer as a mask, and stopping on the upper surface of the first dielectric layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the third mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form the gate trench; forming a grid metal layer to prepare the grid, wherein the grid metal layer covers the grid groove and the upper surface of the ninth dielectric layer; the transverse part of the grid electrode is arranged on the upper surface of the ninth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer.

13. The GaN HEMT integrated device of any one of claims 8-12, wherein said substrate is a single crystal structure of one of Si, GaN, SiC, sapphire or diamond; and/or the presence of a gas in the gas,

the first epitaxial layer is of a single-layer structure formed by GaN materials or a multi-layer structure formed by AlGaN, InGaN and GaN materials, the second epitaxial layer is of a single-layer or multi-layer structure formed by at least one of AlGaN, InGaN, InAlN and InAlGaN, the thickness of the first epitaxial layer is 10-500nm, and the thickness of the second epitaxial layer is 5-30 nm; and/or the presence of a gas in the gas,

the first dielectric layer is SiO₂、SiN_x、Al₂O₃、AlN、AlON、SiO_xN_y、HfO₂、Ga₂O₃The thickness of the first dielectric layer is 5-30 nm; and/or the presence of a gas in the gas,

the thickness of the first thin film layer is 100-300 nm; and/or the presence of a gas in the gas,

the second dielectric layer is SiO₂、SiN_x、SiO_xN_yOr Al₂O₃The thickness of the second dielectric layer is 20-100 nm; and/or the presence of a gas in the gas,

the third epitaxial layer is of a single-layer structure formed by one of n-type GaN, AlGaN or InGaN, and the thickness of the third epitaxial layer is 10-50 nm.

Technical Field

The application relates to the technical field of semiconductor device processes, in particular to a GaN HEMT integrated device and a preparation method thereof.

Background

Gallium nitride (GaN) -based semiconductor materials are third generation semiconductor materials following silicon (Si) and gallium arsenide (GaAs). The high-mobility electron gun has the characteristics of large forbidden band width, strong breakdown electric field, high electron mobility, high electron saturation rate and the like. It has particular advantages in semiconductor light emitting devices, detectors, photovoltaic devices, and electronic devices such as High Electron Mobility Transistors (HEMTs).

The GaN-based HEMT integrated device has the advantages of high working temperature, strong radiation resistance, low loss, high digital-to-analog conversion efficiency and the like, but also has the problems of preparation cost, device size, parasitic resistance and the like, thereby influencing the application of the GaN-based HEMT integrated device in radio frequency and millimeter wave.

Disclosure of Invention

The embodiment of the application provides a gallium nitride high electron mobility transistor integrated device and a preparation method thereof, and aims to prepare a GaN radio frequency HEMT integrated device with low cost and high yield, reduce the size of the integrated device, realize a grid electrode process integration method of a full-self-alignment and small-size structure, reduce parasitic resistance from a source electrode to a grid electrode, and improve the performance of the GaN HEMT integrated device in radio frequency and millimeter wave application.

In a first aspect, an embodiment of the present application provides a method for manufacturing an integrated device of a gallium nitride high electron mobility transistor, including:

forming a grid outer wall on the outer side of the reference grid, and forming a heavily doped third epitaxial layer by epitaxy according to the reference grid and the grid outer wall as masks, wherein the grid outer wall is used for protecting the reference grid, the grid outer wall is arranged on the upper surface of the first medium layer, the third epitaxial layer is used for forming a low-resistance source-drain contact region so as to reduce the contact resistance of a source-drain electrode, and the source-drain contact region is positioned on two sides of the reference grid;

In a second aspect, an embodiment of the present application provides a gallium nitride high electron mobility transistor integrated device, including: the device comprises a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, a first dielectric layer, a grid outer wall, a heavily doped third epitaxial layer, a grid and a source drain; wherein the content of the first and second substances,

It can be seen that, in the embodiment of the present application, firstly, by adopting a method compatible with a CMOS process, it is beneficial to implement the fabrication of a low-cost high-yield GaN radio frequency HEMT integrated device and to reduce the size of the integrated device. And secondly, a reference grid of polysilicon, amorphous silicon, silicon dioxide, silicon nitride or silicon oxynitride material is adopted, so that the grid process integration method of full self-alignment and small-size structure is facilitated. Then, through photoetching and a fully self-aligned grid electrode small-size structure, the size from a source electrode, a drain electrode to a grid electrode and parasitic resistance are reduced, and the performance of the GaN HEMT integrated device in radio frequency and millimeter wave application is improved. And finally, the parasitic resistance and the contact resistance of the source and the drain are further reduced through a third epitaxial layer which is completely compatible with the secondary epitaxial growth of the CMOS process.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings described below are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic flow chart illustrating a method for fabricating a gan hemt device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an epitaxial structure of a gan hemt device according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a device after photolithography and etching of a cap layer according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating a device structure after a third dielectric layer is deposited according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a device after etching a third dielectric layer according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a device after etching a first dielectric layer according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a device after a third dielectric layer is epitaxially formed according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another device after a third dielectric layer is epitaxially formed according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another device after a third dielectric layer is epitaxially formed according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram illustrating a device structure after depositing a fourth dielectric layer according to an embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of a device after etching a second dielectric layer in a reference gate according to an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of a device after etching a first thin film layer in a reference gate according to an embodiment of the present disclosure;

FIG. 13 is a schematic structural diagram of a device after etching a first thin film layer and a first dielectric layer in a reference gate according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a device structure after a gate metal layer is deposited according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a device after a gate is fabricated according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram illustrating a device structure after depositing a fifth dielectric layer according to an embodiment of the present disclosure;

fig. 17 is a schematic structural diagram of a device after source and drain are prepared according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of a device after source and drain are prepared according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of a device after source and drain are prepared according to an embodiment of the present application;

FIG. 20 is a schematic diagram illustrating a device structure after an eighth dielectric layer is deposited according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a device after etching a second dielectric layer according to an embodiment of the present disclosure;

FIG. 22 is a schematic diagram of a device structure after etching a first thin film layer according to an embodiment of the present disclosure;

fig. 23 is a schematic structural diagram of a device after a gate is fabricated according to an embodiment of the present disclosure;

fig. 24 is a schematic structural diagram of a gan hemt device according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of yet another gan hemt device according to embodiments of the present application;

fig. 26 is a schematic structural diagram of yet another gan hemt device according to embodiments of the present application;

fig. 27 is a schematic structural diagram of yet another gan hemt device according to embodiments of the present application;

fig. 28 is a schematic structural diagram of another gan hemt device according to embodiments of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In the drawings provided by the embodiments of the present invention, the cross-sectional view of the device structure shown in the drawings is not partially enlarged in a general scale, and the schematic drawings are only illustrative and should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Fig. 1 is a schematic flow chart illustrating a method for fabricating a gan hemt device according to an embodiment of the present invention, the method comprising:

s110, preparing a buffer layer on the substrate, and forming a first epitaxial layer and a second epitaxial layer on the buffer layer in an epitaxial mode.

Specifically, the first epitaxial layer and the second epitaxial layer can be used as a heterojunction structure which is modulated and doped by a GaN-based material, and the heterojunction structure can obtain higher electron mobility, higher peak electron velocity and saturated electron velocity and higher two-dimensional electron gas density at room temperature. The GaN-based material may be GaN, InN, AlN and multi-component alloy materials (such as InGaN, AlGaN, AlInN, InAlGaN) composed of them.

It should be noted that in the embodiment of the present application, a thickness of the buffer layer meeting a preset requirement may be grown at a low temperature or a high temperature, and then, after an annealing process and the like, a first epitaxial layer and a second epitaxial layer are epitaxially formed on the buffer layer. The thickness of the buffer layer has an important influence on the electrical properties and surface topography of the epitaxial layer. Furthermore, the method is simple. In the embodiments of the present disclosure, the first epitaxial layer and the second epitaxial layer may be deposited by metal-organic chemical vapor deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Hydride Vapor Phase Epitaxy (HVPE), Pulsed Laser Deposition (PLD), or reactive sputtering. The method comprises the steps of filling materials such as an aluminum source, an indium source, a gallium source and a nitrogen source into a reaction chamber, and growing the first epitaxial layer and the second epitaxial layer which meet preset requirements by controlling the temperature of the reaction chamber to be 800-1200 ℃ and controlling the reaction rate to be less than 30 nm/min.

Specifically, the substrate may be a single crystal structure made of one material of Si, GaN, SiC, sapphire, or diamond.

Specifically, the buffer layer may have a single-layer or multi-layer structure made of at least one material of AlN, GaN, and AlGaN. Wherein, the thickness of buffer layer is 0.5-4 um. It should be noted that, because the substrate and the first epitaxial layer are made of different materials, the substrate and the first epitaxial layer have a difference in physical and chemical properties, and therefore, the lattice mismatch between the substrate and the epitaxial thin film can be effectively reduced through the buffer layer, the problems of cracks and the like in the growth process can be solved, and the quality of the thin film can be improved. For example, since AlN material is chemically stable with a thermal expansion coefficient between that of Si material and GaN material, when the substrate is Si material and the first buffer layer contains GaN material, in the case of growing the first epitaxial layer on Si, the problem of cracks occurring during growth is solved by introducing the AlN buffer layer. Meanwhile, the first epitaxial layer without cracks can be grown by adding a certain number of buffer layers in the growth process. Therefore, cracks can also be eliminated by introducing an AlN buffer layer at high and low temperatures and AlGaN of different compositions.

Specifically, the first epitaxial layer may be a single-layer structure made of a GaN material. Alternatively, the first epitaxial layer may be a multilayer structure composed of at least two materials of AlGaN, InGaN, or GaN. Wherein the thickness of the first epitaxial layer is 10-500 nm. It should be noted that, in the embodiments of the present application, the preparation process and the requirements of the gan hemt device need to be specifically considered, and the material for epitaxially growing the first epitaxial layer needs to be reasonably selected. In addition, when the first epitaxial layer is a single-layer structure, the first epitaxial layer may be a channel layer in a heterojunction structure; when the first epitaxial layer is a multilayer structure, the first epitaxial layer may include a back barrier layer and a channel layer in a heterostructure. The AlGaN material is used as a back barrier layer with low Al component, so that the potential barrier on one side of the buffer layer can be improved, and the quantum limit of electron gas in a channel well is enhanced, thereby improving the output performance and pinch-off characteristic of the GaN HEMT device and reducing the leakage of the buffer layer.

Specifically, the second epitaxial layer may be a single layer or a multilayer structure made of at least one material of AlGaN, InGaN, InAlN, AlN, or InAlGaN. Wherein the thickness of the second epitaxial layer is 5-30 nm. It should be noted that, in the embodiments of the present application, the preparation process and the requirements of the gan hemt device need to be specifically considered, and the material for epitaxially growing the second epitaxial layer needs to be reasonably selected. The second epitaxial layer may be a barrier layer in a heterojunction structure, for example, the second epitaxial layer may be a single barrier layer made of a material such as AlGaN, InAlN, or InAlGaN, or may be a composite barrier layer made of a material such as AlInN/AlGaN, InAlGaN/InGaN, or InAlGaN.

Therefore, different heterojunction structures of the GaN-based HEMT device are formed by adopting different semiconductor process flows, different materials of the first epitaxial layer and the second epitaxial layer and different film level structures, different two-dimensional electron gas densities are generated, different working frequencies, different saturated leakage currents and different radiation resistance capabilities are achieved, and the preparation requirements of high-frequency high-power electronic devices and high-speed low-consumption electronic devices are met.

For example, first, a silicon substrate is placed in a reaction chamber of an MOCVD apparatus, and the degree of vacuum of the reaction chamber is evacuated to 1X 10^-2Performing high-temperature heat treatment on the silicon substrate under the protection of hydrogen at the heating temperature of 1000-1200 ℃, the heating time of 4-6min and the pressure of the reaction chamber of 35-45 torr, and introducing the hydrogen flow of 100-1000 sccm; secondly, reducing the temperature of the silicon substrate to 600-800 ℃, keeping the growth pressure to 35-45 torr, controlling the flow of argon gas to 20-50sccm and the flow of ammonia gas to 40-500sccm, and introducing trimethylaluminum (TMAl) into the reaction chamber to grow the AlN buffer layer; thirdly, raising the temperature to 900-; then, introducing trimethyl gallium into the reaction chamber at the same time, maintaining the temperature at 900-; and finally, simultaneously introducing trimethyl aluminum, trimethyl gallium and/or trimethyl indium into the reaction chamber, maintaining the temperature at 900-1100 ℃, and controlling the flow rate to grow the AlInN/AlGaN composite barrier layer.

And S120, depositing a first dielectric layer and a cap layer on the upper surface of the second external delay, wherein the cap layer is used for preparing a reference grid of the GaN HEMT device.

The cap layer may include a first thin film layer and a second dielectric layer, the first thin film layer and the second dielectric layer are sequentially disposed on the upper surface of the second epitaxial layer from bottom to top, and the first thin film layer may include at least one of the following: polysilicon layer, amorphous silicon layer, SiO2 layer, SiNx layer, SiON layer.

It should be noted that in the embodiment of the present application, a reference gate made of polysilicon, amorphous silicon, SiO2, SiNx, or SiON material is used as a dummy gate (dummy gate) in advance, which is beneficial to implementing full self-aligned (FSA) gate process integration and ensuring a GaN HEMT device with an FSA architecture. In addition, the size from a source electrode, a drain electrode to a grid electrode and parasitic resistance can be further reduced by the FSA, and the small-size structure of the grid electrode in the FSA process also improves the device performance of the GaN HEMT device in radio frequency and millimeter wave applications.

Referring to fig. 2, the buffer layer, the first epitaxial layer, the second epitaxial layer, the first dielectric layer, the first thin film layer, and the second dielectric layer are sequentially disposed on the upper surface of the substrate. It should be noted that the thickness of each layer in the illustrated example is only illustrative and needs to be determined according to a specific semiconductor process, and does not constitute a limitation on the embodiment of the present application.

Specifically, the first dielectric layer may be SiO₂、SiN_x、Al₂O₃、AlN、AlON、SiO_xN_y、HfO₂And Ga₂O₃A single-layer or multi-layer (or composite) structure of at least one material of (a). Preferably, the first dielectric layer may be SiN_xA single layer structure of material. Preferably, the first dielectric layer may be SiO₂And SiN_xComposite or multilayer structures of materials. The thickness of the first dielectric layer can be 5-30 nm. It should be noted that the first dielectric layer may be regarded as a gate dielectric layer, and may be deposited by Atomic Layer Deposition (ALD), Plasma Enhanced Atomic Layer Deposition (PEALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), low pressure chemical vapor deposition (MOCVD), plasma oxidation, thermal oxidation, PLD, MOCVD, and other techniques. In addition, the first dielectric layer considered in the embodiment of the application adopts a material with a high dielectric constant. This is because, under the condition that the GaN HETM device ensures that the gate control capability is not changed, the transconductance (an index for indicating the gate control capability) is related to the unit gate capacitance, and the unit gate capacitance can be indicated by the ratio of the dielectric constant of the gate dielectric layer to the thickness of the gate dielectric layer, so that the higher the dielectric constant of the gate dielectric layer is, the larger the thickness thereof is in proportion, which is beneficial to further reducing the gate leakage current and improving the conduction current of the channel.

Specifically, the thickness of the first thin film layer is 100-300 nm.

Specifically, the second dielectric layer may be SiO₂、SiN_x、SiO_xN_yOr Al₂O₃A single-layer structure of one of the materials. Preferably, the second dielectric layer may be SiO₂A single layer structure of material. The thickness of the second dielectric layer can be 20-100 nm. It should be noted that the second dielectric layer can be used to protect the first thin film layer and can be deposited by ALD, PEALD, PECVD, LPCVD, plasma oxidation, thermal oxidation, PLD, MOCVD, and the like.

Further, the first dielectric layer may be SiN_xAnd SiO₂A multi-layer structure of two materials of (3), or Al₂O₃And SiO₂A multilayer structure of two materials.

Further, the thickness of the first dielectric layer may be 20nm, the thickness of the first thin film layer may be 200nm, and the length of the reference gate may be 150 nm.

In one possible example, the capping layer fabricating the reference gate may include the following operations: obtaining a first mask layer on the second dielectric layer by using a photoetching process; and etching the second dielectric layer and the first thin film layer by taking the first mask layer as a mask, and stopping on the upper surface of the first dielectric layer to form a reference grid, wherein the reference grid is positioned on the upper surface of the first dielectric layer. It should be noted that, in the embodiment of the present application, it may be considered that the second dielectric layer and/or the first thin film layer are etched by using a dry etching or wet etching technique, such as capacitive Coupled Plasma-reactive ion etching (CCP-RIE), Inductive Coupled Plasma-reactive ion etching (ICP-RIE), and the like.

As shown in fig. 3, a reference gate composed of a second dielectric layer and a first thin film layer is obtained by performing photolithography and etching on the cap layer, and the reference gate may be located at any position on the upper surface of the first dielectric layer, specifically determined by the process requirements and the pattern of the mask, which is not specifically limited in the embodiments of the present application.

And S130, forming a grid outer wall on the outer side of the reference grid, and forming a heavily doped third epitaxial layer by epitaxy by taking the reference grid and the grid outer wall as masks.

The grid outer wall is used for protecting the reference grid, the grid outer wall is arranged on the upper surface of the first medium layer, the third epitaxial layer is used for forming a low-resistance source-drain contact area so as to reduce the contact resistance of a source-drain electrode, and the source-drain contact area is located on two sides of the reference grid.

In one possible example, forming a gate outer wall outside the reference gate, and epitaxially forming a heavily doped third epitaxial layer for the mask according to the reference gate and the gate outer wall may include: depositing a third dielectric layer on the upper surface and the outer side of the reference grid and the upper surface of the first dielectric layer; etching the third dielectric layer, and stopping at the second dielectric layer and the first dielectric layer to form a grid outer wall; etching the first dielectric layer in the source-drain contact area to reserve the first dielectric layer on the lower surface of the reference grid and the lower surface of the grid outer wall and stop on the upper surface of the second epitaxial layer; and epitaxially forming a third epitaxial layer by taking the reference grid and the outer wall of the grid as a mask.

It should be noted that, when the material of the third dielectric layer is different from the material of the second dielectric layer and the material of the first dielectric layer, the third dielectric layer may be directly etched through a mask-free process to stop at the second dielectric layer and the first dielectric layer to form the gate outer wall. In addition, the third dielectric layer can be etched by a dry etching or wet etching technique such as CCP-RIE, ICP-RIE and the like.

Specifically, the third dielectric layer may be SiN_x、SiO_xN_y、Al₂O₃A single layer or a multi-layer structure of at least one material of (1). Wherein, the thickness of the third dielectric layer can be 100-200 nm. It should be noted that the third dielectric layer can be used for preparing the gate outer wall, and can be deposited by ALD, PEALD, PECVD, LPCVD, plasma oxidation, thermal oxidation, PLD, MOCVD, and other techniques.

Specifically, the third epitaxial layer may be one of n-type GaN, AlGaN, or InGaN. Wherein the thickness of the third epitaxial layer may be 10-50 nm. It should be noted that, in general, unintentionally doped GaN material is n-type, and in the embodiments of the present application, heavily doped n-type GaN can be prepared by selecting Si as a dopant. For example, MOCVD is used to prepare different SiH₄Heavily doped n-type GaN at flow, where SiH₄The flow rate can be 10-30cm³And/min. Preferably, SiH₄The flow rate can be 20cm³/min。

Further, the thickness of the third epitaxial layer may be 20 nm.

For example, as shown in FIG. 4, a third dielectric layer is deposited on the upper surface and outside of the reference gate and on the upper surface of the first dielectric layer.

And as shown in fig. 5, the third dielectric layer is etched to form the outer wall of the gate.

As shown in fig. 6, the first dielectric layer is etched to leave the first dielectric layer on the lower surface of the reference gate and the lower surface of the gate outer wall.

In one possible example, epitaxially forming the third epitaxial layer for the mask according to the reference gate and the gate outer wall may include: extending the upper surface of the second epitaxial layer to form a third epitaxial layer according to the reference grid and the grid outer wall as masks so as to form a source-drain contact region; or, etching back the second epitaxial layer by taking the reference gate and the outer wall of the gate as masks; extending the upper surface of the second epitaxial layer after back etching to form the third epitaxial layer and the source-drain contact region; the thickness of the second epitaxial layer positioned in the source-drain contact region is thinner than that of the second epitaxial layer positioned in the gate groove region; or, etching back the second epitaxial layer by taking the reference gate and the outer wall of the gate as masks to penetrate through the second epitaxial layer and stop at the first epitaxial layer; and epitaxially forming a third epitaxial layer on the upper surface of the first epitaxial layer to form a source-drain contact region.

For example, as shown in fig. 7, a third epitaxial layer is epitaxially formed on the upper surface of the second epitaxial layer.

As shown in fig. 8, the second epitaxial layer is etched back and a third epitaxial layer is epitaxially formed on the upper surface of the etched back second epitaxial layer.

As shown in fig. 9, the second epitaxial layer is etched back to penetrate the second epitaxial layer and stop at the first epitaxial layer; and epitaxially forming a third epitaxial layer on the upper surface of the first epitaxial layer.

S140, preparing the reference grid into a grid and preparing a source drain electrode in a source drain contact area.

The grid electrode and the first dielectric layer form a metal-insulator-semiconductor structure or the grid electrode and the second epitaxial layer form Schottky contact, and the source electrode and the drain electrode form ohmic contact with the third epitaxial layer.

In one possible example, preparing the reference gate as the gate and the source and drain electrodes in the source and drain contact region may include the following operations: depositing a fourth dielectric layer on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall; obtaining a second mask layer on the fourth dielectric layer by using a photoetching patterning process; etching the fourth dielectric layer and the second dielectric layer in the reference grid by taking the second mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the second mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the second mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form a gate groove; depositing a grid metal layer on the upper surfaces of the grid groove and the fourth dielectric layer to prepare a grid; the transverse part of the grid electrode is arranged on the upper surface of the fourth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer; depositing a fifth dielectric layer on the transverse part of the grid and the upper surface of the fourth dielectric layer, wherein the fourth dielectric layer and the fifth dielectric layer are sixth dielectric layers; etching the sixth dielectric layer to form a source drain groove, and depositing a source drain metal layer on the upper surfaces of the source drain groove and the sixth dielectric layer to prepare a source drain; the transverse part of the source and drain electrode is transversely arranged on the upper surface of the sixth dielectric layer, the longitudinal part of the source and drain electrode penetrates through the sixth dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer.

Specifically, the fourth dielectric layer is SiO₂、SiNx、SiO_xN_yOr Al₂O₃A single-layer structure of one of the materials. Wherein the thickness of the fourth dielectric layer is 200nm-400 nm.

Specifically, the fifth dielectric layer and the fourth dielectric layer are made of the same material, and the thickness of the fifth dielectric layer is 200nm-400 nm.

For example, as shown in fig. 10, a fourth dielectric layer is deposited on the upper surface of the third epitaxial layer, the upper surface of the reference gate, and the upper surface of the gate outer wall. It should be noted that, in the illustration, the third epitaxial layer is epitaxially formed after the second epitaxial layer is partially etched back, and the third epitaxial layer may not be etched back or penetrate through the second epitaxial layer, and the embodiment of the present application is not particularly limited.

As shown in fig. 11, the second dielectric layer in the reference gate is etched to expose the first thin film layer in the reference gate.

As shown in fig. 12, the first thin film layer in the reference gate is etched and stops on the upper surface of the first dielectric layer to form a gate trench.

As shown in fig. 13, the first thin film layer and the first dielectric layer are etched, stopping on the upper surface of the second epitaxial layer to form a gate trench.

As shown in fig. 14, a gate metal layer is deposited on the upper surfaces of the gate trench and the fourth dielectric layer.

As shown in fig. 15, the gate electrode is prepared according to the gate metal layer. And the lower surface of the longitudinal part of the grid electrode is contacted with the first dielectric layer to form a metal-insulator-semiconductor structure. It should be noted that the gate electrode in the figure shows a mushroom shape, but the gate electrode in the embodiment of the present application may also take other shapes, which need to be determined according to a specific semiconductor process, and is not particularly limited.

As shown in fig. 16, a fifth dielectric layer is deposited on the lateral portion of the gate and the upper surface of the fourth dielectric layer.

As shown in fig. 17, the sixth dielectric layer is etched to form a source/drain trench, and a source/drain metal layer is deposited on the source/drain trench and the upper surface of the sixth dielectric layer to form a source/drain. The transverse part of the source and drain electrode is transversely arranged on the upper surface of the sixth dielectric layer, the longitudinal part of the source and drain electrode penetrates through the sixth dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer to form ohmic contact.

As shown in fig. 18, the lateral portion of the gate electrode is placed in the sixth dielectric layer, and the lower surface of the longitudinal portion of the gate electrode is in contact with the first dielectric layer to be formed.

In one possible example, preparing the reference gate as the gate and the source and drain electrodes in the source and drain contact region may include the following operations: depositing a seventh dielectric layer on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall; etching the seventh dielectric layer to form a source drain groove, and depositing a source drain metal layer on the upper surfaces of the source drain groove and the seventh dielectric layer to prepare a source drain; the transverse part of the source drain electrode is transversely arranged on the upper surface of the seventh dielectric layer, the longitudinal part of the source drain electrode penetrates through the seventh dielectric layer, and the lower surface of the longitudinal part of the source drain electrode is in contact with the third epitaxial layer; forming an eighth dielectric layer, wherein the eighth dielectric layer covers the upper surfaces of the source drain and the seventh dielectric layer, and the seventh dielectric layer and the eighth dielectric layer are ninth dielectric layers; obtaining a third mask layer on the ninth dielectric layer by using a photoetching process; etching the ninth dielectric layer and the second dielectric layer in the reference grid by taking the third mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the third mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the third mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form a gate groove; forming a grid metal layer to prepare a grid, wherein the grid metal layer covers the grid groove and the upper surface of the ninth dielectric layer; and the lower surface of the longitudinal part of the grid electrode is contacted with the first dielectric layer or the second epitaxial layer.

Specifically, the seventh dielectric layer is SiO₂、SiNx、SiO_xN_yOr Al₂O₃A single-layer structure of one of the materials. Wherein the thickness of the seventh dielectric layer is 200nm-400 nm.

Specifically, the eighth dielectric layer and the seventh dielectric layer are made of the same material, and the thickness of the eighth dielectric layer is 200nm-400 nm.

For example, as shown in fig. 19, a seventh dielectric layer is deposited on the upper surface of the third epitaxial layer, the upper surface of the reference gate, and the upper surface of the gate outer wall. And then, etching the seventh dielectric layer to form a source drain groove, and depositing a source drain metal layer on the upper surfaces of the source drain groove and the seventh dielectric layer to prepare a source drain. And the lower surface of the longitudinal part of the source drain electrode is in contact with the third epitaxial layer to form ohmic contact.

As shown in fig. 20, an eighth dielectric layer is deposited on the upper surfaces of the source and drain electrodes and the seventh dielectric layer. And the seventh dielectric layer and the eighth dielectric layer are ninth dielectric layers.

As shown in fig. 21, a third mask layer is obtained on the ninth dielectric layer by using a photolithography and patterning process, and then the ninth dielectric layer and the second dielectric layer in the reference gate are etched by using the third mask layer as a mask to expose the first thin film layer in the reference gate.

As shown in fig. 22, the first thin film layer is etched by using the third mask layer as a mask, and the gate trench is formed by stopping on the upper surface of the first dielectric layer.

As shown in fig. 23, a gate metal layer is deposited on the upper surfaces of the gate trench and the ninth dielectric layer to prepare a gate. And the lower surface of the longitudinal part of the grid electrode is contacted with the first dielectric layer to form a metal-insulator-semiconductor structure.

Specifically, the fourth dielectric layer may be SiO₂、SiNx、SiO_xN_yOr Al₂O₃A single-layer structure of one of the materials. The thickness of the fourth dielectric layer can be 200nm-400 nm. It should be noted that the fourth dielectric layer can be deposited by ALD, PEALD, PECVD, LPCVD, plasma oxidation, thermal oxidation, PLD, MOCVD, or the like.

Specifically, the fifth dielectric layer and the fourth dielectric layer are made of the same material. The thickness of the fifth dielectric layer can be 200nm-400 nm.

Specifically, the seventh dielectric layer may be SiO₂、SiNx、SiO_xN_yOr Al₂O₃A single-layer structure of one of the materials. The thickness of the seventh dielectric layer can be 200nm-400 nm. It should be noted that the seventh dielectric layer can be deposited by ALD, PEALD, PECVD, LPCVD, plasma oxidation, thermal oxidation, PLD, MOCVD, or the like.

Specifically, the eighth dielectric layer and the seventh dielectric layer are made of the same material. The thickness of the eighth dielectric layer may be 200nm to 400 nm.

Specifically, the gate metal layer may be a multilayer structure of TiN/Al/TiN, TaN/Al/TaN, etc., and may be deposited by Physical Vapor Deposition (PVD), Pulsed Laser Deposition (PLD), Atomic Layer Deposition (ALD), etc. It should be noted that the gate may be mushroom-shaped or other shapes, and this is not particularly limited.

Specifically, the source-drain metal layer may be a multilayer structure of titanium/aluminum/titanium nitride (Ti/Al/TiN), titanium/aluminum/titanium nitride (Ti/Al/Ti/TiN), tantalum/aluminum/tantalum nitride (Ta/Al/TaN), tantalum/aluminum/tantalum nitride (Ta/Al/Ta/TaN), and may be deposited by PVD, PLD, ALD, or the like. It should be noted that the source and drain may be T-shaped or other shapes, and this is not particularly limited.

Further, the thickness of the fourth dielectric layer may be 300nm, the thickness of the gate metal layer may be 150nm, the thickness of the fifth dielectric layer may be 300nm, the thickness of the seventh dielectric layer may be 300nm, and the thickness of the eighth dielectric layer may be 300 nm.

It can be seen that, in the embodiment of the present application, firstly, by adopting a method compatible with a CMOS process, it is beneficial to implement the fabrication of a low-cost high-yield GaN radio frequency HEMT integrated device and to reduce the size of the integrated device. And secondly, a reference grid of polysilicon, amorphous silicon, silicon dioxide, silicon nitride or silicon oxynitride is adopted, so that the grid process integration method of full self-alignment and small-size structure is facilitated. Then, the size and parasitic resistance from the source electrode, the drain electrode and the grid electrode can be reduced through the fully self-aligned grid electrode small-size structure, and the performance of the GaN HEMT integrated device in radio frequency and millimeter wave application can be improved. And finally, the parasitic resistance and the contact resistance of the source and the drain are further reduced through a third epitaxial layer which is completely compatible with the secondary epitaxial growth of the CMOS process.

The above example introduces a method of fabricating a GaN HEMT device. The structure of a GaN HEMT device is described in detail below, the GaN HEMT device including: the device comprises a substrate, a buffer layer, a first epitaxial layer, a second external delay, a first dielectric layer, a grid external wall, a heavily doped third epitaxial layer, a grid and a source drain.

The forbidden band of the second epitaxial layer is wider than that of the first epitaxial layer, and a two-dimensional electron gas conducting channel is formed between the first epitaxial layer and the second epitaxial layer; the buffer layer, the first epitaxial layer and the second epitaxial layer are sequentially arranged on the upper surface of the substrate from bottom to top; the upper surface of the second epitaxial layer is sequentially overlapped with a first dielectric layer and a cap layer, the cap layer is used for preparing a reference grid of the GaNHEMT device, the cap layer comprises a first thin layer and a second dielectric layer, the first thin layer and the second dielectric layer are sequentially arranged on the upper surface of the first dielectric layer from bottom to top, and the first thin layer comprises at least one of the following components: a polysilicon layer, an amorphous silicon layer, a silicon dioxide layer, a silicon nitride layer and a silicon oxynitride layer; the grid outer wall is positioned on the outer side of the reference grid and is arranged on the upper surface of the first dielectric layer; the third epitaxial layer is formed by taking the reference grid and the outer wall of the grid as masks, the third epitaxial layer is used for forming a low-resistance source-drain contact area so as to reduce the contact resistance of the source-drain electrode, and the source-drain contact area is positioned on two sides of the reference grid; the grid electrode is formed through reference grid electrode preparation, the source drain electrode is formed through source drain contact region preparation, the grid electrode and the first dielectric layer form a metal-insulator-semiconductor structure or the grid electrode and the second epitaxial layer form Schottky contact, and the source drain electrode and the third epitaxial layer form ohmic contact.

For example, referring to fig. 24, the buffer layer, the first epitaxial layer, and the second epitaxial layer are sequentially disposed on the upper surface of the substrate from bottom to top, the second epitaxial layer located in the source-drain region is thinner than the second epitaxial layer located in the gate region, the third epitaxial layer is disposed on the upper surface of the second epitaxial layer, the gate outer wall is located on both sides of the gate, the gate is disposed in the sixth dielectric layer, the lower surface of the longitudinal portion of the gate is in contact with the first dielectric layer, the lower surface of the longitudinal portion of the source-drain electrode is in contact with the third epitaxial layer, and the lateral portion of the source-drain electrode is disposed across the upper surface of the sixth.

Referring to fig. 25, similar to fig. 24, except that the lower surface of the gate is in contact with the second epitaxial layer.

Referring to fig. 26, similar to fig. 24, except that a third epitaxial layer is disposed on the upper surface of the first epitaxial layer. It should be noted that the gate may also be in contact with the second epitaxial layer, and is not particularly limited.

Referring to fig. 27, similar to fig. 24, except that the second epitaxial layer at the source and drain regions is as thick as the second epitaxial layer at the gate region. It should be noted that the gate may also be in contact with the second epitaxial layer, and is not particularly limited.

Referring to fig. 28, the buffer layer, the first epitaxial layer and the second epitaxial layer are sequentially disposed on the upper surface of the substrate from bottom to top, the second epitaxial layer located in the source-drain region is thinner than the second epitaxial layer located in the gate region, the third epitaxial layer is disposed on the upper surface of the second epitaxial layer, the outer wall of the gate is located on two sides of the gate, the source-drain region is disposed in the ninth dielectric layer, the lower surface of the longitudinal portion of the source-drain region is in contact with the third epitaxial layer, the transverse portion of the gate is disposed on the upper surface of the ninth dielectric layer in a transverse mode, and the lower surface of the longitudinal portion of the gate is. It should be noted that, similarly to the above, in the illustration, the second epitaxial layer located in the source/drain region may be as thick as the second epitaxial layer located in the gate region, or the third epitaxial layer may be disposed on the upper surface of the first epitaxial layer, or the gate may be in contact with the second epitaxial layer, which is not limited in particular.

It can be seen that, in the embodiment of the present application, firstly, by adopting a method compatible with a CMOS process, it is beneficial to implement the fabrication of a low-cost high-yield GaN radio frequency HEMT integrated device and to reduce the size of the integrated device. And secondly, a reference grid of polysilicon, amorphous silicon, silicon dioxide, silicon nitride or silicon oxynitride is adopted, so that the grid process integration method of full self-alignment and small-size structure is facilitated. Then, through photoetching and a fully self-aligned grid electrode small-size structure, the size from a source electrode, a drain electrode to a grid electrode and parasitic resistance are reduced, and the performance of the GaN HEMT integrated device in radio frequency and millimeter wave application is improved. And finally, the parasitic resistance and the contact resistance of the source and the drain are further reduced through a third epitaxial layer which is completely compatible with the secondary epitaxial growth of the CMOS process.

In one possible example, the GaN HEMT device may further comprise a third dielectric layer; the third dielectric layer is used for forming a grid outer wall and covers the upper surface of the first dielectric layer and the upper surface and the outer side of the reference grid; the gate outer wall may be formed by: and etching the third dielectric layer, and stopping on the second dielectric layer and the first dielectric layer to form a grid outer wall.

In one possible example, the third epitaxial layer may be formed by: extending the upper surface of the second epitaxial layer to form a third epitaxial layer according to the reference grid and the grid outer wall as masks so as to form a source-drain contact region; or, etching back the second epitaxial layer by taking the reference gate and the outer wall of the gate as masks; extending the upper surface of the etched-back second delay layer to form a third epitaxial layer so as to form a source-drain contact area; the thickness of the second epitaxial layer positioned in the source-drain contact region is thinner than that of the second epitaxial layer positioned in the gate groove region; or back-etching the second epitaxial layer by taking the reference gate and the outer wall of the gate as masks to penetrate through the second epitaxial layer and stop at the first epitaxial layer; and epitaxially forming a third epitaxial layer on the upper surface of the first epitaxial layer to form a source-drain contact region.

In one possible example, the GaN HEMT device may further include a sixth dielectric layer including a fourth dielectric layer and a fifth dielectric layer; the fourth dielectric layer is arranged on the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall; the gate is prepared by: obtaining a second mask layer on the fourth dielectric layer by using a photoetching patterning process; etching the fourth dielectric layer and the second dielectric layer in the reference grid by taking the second mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the second mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the second mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form a gate groove; depositing a grid metal layer on the upper surfaces of the grid groove and the fourth dielectric layer to prepare a grid; the transverse part of the grid electrode is arranged on the upper surface of the fourth dielectric layer, and the lower surface of the longitudinal part of the grid electrode is in contact with the first dielectric layer or the second epitaxial layer; the fifth dielectric layer covers the transverse part of the grid and the upper surface of the fourth dielectric layer; the source and drain electrodes are prepared by etching the sixth dielectric layer to form a source and drain groove and depositing a source and drain electrode metal layer on the upper surfaces of the source and drain groove and the sixth dielectric layer; the transverse part of the source and drain electrode is transversely arranged on the upper surface of the sixth dielectric layer, the longitudinal part of the source and drain electrode penetrates through the sixth dielectric layer, and the lower surface of the longitudinal part of the source and drain electrode is in contact with the third epitaxial layer.

In one possible example, the GaN HEMT device further comprises a ninth dielectric layer comprising a seventh dielectric layer and an eighth dielectric layer; the seventh dielectric layer covers the upper surface of the third epitaxial layer, the upper surface of the reference grid and the upper surface of the grid outer wall; the source and drain electrodes are prepared by etching the seventh dielectric layer to form a source and drain groove and depositing a source and drain electrode metal layer on the upper surfaces of the source and drain groove and the seventh dielectric layer; the transverse part of the source drain electrode is transversely arranged on the upper surface of the seventh dielectric layer, the longitudinal part of the source drain electrode penetrates through the seventh dielectric layer, and the lower surface of the longitudinal part of the source drain electrode is in contact with the third epitaxial layer; the eighth dielectric layer covers the upper surfaces of the source drain electrode and the seventh dielectric layer; the gate is prepared by: obtaining a third mask layer on the ninth dielectric layer by using a photoetching process; etching the ninth dielectric layer and the second dielectric layer in the reference grid by taking the third mask layer as a mask to expose the first thin film layer in the reference grid; etching the first thin film layer by taking the first mask layer as a mask, and stopping on the upper surface of the first medium layer to form a gate groove; or, etching the first thin film layer and the first dielectric layer by taking the third mask layer as a mask, and stopping on the upper surface of the second epitaxial layer to form a gate groove; forming a grid metal layer to prepare a grid, wherein the grid metal layer covers the grid groove and the upper surface of the ninth dielectric layer; and the lower surface of the longitudinal part of the grid electrode is contacted with the first dielectric layer or the second epitaxial layer.

In one possible example, the substrate is a single crystal structure of one of Si, GaN, SiC, sapphire, or diamond; and/or the buffer layer is AlN,A single-layer or multi-layer structure composed of at least one of GaN and AlGaN, the thickness of the buffer layer is 0.5-4 um; and/or the first epitaxial layer is a single-layer structure formed by GaN materials or a multi-layer structure formed by AlGaN, InGaN and GaN materials, the second epitaxial layer is a single-layer or multi-layer structure formed by at least one of AlGaN, InGaN, InAlN, and InAlGaN, the thickness of the first epitaxial layer is 10-500nm, and the thickness of the second epitaxial layer is 5-30 nm; and/or the first dielectric layer is SiO₂、SiN_x、Al₂O₃、AlN、AlON、SiO_xN_y、HfO₂、Ga₂O₃A single-layer or multi-layer structure composed of at least one of the above materials, wherein the thickness of the first dielectric layer is 5-30 nm; and/or the thickness of the first thin film layer is 100-300 nm; and/or the second dielectric layer is SiO₂、SiNx、SiO_xN_yOr Al₂O₃The thickness of the second dielectric layer is 20-100 nm; and/or the third dielectric layer is SiN_x、SiNx、SiO_xN_y、Al₂O₃The thickness of the third dielectric layer is 100-200 nm; and/or the third epitaxial layer is of a single-layer structure formed by one material of n-type GaN, AlGaN or InGaN, and the thickness of the third epitaxial layer is 10-50 nm; and/or the fourth dielectric layer is SiO₂、SiNx、SiO_xN_yOr Al₂O₃The thickness of the fourth dielectric layer is 200nm-400nm, the fifth dielectric layer and the fourth dielectric layer are made of the same material, and the thickness of the fifth dielectric layer is 200nm-400 nm; or the seventh dielectric layer is SiO₂、SiNx、SiO_xN_yOr Al₂O₃The thickness of the seventh dielectric layer is 200nm-400nm, the eighth dielectric layer and the seventh dielectric layer are made of the same material, and the thickness of the eighth dielectric layer is 200nm-400 nm.

For simplicity of description, each of the above method embodiments is described as a series of combinations of operations. Those skilled in the art should appreciate that the present application is not limited by the order of acts described, as some steps in the embodiments of the present application may occur in other orders or concurrently. Moreover, those skilled in the art will recognize that the embodiments described in this specification are among the preferred embodiments and that no action is necessarily required by the embodiments of the application.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The embodiments of the present application are described in detail above, and the description in the embodiments of the present application is only for assisting understanding of the method and the core idea of the present application. One skilled in the art will appreciate that the embodiments of the present application can be varied in both the detailed description and the application, and thus the present description should not be construed as limiting the application.

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