阅读说明：本技术 一种半导体器件的终端结构及其制造方法 (Terminal structure of semiconductor device and manufacturing method thereof ) 是由 肖婷 史波 曾丹 敖利波 曹俊 于 2019-10-21 设计创作，主要内容包括：本发明公开了一种半导体器件的终端结构及其制造方法,一种半导体器件的终端结构,包括：半导体衬底层、沟槽和离子掺杂层；多个沟槽沿预设方向开设在所述半导体衬底层上表面,多个所述沟槽的尺寸沿所述预设方向逐渐增大；离子掺杂层通过离子注入在所述半导体衬底层形成,所述离子掺杂层包围所述沟槽。本发明在沟槽刻蚀阶段对沟槽结构进行改进,通过沟槽刻蚀尺寸来影响刻蚀深度情况,实现终端结构的变掺杂,无需对终端离子注入工艺进行调整,避免了离子断开,不能实现渐变,引起器件漏电的问题。(The invention discloses a terminal structure of a semiconductor device and a manufacturing method thereof, and the terminal structure of the semiconductor device comprises: the semiconductor substrate layer, the groove and the ion doping layer; the plurality of grooves are formed in the upper surface of the semiconductor substrate layer along a preset direction, and the sizes of the plurality of grooves are gradually increased along the preset direction; an ion doped layer is formed in the semiconductor substrate layer by ion implantation, the ion doped layer surrounding the trench. According to the invention, the groove structure is improved in the groove etching stage, the etching depth condition is influenced by the groove etching size, the variable doping of the terminal structure is realized, the terminal ion implantation process is not required to be adjusted, and the problem of electric leakage of a device caused by ion disconnection and incapability of realizing gradual change is avoided.)

1. A termination structure for a semiconductor device, comprising:

a semiconductor substrate layer (1);

the semiconductor substrate layer is provided with a plurality of grooves (2) which are arranged on the upper surface of the semiconductor substrate layer along a preset direction, and the sizes of the grooves (2) are gradually increased along the preset direction;

an ion-doped layer (3) formed on the semiconductor substrate layer (1) by ion implantation, the ion-doped layer (3) surrounding the trench (2).

2. A termination structure for a semiconductor device according to claim 1, wherein the depth of a plurality of said trenches (2) increases gradually along said predetermined direction and/or the width of a plurality of said trenches (2) increases gradually along said predetermined direction.

3. A termination structure for a semiconductor device according to claim 1, wherein a plurality of said trenches (2) are arranged at regular intervals.

4. A termination structure for a semiconductor device according to claim 1, wherein said ion-doped layer (3) comprises a plurality of ion-doped modules (31) connected in series along said predetermined direction, said ion-doped modules (31) comprising a bottom (311) surrounding the bottom wall of said trench (2) and side portions (312) surrounding the side walls of said trench (2).

5. A termination structure for a semiconductor device according to claim 1, comprising a first oxide layer (4), a polysilicon layer (5), a second oxide layer (6) and a metal layer (7); the first oxidation layer (4) is arranged on the upper surface of the semiconductor substrate layer (1) and on the inner side of the groove (2); the polycrystalline silicon layer (5) is arranged on the first oxidation layer (4) positioned on the inner side of the groove (2); the second oxide layer (6) is arranged on the first oxide layer (4) on the surface of the semiconductor and fills the groove (2); the metal layers (7) are arranged on two sides of the second oxidation layer (6) and are respectively connected with the second oxidation layer (6) and the semiconductor substrate layer (1).

6. A method of fabricating a termination structure of a semiconductor device, comprising the steps of:

etching a groove, namely etching and forming a plurality of grooves on the upper surface of the semiconductor substrate layer along a preset direction, wherein the width size and/or the depth size of the plurality of grooves are gradually increased along the preset direction;

and P-type ion implantation, wherein ion implantation is performed on the semiconductor substrate layer to form an ion doping layer, and the ion doping layer surrounds the groove.

7. A method of manufacturing a termination structure according to claim 6, comprising:

and arranging a first oxidation layer, wherein the first oxidation layer is arranged on the upper surface of the semiconductor substrate layer and on the inner side of the groove.

8. The method of manufacturing a termination structure according to claim 7, comprising:

and depositing a polysilicon layer, depositing the polysilicon layer on the first oxide layer, and removing the polysilicon on two sides above the groove so that the polysilicon layer is only positioned on the inner side of the groove.

9. The method of manufacturing a termination structure according to claim 8, comprising:

and arranging a second oxide layer, wherein the second oxide layer is deposited on the first oxide layer on the surface of the semiconductor and fills the groove.

10. The method of manufacturing a termination structure according to claim 9, comprising:

and arranging metal layers, and depositing the metal layers on two sides of the semiconductor substrate layer.

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a terminal structure of a semiconductor device.

Background

Power semiconductor devices represented by IGBTs and MOSFETs are mainstream devices in the field of power electronics today, and are key devices for weak current control of strong current. The circuit is widely applied to various circuits such as power control circuits, driving circuits and the like. Especially, the system has irreplaceable effects in the fields of various variable frequency motors, photovoltaic inversion, smart power grids, new energy vehicles, electric locomotive traction drive and the like.

In the conventional design, a field limiting ring (combined with a metal or polycrystalline field plate) structure, a junction terminal extension structure, a lateral variable doping structure and the like are often adopted in a terminal voltage-resistant structure of a power semiconductor device (such as a MOSFET and an IGBT), wherein the junction terminal extension structure and the lateral variable doping structure have great advantages in occupying terminal width.

The existing terminal structure is mostly carried out from two directions of layout design and terminal ion implantation process adjustment, and a variable doping structure is realized. When the structure is actually produced, the dosage of ion implantation needs to be accurately controlled, the disconnection of the implanted ions of the terminal ring is easily caused, the gradual change cannot be realized, and the electric leakage of a device is caused.

Disclosure of Invention

The invention provides a terminal structure of a semiconductor device, aiming at solving the problems that the existing structure for realizing variable doping is easy to generate ion disconnection, cannot realize the gradual change and causes the electric leakage of the device.

In order to achieve the purpose, the technical scheme provided by the invention is as follows:

a termination structure for a semiconductor device, comprising:

a semiconductor substrate layer;

the semiconductor substrate layer is provided with a plurality of grooves along a preset direction, and the sizes of the grooves are gradually increased along the preset direction;

an ion doped layer formed on the semiconductor substrate layer by ion implantation, the ion doped layer surrounding the trench.

Further, the depth of the plurality of grooves gradually increases along the preset direction, and/or the width of the plurality of grooves gradually increases along the preset direction.

Further, a plurality of the grooves are uniformly distributed at intervals.

Furthermore, the ion doping layer comprises a plurality of ion doping modules which are sequentially connected along the preset direction, and each ion doping module comprises a bottom part surrounding the bottom wall of the groove and a side part surrounding the side wall of the groove.

Further, the device comprises a first oxide layer, a polysilicon layer, a second oxide layer and a metal layer; the first oxidation layer is arranged on the upper surface of the semiconductor substrate layer and on the inner side of the groove; the polycrystalline silicon layer is arranged on the first oxidation layer positioned on the inner side of the groove; the second oxide layer is arranged on the first oxide layer on the surface of the semiconductor and fills the groove; the metal layers are arranged on two sides of the second oxidation layer and are respectively connected with the second oxidation layer and the semiconductor substrate layer.

A second object of the present invention is to provide a method for manufacturing a termination structure of a semiconductor device, comprising the steps of:

etching a groove, namely etching and forming a plurality of grooves on the upper surface of the semiconductor substrate layer along a preset direction, wherein the width size and/or the depth size of the plurality of grooves are gradually increased along the preset direction;

and P-type ion implantation, wherein ion implantation is performed on the semiconductor substrate layer to form an ion doping layer, and the ion doping layer surrounds the groove.

Further, the manufacturing method of the terminal structure of the semiconductor device comprises the following steps:

and arranging a first oxidation layer, wherein the first oxidation layer is arranged on the upper surface of the semiconductor substrate layer and on the inner side of the groove.

Further, the manufacturing method of the terminal structure of the semiconductor device comprises the following steps:

and depositing a polysilicon layer, depositing the polysilicon layer on the first oxide layer, and removing the polysilicon on two sides above the groove so that the polysilicon layer is only positioned on the inner side of the groove.

Further, the manufacturing method of the terminal structure of the semiconductor device comprises the following steps:

and arranging a second oxide layer, wherein the second oxide layer is deposited on the first oxide layer on the surface of the semiconductor and fills the groove.

Further, the manufacturing method of the terminal structure of the semiconductor device comprises the following steps:

and arranging metal layers, and depositing the metal layers on two sides of the semiconductor substrate layer.

According to the terminal structure of the semiconductor device and the manufacturing method thereof provided by the invention, the groove structure is improved in the groove etching stage, the etching depth condition is influenced by the groove etching size, the variable doping of the terminal structure is realized, the terminal ion implantation process is not required to be adjusted, and the problems of ion disconnection, incapability of realizing gradual change and device electric leakage are avoided.

Advantages of the above additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a schematic view of a terminal structure of a semiconductor device according to an embodiment of the present invention;

fig. 2 is a schematic view of a termination structure of another semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a semiconductor substrate layer after a trench is etched in the method for manufacturing the terminal structure according to the embodiment of the invention;

fig. 4 is a schematic diagram of a semiconductor substrate layer after P-type ion implantation in the method for manufacturing the terminal structure according to the embodiment of the invention;

fig. 5 is a schematic view after a first oxide layer is formed on a semiconductor substrate layer in the method for manufacturing a termination structure according to the embodiment of the invention;

FIG. 6 is a schematic illustration of a method of fabricating a termination structure according to an embodiment of the present invention after depositing polysilicon on a semiconductor substrate layer;

FIG. 7 is a schematic diagram illustrating the method for fabricating a terminal structure according to the embodiment of the present invention after removing the excess polysilicon;

fig. 8 is a schematic view after N-type ion implantation is performed on a semiconductor substrate layer in the method for manufacturing a terminal structure according to the embodiment of the present invention;

fig. 9 is a schematic view of forming a second oxide layer on a semiconductor substrate layer in the method for manufacturing a termination structure according to the embodiment of the present invention.

In the drawings, the components represented by the respective reference numerals are listed below:

1. a semiconductor substrate layer; 2. a trench; 3. an ion doping layer; 31. an ion doping module; 311. a bottom; 312. a side portion; 4. a first oxide layer; 5. a polysilicon layer; 6. a second oxide layer; 7. a metal layer; 8. a stop ring.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, the present embodiment provides a terminal structure of a semiconductor device, where the base of the terminal structure is a semiconductor substrate layer 1, specifically, a wafer substrate, and based on the problems existing in the background art, the present embodiment improves a structure of a groove in a groove etching stage, first, a plurality of grooves 2 of the present embodiment are spaced apart from each other along a preset direction and are formed on an upper surface of the semiconductor substrate layer, and sizes of the plurality of grooves 2 are gradually increased along the preset direction (from left to right in the drawing); then, an ion-doped layer 3 formed on the semiconductor substrate layer 1 by ion implantation, the ion-doped layer 3 surrounding the trench 2.

The terminal structure of the semiconductor device of the embodiment improves the structure of the groove 2 in the etching stage of the groove 2, the etching depth condition is influenced by the etching size of the groove 2, the variable doping of the terminal structure is realized, the terminal ion implantation process is not required to be adjusted, the ion disconnection is avoided, the gradual change cannot be realized, and the problem of device electric leakage is caused.

The depth of the plurality of trenches 2 of the present embodiment gradually increases along the preset direction, and the width of the plurality of trenches 2 gradually increases along the preset direction, so as to improve the effect of variable doping.

Moreover, the trenches 2 of the present embodiment are uniformly spaced, so that the ion doping layer 3 between two adjacent trenches 2 is uniformly distributed along the predetermined direction, so as to facilitate the subsequent ion doping step.

Further, the ion doping layer 3 of the present embodiment can be regarded as comprising a plurality of ion doping modules 31 connected in sequence along a predetermined direction, wherein the ion doping module 31 comprises a bottom 311 surrounding the bottom wall of the trench 2 and a side 312 surrounding the sidewall of the trench 2, where the side 312 is the "ion doping layer 3 between two adjacent trenches 2" mentioned above.

In addition, in order to realize the functionality of the power device, the termination structure of the semiconductor device of the present embodiment further includes the levels of the first oxide layer 4, the polysilicon layer 5, the second oxide layer 6, and the metal layer 7, in addition to the trench 2 and the ion doping module 31 described above.

Wherein, the first oxide layer 4 of the embodiment is arranged on the upper surface of the semiconductor substrate layer 1 and on the inner side of the trench 2; a polysilicon layer 5(poly layer) of the present embodiment is provided on the first oxide layer 4 located inside the trench 2; the second oxide layer 6 of the present embodiment is disposed on the first oxide layer 4 on the semiconductor surface, and fills all the trenches 2 of the present embodiment, and the second oxide layer 6 plays a role of isolation; the metal layers 7 of this embodiment are disposed on both sides of the second oxide layer 6, and are respectively connected to the second oxide layer 6 and the semiconductor substrate layer 1, so as to perform fixing and connecting functions.

Based on the above-described terminal structure of the semiconductor device, the present embodiment also provides a manufacturing method including the steps of:

firstly, etching the grooves 2, and etching the upper surface of the semiconductor substrate layer 1 along a preset direction to form a plurality of grooves 2, wherein the width size and/or the depth size of the plurality of grooves 2 are gradually increased along the preset direction.

Specifically, a hard mask (hardmask) is deposited on a substrate wafer, the hardmask is etched by using a mask plate, unnecessary patterns are etched, and then the wafer substrate is etched to form a groove 2 structure. After the etching is completed, hardmark is removed. To form the structure shown in figure 3.

Further, P-type ion implantation is started, and ion implantation is performed on the semiconductor substrate layer 1 to form an ion doped layer 3, the ion doped layer 3 surrounding the trench 2.

Specifically, the P-type ion implantation is performed on the wafer substrate, and this step requires that the wafer be tilted by 30-60 degrees, and simultaneously the wafer is rotated, so that the ions can be uniformly implanted into the side wall of the trench 2 and the bottom wall of the trench 2. Then, a diffusion step is carried out to form step-shaped P-type ion doping. And realizing variable doping of the terminal structure. Resulting in the structure shown in fig. 4.

Further, a first oxide layer 4 is arranged at the beginning, the first oxide layer 4 is arranged on the upper surface of the semiconductor substrate layer 1 and on the inner side of the groove 2, specifically, an oxide layer is arranged on the wafer and uniformly coated on the surface of the wafer, including the inner part of the groove 2. To form the structure of figure 5.

Further, a polysilicon layer 5(poly layer) is deposited, the polysilicon layer 5 is deposited on the first oxide layer 4, and the polysilicon layer 5 on both sides above the trench 2 is removed so that the polysilicon layer 5 is located only inside the trench 2. The smaller trenches 2 will be filled with polysilicon and the wider trenches 2 will form a uniform adhesion on the sidewalls and bottom wall. To form the structure of figure 6.

The step also includes removing the excess poly on the front surface of the wafer, and reserving the poly in the trench 2, which can play a role of suppressing the electric field. To form the structure of fig. 7.

Further, the photoresist is exposed, developed and etched by using a mask, the outermost photoresist is opened, then the outermost N-type ion implantation is performed to form a stop ring 8, and then the photoresist is removed. To form the structure of figure 8.

Further, a second oxide layer 6 is initially provided, the second oxide layer 6 being deposited on the first oxide layer 4 on the semiconductor surface and filling the trench 2, it being understood that the second oxide layer 6 is partially on the first oxide layer 4 and the portion located within the trench 2 is provided on the polysilicon layer 5.

Specifically, BPSG is deposited to form an isolation oxide layer. The unwanted oxide layer is then etched away with a reticle to form the structure of fig. 9.

And finally, depositing a metal layer 7, depositing the metal layer 7 on two sides of the semiconductor substrate layer 1, exposing, developing and etching, and forming a metal field plate at the terminal to finally realize the variable doping structure. To form the finished structure of figure 1.

In addition, referring to fig. 2, the present embodiment further provides another terminal structure of a semiconductor device, the specific structure and the manufacturing method of which are substantially the same as those of the terminal structure of the semiconductor device in fig. 1, except that there is a certain distance between the side portions 312 of two adjacent ion doping modules 31, that is, the ion doping layer of the terminal structure is an intermittent structure, and this structure is implemented by controlling ion implantation.

In the description of the present invention, it is to be understood that the terms "inside", "outside", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.