阅读说明：本技术 一种逆变器pwm电压采样前处理装置 (Inverter PWM voltage sampling pretreatment device ) 是由 沈捷 何绍民 迈克·舒伯特 杨欢 于 2020-12-31 设计创作，主要内容包括：本申请提供了一种逆变器PWM电压采样前处理装置,包括充放电支路和用于隔离的光耦支路,充放电支路包括与逆变器直流侧并联的电阻,与开关管输出电容组成充放电回路以使充放电回路在死区时间内完成充放电过程；光耦支路包括与逆变器直流侧并联的发光二极管和其集电极用于输出至PWM电压采样设备的光敏三极管。本方案通过充放电支路解决了逆变器空载时由于没有输出电流而造成死区检测困难的问题,构造了同一桥臂上下管全关时逆变器输出电压与单管开关期间输出电压的差异,使得PWM死区电压可以被检测出来,从而提高了PWM电压采样的精度。另外还可通过钳位支路过滤采样信号噪声,进一步提高检测准确性。此外还可通过电阻网络防范散热风险。(The application provides a pretreatment device for sampling PWM voltage of an inverter, which comprises a charge-discharge branch and an optocoupler branch for isolation, wherein the charge-discharge branch comprises a resistor connected with the DC side of the inverter in parallel, and forms a charge-discharge loop with an output capacitor of a switching tube so that the charge-discharge loop completes a charge-discharge process in dead time; the optical coupling branch comprises a light emitting diode connected with the direct current side of the inverter in parallel and a phototriode of which the collector is used for outputting to the PWM voltage sampling device. According to the scheme, the problem that dead zone detection is difficult due to the fact that no output current exists when the inverter is in no-load is solved through the charging and discharging branch circuits, the difference between the output voltage of the inverter when the upper pipe and the lower pipe of the same bridge arm are completely closed and the output voltage during the single-pipe switching period is constructed, the PWM dead zone voltage can be detected, and the precision of PWM voltage sampling is improved. In addition, the noise of the sampling signal can be filtered through the clamping branch circuit, and the detection accuracy is further improved. In addition, the heat dissipation risk can be prevented through the resistance network.)

1. The utility model provides an inverter PWM voltage sampling pretreatment device, its characterized in that, pretreatment device is used for connecting the same bridge arm of inverter, pretreatment device includes charge-discharge branch road and the opto-coupler branch road that is used for keeping apart, wherein:

the charging and discharging branch circuit comprises a resistor connected with the direct current side of the inverter in parallel, and the resistor is used for forming a charging and discharging loop with an output capacitor of the inverter switching tube so that the charging and discharging loop can complete a charging and discharging process within the dead time of the inverter;

the optical coupling branch circuit comprises a light emitting diode used for signal generation and a corresponding photosensitive triode used for signal receiving, the light emitting diode is connected with the direct current side of the inverter in parallel, and a collector of the photosensitive triode is used for being connected with PWM voltage sampling equipment.

2. The pretreatment apparatus according to claim 1, wherein the switching tube is an Insulated Gate Bipolar Transistor (IGBT).

3. The pretreatment apparatus according to claim 1, wherein the switching tube includes a first switching tube and a second switching tube, the resistor in the charge/discharge branch includes a first resistor and a second resistor, the first resistor is connected in parallel with the first switching tube, and the second resistor is connected in parallel with the second switching tube.

4. The pretreatment apparatus according to claim 3, wherein the first resistor and/or the second resistor is/are a resistor network, and the resistor network comprises a plurality of resistors connected in series-parallel.

5. The pretreatment apparatus according to claim 3, wherein the resistance values of the first resistor and/or the second resistor are determined by:

determining a time constant tau according to the dead time of the inverter and a preset proportional relation, wherein the time constant tau is the time constant tau of the charge-discharge loop;

and determining the resistance value according to the time constant tau and the output capacitor so as to enable the charge-discharge loop to complete the charge-discharge process within the dead time of the inverter.

6. The pretreatment apparatus according to claim 5, wherein the predetermined proportional relationship is:

the time constant τ is 1/10 of the inverter dead time.

7. The pretreatment apparatus according to claim 1, wherein the switch tube comprises a first switch tube and a second switch tube, the optical coupling branch comprises a first light emitting diode and a first phototriode corresponding to the first light emitting diode, a second light emitting diode and a second phototriode corresponding to the second light emitting diode, the first light emitting diode is connected in parallel with the first switch tube, and the second light emitting diode is connected in parallel with the second switch tube.

8. The pretreatment apparatus according to claim 1, further comprising:

the clamping branch comprises a clamping diode connected with the light emitting diode of the optical coupling circuit in parallel, and the clamping branch is used for providing a voltage threshold range to filter noise of a sampling signal.

9. The pretreatment apparatus according to claim 8, wherein the clamp diode is a zener diode.

10. The pretreatment apparatus according to claim 8, wherein a clamp voltage value of the clamp diode is determined by:

and determining the clamping voltage value according to the noise quality of the sampling signal, wherein the upper limit of the voltage threshold range is below the high level of the voltage generated by the switching tube and is a first specified distance away from the high level, and the lower limit of the voltage threshold range is above the low level of the voltage generated by the switching tube and is a second specified distance away from the low level.

Technical Field

The application relates to the technical field of power electronics and the field of in-loop simulation of motor control hardware, in particular to a pretreatment device for sampling of PWM (pulse width modulation) voltage of an inverter.

Background

The inverter is a DC (direct current) to AC (alternating current) transformer, and can convert direct current electric energy into constant-frequency constant-voltage or frequency-modulation voltage-regulation alternating current. The inverter usually adopts a PWM (pulse width modulation) technique, the PWM has a basic principle that on-off of a switching device of the inverter circuit is controlled to make an output end obtain a series of pulses with equal amplitude, the pulses are used to replace sine waves or required waveforms, i.e. a plurality of pulses are generated in a half cycle of the output waveform, so that the equivalent voltage of each pulse is a sine waveform, the obtained output is smooth and has few low harmonics, the width of each pulse is modulated according to a certain rule, and the size of the output voltage of the inverter circuit can be changed, and the output frequency can also be changed.

The hardware-in-the-loop simulation technology can conveniently simulate an actual motor control scene, and is the strongest and powerful simulation environment before the motor controller moves to actual testing. The hardware-in-loop simulation platform of the motor control system needs to sample the output PWM voltage of the inverter, so that on one hand, the normal operation of the simulation system is ensured, and on the other hand, the test range of the motor control system can be expanded, therefore, the sampling precision of the output PWM voltage of the inverter is very critical to the influence of the performance of the whole hardware-in-loop simulation system.

However, in the process of implementing the solution of the present application, the inventor finds that, when the inverter is in no-load state, that is, when the inverter is not connected to a load, because no output current exists on the output side of the inverter, a fully-off state (for example, in a dead time) of upper and lower tubes of the same bridge arm of the inverter is difficult to detect, and thus, the sampling accuracy of the PWM voltage is adversely affected. The problem that the dead zone is difficult to detect when the inverter is in no-load becomes a big difficulty in the application occasion of the hardware-in-loop simulation based on the motor control.

In the prior art, the hardware-in-loop simulation can be performed by directly adopting the PWM signal sent by the control board card, although the method is reliable, the method does not cover a driving circuit, namely the PWM signal does not pass through the driving circuit and an inverter thereof, so that the testing range is smaller, and a certain difference exists between the testing range and a real scene. In another prior art, a PWM voltage output by the inverter may be directly sampled by a period averaging method, and an average value of one switching period may be obtained by integrating with an integrator.

Disclosure of Invention

The application provides a processing apparatus before inverter PWM voltage sampling to when solving to the sampling of inverter output PWM voltage, because the state of the upper and lower pipe complete shut of same bridge arm leads to the problem that the sampling precision receives the influence.

The embodiment of the application provides processing apparatus before inverter PWM voltage sampling, processing apparatus is used for connecting same bridge arm of inverter, processing apparatus includes charge and discharge branch road and the opto-coupler branch road that is used for keeping apart, wherein:

the charging and discharging branch circuit comprises a resistor connected with the direct current side of the inverter in parallel, and the resistor is used for forming a charging and discharging loop with an output capacitor of the inverter switching tube so that the charging and discharging loop can complete a charging and discharging process within the dead time of the inverter;

the optical coupling branch circuit comprises a light emitting diode used for signal generation and a corresponding photosensitive triode used for signal receiving, the light emitting diode is connected with the direct current side of the inverter in parallel, and a collector of the photosensitive triode is used for being connected with PWM voltage sampling equipment.

Optionally, the switch tube is an insulated gate bipolar transistor IGBT.

Optionally, the switch tube includes a first switch tube and a second switch tube, the resistor in the charge-discharge branch includes a first resistor and a second resistor, the first resistor is connected in parallel with the first switch tube, and the second resistor is connected in parallel with the second switch tube.

Optionally, the first resistor and/or the second resistor are/is a resistor network, and the resistor network includes a plurality of resistors connected in series and parallel.

Optionally, the resistance values of the first resistor and/or the second resistor are determined as follows:

determining a time constant tau according to the dead time of the inverter and a preset proportional relation, wherein the time constant tau is the time constant tau of the charge-discharge loop;

and determining the resistance value according to the time constant tau and the output capacitor so as to enable the charge-discharge loop to complete the charge-discharge process within the dead time of the inverter.

Optionally, the preset proportional relationship is:

the time constant τ is 1/10 of the inverter dead time.

Optionally, the switch tube includes a first switch tube and a second switch tube, the optocoupler branch includes a first light emitting diode and a first phototriode, a second light emitting diode corresponding to the first light emitting diode and a second phototriode corresponding to the second light emitting diode, the first light emitting diode is connected in parallel with the first switch tube, and the second light emitting diode is connected in parallel with the second switch tube.

Optionally, the pretreatment device further includes:

the clamping branch comprises a clamping diode connected with the light emitting diode of the optical coupling circuit in parallel, and the clamping branch is used for providing a voltage threshold range to filter noise of a sampling signal.

Optionally, the clamping diode is specifically a zener diode.

Optionally, the clamping voltage value of the clamping diode is determined by:

and determining the clamping voltage value according to the noise quality of the sampling signal, wherein the upper limit of the voltage threshold range is below the high level of the voltage generated by the switching tube and is a first specified distance away from the high level, and the lower limit of the voltage threshold range is above the low level of the voltage generated by the switching tube and is a second specified distance away from the low level.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

the application provides a preceding processing apparatus of inverter PWM voltage sampling for connect the same bridge arm of inverter, this preceding processing apparatus can include charge and discharge branch road and the opto-coupler branch road that is used for keeping apart, and wherein charge and discharge branch road includes the resistance parallelly connected with the dc side of inverter, and the opto-coupler branch road is including the emitting diode that is used for signal generation and the corresponding photosensitive triode that is used for signal reception. The technical scheme of the application not only enlarges the testing range of hardware-in-the-loop simulation by directly sampling the output PWM voltage of the inverter, better approaches to the real situation, has better application prospect and practical significance, but also more importantly, solves the problem of difficult dead zone detection caused by no output current when the inverter is in no load through the charging and discharging branch, namely, the difference between the inverter output voltage and the output voltage during the on/off period of a single tube under the full-off state of upper and lower tubes of the same bridge arm during the dead zone period is constructed, so that the PWM voltage sampling during the dead zone period can be detected, and the precision of the PWM voltage sampling is improved. Meanwhile, the optical coupling branch circuit solves the isolation problem caused by the rise of the voltage grade due to the fact that the mode of directly sampling the PWM voltage output by the inverter is adopted to enlarge the test range of hardware-in-loop simulation.

In addition, the clamp branch can provide a voltage threshold range to filter the noise of the sampling signal, and the accuracy of dead time detection is further improved. In addition, a resistor network can be used as a resistor in the charging and discharging branch circuit to further prevent heat dissipation risks.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise. Furthermore, these descriptions should not be construed as limiting the embodiments, wherein elements having the same reference number designation are identified as similar elements throughout the figures, and the drawings are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of three-phase PWM output voltages when an inverter is unloaded;

FIG. 2 is a schematic diagram of one phase PWM output voltage of the inverter during no-load;

fig. 3 is a schematic diagram of a processing apparatus before sampling of a PWM voltage of an inverter according to an embodiment of the present application;

fig. 4 is a schematic diagram of a processing apparatus before sampling of a PWM voltage of an inverter according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a no-load inverter one-phase charging and discharging process during a dead band;

FIG. 6 is a schematic diagram of one phase bridge arm output voltage as a function of switching signals;

FIG. 7 is a schematic diagram of a resistor network;

fig. 8 is a schematic diagram of a processing apparatus before sampling of a PWM voltage of an inverter according to an embodiment of the present application;

fig. 9 is a partial view of a light emitting diode and a clamping diode in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application. When referring to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise specified. It should be apparent that the examples described below are only a part of examples of the present application and not all examples, or that the embodiments described in the following exemplary examples do not represent all embodiments consistent with the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," and the like in the description, claims, and drawings of the embodiments of the present application are used for distinguishing between different objects and not for limiting a particular order. In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Fig. 1 is a schematic diagram of three-phase PWM output voltages when the inverter is unloaded. In the application occasions of motor control hardware in loop simulation and the like, PWM voltage output by an inverter needs to be sampled. In fig. 1, Vdc is a dc power supply, two switching tubes are provided in each of the three arms, and U, V, W is a three-phase ac voltage generated by the inverter. The accuracy of sampling the output PWM voltage of the inverter is very important, but when the inverter is in no-load, namely under the condition of not being connected with a load, the inverter has no output current on the output side, so that the totally-closed states of the upper and lower tubes of the same bridge arm, such as the dead zone of the inverter, are difficult to detect.

Fig. 2 is a schematic diagram of one phase PWM output voltage when the inverter is unloaded. In brief, the upper and lower switching tubes in the same bridge arm have three states, i.e., upper and lower switches, and full-off, and the sampling has only two states of high level and low level (which respectively reflect the states of upper and lower switches and upper and lower switches), which cannot identify the full-off state of the three states.

For example, as shown in fig. 2, fig. 2 is one arm (inside the dashed line frame of fig. 1) in fig. 1, the midpoint of the arm is the sampling point, and two switching tubes are represented by S1 and S2, where 0 represents that the switching tube is closed, and 1 represents that the switching tube is open, then as shown in fig. 2, when S1 is equal to 0, S2 is equal to 1, and S1 is equal to 1, and S2 is equal to 0, a high level is generated, but when S1 is equal to 0, and S2 is equal to 0, that is, when two switching tubes on the same arm are both closed, the generated level signal cannot be detected. The problem that the fully closed states of the upper and lower pipes of the same bridge arm, such as the dead zone of an inverter, are difficult to detect when the bridge arm is not connected with a load is a great difficulty in the application of hardware based on motor control in loop simulation.

Fig. 3 is a schematic diagram of a processing apparatus before sampling of a PWM voltage of an inverter according to an embodiment of the present application.

The inverter PWM voltage sampling pretreatment device provided by the embodiment of the application can be applied to the fields of motor control hardware in-loop simulation and the like. Of course, the application scenario of motor control hardware in loop simulation is taken as an example only, and in practical application, the scheme of the present application may also be applied to other application scenarios.

The preprocessing device can be used for preprocessing the PWM voltage sampling of the inverter, so that the output voltage of the inverter in a dead zone period equal to the fully-off state of an upper bridge arm and a lower bridge arm can be detected, the input end (the input end can be provided with a plurality of input ends) of the preprocessing device can be connected with the same bridge arm of the inverter, and the output end of the preprocessing device can be connected with PWM voltage sampling equipment, such as PWM voltage sampling equipment of hardware in a loop simulation system.

Specifically, as shown in fig. 3, the pretreatment device 300 may include a charging and discharging branch 301 and an optical coupling branch 302 for isolation, where:

the charging and discharging branch circuit comprises a resistor connected with the direct current side of the inverter in parallel, and the resistor is used for forming a charging and discharging loop with an output capacitor of the inverter switching tube so that the charging and discharging loop can complete a charging and discharging process within the dead time of the inverter;

the optical coupling branch circuit comprises a light emitting diode used for signal generation and a corresponding photosensitive triode used for signal receiving, the light emitting diode is connected with the direct current side of the inverter in parallel, and a collector of the photosensitive triode is used for being connected with PWM voltage sampling equipment.

The present embodiment is not limited to the specific type of the switching tube, and those skilled in the art can select and design the switching tube according to different requirements/different scenarios, and these choices and designs can be used herein without departing from the spirit and scope of the present application. As an example, the switching tube may be an insulated Gate Bipolar transistor (igbt).

As an example, in a specific implementation, the switching tube includes a first switching tube and a second switching tube, the resistors in the charge and discharge branch include a first resistor and a second resistor, the first resistor is connected in parallel with the first switching tube, and the second resistor is connected in parallel with the second switching tube.

Similarly, the optical coupling branch may include a first light emitting diode, and a first phototransistor corresponding to the first light emitting diode, a second light emitting diode, and a second phototransistor corresponding to the second light emitting diode, where the first light emitting diode is connected in parallel with the first switch tube, and the second light emitting diode is connected in parallel with the second switch tube.

Referring to fig. 4, in fig. 4, S1 is a first switch tube, S2 is a second switch tube, 301a is a first resistor connected in parallel with S1, 301b is a second resistor connected in parallel with S2, 302a is a first led connected in parallel with S1, and 302b is a second led connected in parallel with S2.

The optical coupling branch circuit is used for solving the isolation problem caused by the rise of the voltage grade due to the increase of the test range. The charging and discharging branch circuit is used for providing a charging and discharging loop for an IGBT output capacitor of the inverter, and the output circuit of the IGBT and a resistor connected in parallel form an RC loop so as to solve the problem that dead zone detection is difficult due to no output current when the inverter is in no-load.

The direct-current side parallel resistor is added, an RC circuit is formed by an IGBT output capacitor of the inverter, a charge-discharge loop is provided, PWM output voltage can be rapidly charged and discharged to 1/2Vdc in dead time through reasonably designing the parallel resistance, the difference between the output voltage of the inverter and the output voltage of a single tube during the on/off period is constructed, and the dead time can be detected.

As an example, as shown in fig. 5, fig. 5 is a schematic diagram of a one-phase charging and discharging process of a no-load inverter during a dead zone, where a on the left side is a schematic diagram of charging and discharging when an up-switch and a down-switch are switched to a dead zone, a right side b is a schematic diagram of charging and discharging when an up-switch and a down-switch are switched to a dead zone, a dotted line in the diagram represents a current path in a non-dead zone time, a dotted line represents a current path in a dead zone time, and Vph represents an output. It is also easy to understand that the capacitance connected in parallel with the switch tube in fig. 5 is not the newly added capacitance, but represents the output capacitance of the switch tube.

Fig. 6 is a schematic diagram of the output voltage of one phase bridge arm varying with the switching signal. By adding the parallel resistor on the direct current side to provide a charge and discharge loop for the IGBT output capacitor of the inverter, there are three possible results of the charge and discharge process, as shown in fig. 6: the method comprises the following steps of firstly representing that charging and discharging are complete in a dead zone period, secondly representing that charging and discharging are just completed in the dead zone period, and thirdly representing that charging and discharging are incomplete in the dead zone period. In addition, S1 and S2 in the figure respectively represent two switching tubes, and Tdt represents dead time.

The situation is that the parallel resistance is small, so that the charging and discharging time constant is small, and the charging and discharging process can be completed before the dead zone is finished; the second case is that the charging and discharging time constant just enables the charging and discharging process to be completed at the dead zone ending time; the situation (c) is that the parallel resistance is large, resulting in a large charging and discharging time constant, and the charging and discharging process cannot be completed in time before the dead zone is finished.

The charging and discharging process of the dead zone state can be controlled to be the first condition by reasonably designing the parallel resistance value, and the difference between the dead zone state and the on/off state is established. The parallel resistance value can be selected according to a time constant τ formed by the output capacitor C and the parallel resistor R, for example, a dead time with τ being 1/10 is set to determine the magnitude of the parallel resistance value.

In other words, in this embodiment or some other embodiments of the present application, the resistance values of the first resistor and/or the second resistor may be determined as follows:

determining a time constant tau according to the dead time of the inverter and a preset proportional relation, wherein the time constant tau is the time constant tau of the charge-discharge loop;

and determining the resistance value according to the time constant tau and the output capacitor so as to enable the charge-discharge loop to complete the charge-discharge process within the dead time of the inverter.

As an example, the preset proportional relationship may be:

the time constant τ is 1/10 of the inverter dead time.

The technical scheme of the embodiment not only enlarges the testing range of hardware-in-the-loop simulation by directly sampling the output PWM voltage of the inverter, better approaches to the real situation, and has better application prospect and practical significance, but also more importantly, solves the problem of difficult dead zone detection caused by no output current when the inverter is in no load through the charging and discharging branch, namely, the difference between the output voltage of the inverter and the output voltage of a single tube during the on/off period of the inverter under the fully-off state of upper and lower tubes of the same bridge arm during the dead zone period is constructed, so that the PWM voltage sampling during the dead zone period can be detected, and the precision of the PWM voltage sampling is improved. Meanwhile, the optical coupling branch circuit solves the isolation problem caused by the rise of the voltage grade due to the fact that the mode of directly sampling the PWM voltage output by the inverter is adopted to enlarge the test range of hardware-in-loop simulation.

In addition, in this embodiment or some other embodiments of the present application, the first resistor and/or the second resistor may specifically be a resistor network, where the resistor network includes a plurality of resistors connected in series and parallel.

This is because in the case of fig. 6, the parallel resistor has a small resistance value in a general state, and there is a risk of heat generation and the like, and therefore, the problem can be solved by adopting a manner that a resistor network is equivalent to the same resistance value.

As an example, as shown in fig. 7, a resistor network 301 a' is used to make a resistor equivalent to an original resistor 301a in a series-parallel manner, so as to solve the heat dissipation risk caused by too small resistance of the parallel resistor 301a of the charge and discharge branch. Alternatively, 301a may be replaced by a resistor that is resistant to heat.

In addition, a voltage threshold range can be provided through the clamping branch circuit to filter noise of the sampling signal, and accuracy of dead time detection is further improved. Therefore, in this embodiment or some other embodiments of the present application, the apparatus may further include:

the clamping branch comprises a clamping diode connected with the light emitting diode of the optical coupling circuit in parallel, and the clamping branch is used for providing a voltage threshold range to filter noise of a sampling signal.

For example, the clamping diode may be specifically a zener diode.

As an example, see fig. 8 and 9, in fig. 8, 303 is a clamping branch, and in fig. 9, 303a is a clamping diode.

Referring to fig. 9, fig. 9 is a partial view of fig. 8 relating to a light emitting diode and a clamping diode, and it is easy to understand that in practical application, resistances such as r1 and r2 (in the figure, r1 is connected in series with the light emitting diode) may be flexibly added for the purposes of protection, current limiting, and the like, and thus, details thereof are not repeated.

In this embodiment or some other embodiments of the present application, the clamping voltage value of the clamping diode is determined by:

and determining the clamping voltage value according to the noise quality of the sampling signal, wherein the upper limit of the voltage threshold range is below the high level of the voltage generated by the switching tube and is a first specified distance away from the high level, and the lower limit of the voltage threshold range is above the low level of the voltage generated by the switching tube and is a second specified distance away from the low level.

As an example, as shown in fig. 9, since the clamping diode may be a zener diode, which has a characteristic of voltage stabilization, that is, when the reverse bias voltage of the diode is greater than a certain value, the clamping voltage of the diode does not increase, it is necessary to ensure that the bridge arm output voltage is higher than the clamping voltage value of the clamping diode 303b, the light emitting diode 302b is turned on, the bridge arm output voltage is lower than the clamping voltage value of the clamping diode 303a, and the light emitting diode 302a is turned on. Thereby constructing a threshold range. The first designated distance and the second designated distance may be the same or different, and are determined by the property of the selected zener diode, and the distance value may be, for example, 1 to 2V.

As an example, see fig. 6, in fig. 6, a horizontal dotted line H represents a high threshold, i.e., an upper limit of a voltage threshold range, and a horizontal dotted line L represents a low threshold, i.e., a lower limit of the voltage threshold range. Usually, a margin of about 1-2V is left between the voltage threshold range and the high and low levels.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.