阅读说明：本技术 一种栅极驱动电路 (Grid driving circuit ) 是由 谭在超 涂才根 张胜 罗寅 丁国华 于 2021-01-21 设计创作，主要内容包括：本发明公开了一种栅极驱动电路,包括左侧电路和驱动电路,左侧电路包括高压电源VCC、Q1三级管、Q2三极管、d1二极管、dz1齐纳二极管、dz2齐纳二极管、dz3齐纳二极管、C1电容、I1偏置电流源、I2偏置电流源、N1MOS管、N2MOS管、N3MOS管以及N4MOS管,驱动电路包括INV1驱动器,INV1驱动器连接INV2驱动器,INV2驱动器连接HN1驱动管,HN1驱动管的漏极连接HP3驱动管的源极,HP3驱动管的漏极连接HP1驱动管的源极和HP2驱动管的栅极,HP2驱动管的源极连接HP4驱动管的漏极,HP4驱动管的源极连接HN2驱动管的漏极,HP4驱动管的漏极连接HP1驱动管的栅极,HN1驱动管、HN2驱动管、HP1驱动管、HP2驱动管、HP3驱动管以及HP4驱动管构成电平位移电路,本驱动电路可以保证即使在薄栅氧工艺中,也能够安全地工作。(The invention discloses a grid driving circuit, which comprises a left side circuit and a driving circuit, wherein the left side circuit comprises a high-voltage power supply VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 zener diode, a dz2 zener diode, a dz3 zener diode, a C1 capacitor, an I1 bias current source, an N1MOS (metal oxide semiconductor) transistor, an N2MOS transistor, an N3MOS transistor and an N4MOS transistor, the driving circuit comprises an INV1 driver, the INV1 driver is connected with the HN1 driving transistor, the drain electrode of the HN1 driving transistor is connected with the source electrode of the HP1 driving transistor, the source electrode of the HP1 driving transistor is connected with the drain electrode of the HP1 driving transistor, the drain electrode of the HP1 driving transistor is connected with the HP driving transistor, the HP1 driving transistor, the HP driving transistor and the HP driving transistor 72 driving transistor are connected with the level of the HP driving transistor, the HP driving transistor and the HP driving transistor is formed by the level of the driving transistor 1 and the HP driving transistor, the driving circuit can ensure safe operation even in a thin gate oxide process.)

1. A gate driving circuit, comprising a left side circuit and a driving circuit, wherein the left side circuit comprises a high voltage power VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 Zener diode, a dz2 Zener diode, a dz3 Zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1MOS transistor, an N2MOS transistor, an N3MOS transistor and an N4MOS transistor, the I1 bias current source is connected with the drain of the N1MOS transistor, the I2 bias current source is connected with the base of the Q1 triode, the gate of the N1MOS transistor is connected with the gate of the N2MOS transistor, the drain and gate of the N1MOS transistor are connected with the gate of the N2MOS transistor, the d 7378 diode and the dz1 Zener diode are connected with the base of the Q1 triode, the emitter of the Q1 triode is connected with the base of the Q2 triode and the drain of the N2MOS transistor, the emitter of the Q2 MOS transistor is connected with VCC and the output of a high voltage power diode 1 and a Zener 1 diode are connected with the high voltage power L and the Zener 464 MOS transistor, the driving circuit comprises an INV1 driver, the INV1 driver is connected with the INV1 driver, the INV1 driver is connected with an HN1 driving tube, the drain electrode of the HN1 driving tube is connected with the source electrode of the HP1 driving tube, the drain electrode of the HP1 driving tube is connected with the grid electrode of the HP1 driving tube, the source electrode of the HP1 driving tube is connected with the drain electrode of the HP1 driving tube, the drain electrode of the HP1 driving tube is connected with the grid electrode of the HP1 driving tube, the HN1 driving tube, the HP1 driving tube and the HP1 driving tube form a level shift circuit, the level shift circuit is connected with the grid electrode of the HP1 driving tube, the source electrode of the HP1 driving tube is connected with the drain electrode of the HP1 driving tube, the drain electrode of the HN1 driving tube, the HP1 driving tube, and the grid electrode of the HP1 driving tube are connected with the HN1 driving tube, and the drain electrode of the HP1 driving tube is connected with the HN1 driving tube, and the HP1 driving tube, and the grid electrode of, the INV1 driver is connected with the INV3 driver, and the INV3 driver is connected with the grid electrode of the HN3 driving tube.

2. The gate driver circuit of claim 1, wherein the gates of the HP3, HP4, and HP6 driver tubes are tied to a VDDH high voltage signal.

3. The gate driving circuit of claim 2, wherein the drains of the HP1, HP2, HP5 and HP7 driving tubes are connected, and the sources of the HN1, HN2 and HN3 driving tubes are connected.

4. The gate drive circuit of claim 3, further comprising an INV4 driver, an INV5 driver, an INV6 driver and an INV7 driver, the INV1 driver being connected in sequence with the INV4 driver, the INV5 driver, the INV6 driver and the INV7 driver, the INV7 driver being connected to the gate of the HN4 drive tube.

5. The gate drive circuit of claim 4, wherein the INV 1-INV 7 drivers are low voltage drivers with a power supply of VDDL.

Technical Field

The invention relates to the technical field of switching power supply circuits, in particular to a grid driving circuit.

Background

In the topology of the switching power supply, there is a power switch tube, so called as a switching power supply, however, the power switch tube needs a driving circuit to control its switch, usually the driving circuit is integrated in the control IC, when the IC is designed, usually the working voltage of its power pin is between 10V to 30V, on one hand, the higher power supply voltage ensures that the driving capability of the IC is strong, on the other hand, the wider working voltage interval can ensure that the IC can be more suitable for various working environments, and has stronger adaptability, however, in the IC design, a low voltage internal power supply (e.g. 5V) is usually designed, and a large number of low voltage tubes can be adopted inside the IC by adopting the low power supply design, so the integration level of the IC can be greatly improved, which is a development trend of the IC design, a typical driving circuit structure inside the IC is shown in fig. 1, P1/N1 is a low voltage tube, HN1 to HN6, HP 1-HP 6 are high-voltage tubes, DRV signals are low-voltage driving signals after logic processing inside an IC, Gate signals are driving output signals of the IC, VDD is a low-voltage power supply inside the IC, VCC is a high-voltage power supply of an IC pin, N1/P1/HN1/HN2/HP1/HP2 form a level shift circuit, the DRV signal of low level can be converted into high level signal, the driving capability is enhanced step by step through the driving circuit of the rear 4 groups of driver structures, and finally the output signal gate with stronger driving capability is obtained, of course, some structures can be improved, dead time is designed for the driving tube HP6/HN6 of the last stage, the HP6 and HN6 are prevented from being conducted simultaneously and damaged, but the core thought is in the structural framework, the application premise of the driving structure is that the high-voltage tube not only can bear high voltage at a drain-source end (Vds), but also can bear high voltage at a gate-oxide end (Vgs) without damage. In a large number of process procedures, a photolithography plate is usually added to simultaneously realize thick gate oxide and thin gate oxide, the withstand voltage of the thick gate oxide is higher, and the thick gate oxide design is adopted in a high-voltage tube, so that the gate oxide can be well protected from breakdown, and thus, the driving structure can be largely adopted, however, in some process procedures with smaller size, such as 0.18um process, many fabs do not provide the selection of the thick gate oxide and the thin gate oxide, and only provide the thin gate oxide, if the driving circuit is continuously adopted, the high-voltage tube is damaged due to insufficient withstand voltage of the gate oxide.

Disclosure of Invention

In order to solve the above problems, the present invention provides a gate driving circuit, which can ensure safe operation even in a thin gate oxide process, the circuit includes a left side circuit and a driving circuit, the left side circuit generates a low voltage power supply VDDL and a high voltage signal VDDH, the right side portion is the driving circuit, VCC is the high voltage power supply and supplies power to the left and right side circuits, the left side circuit includes a high voltage power supply VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 zener diode, a dz2 zener diode, a dz3 zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1MOS transistor, an N2MOS transistor, an N3MOS transistor and an N4MOS transistor, the I1 bias current source is connected to the drain of the N1MOS transistor, the I1 bias current source provides bias current for the N1MOS transistor, the I2 bias current source is connected to the base of the Q1 triode, the gate of the N1MOS transistor is connected to the gate of the N2MOS transistor, the drain of the N1MOS transistor is connected to, the d1 diode and dz1 Zener diode are connected with the base of the Q1 triode, the emitter of the Q1 triode is connected with the base of the Q2 triode and the drain of the N2MOS tube, the emitter of the Q2 triode is connected with the drain output VDDL of the N3MOS tube, VDDL has a Zener diode dz2 Zener diode to the ground, which does not break down normally and plays a role of protection, the drain of the N4MOS tube is connected with the high voltage power VCC through the dz3 Zener diode and the C1 capacitor, the driving circuit comprises an INV1 driver, the INV1 driver is connected with an INV2 driver, the INV2 driver is connected with an HN1 driving tube, the drain of the HN1 driving tube is connected with the source of the HP3 HP driving tube, the drain of the HP3 driving tube is connected with the source of the HP1 driving tube and the gate of the HP2 driving tube, the source of the HP2 driving tube is connected with the HP2 driving tube, the drain of the HP2 driving tube is connected with the HN2, the HN2 and the gate of the HN2 driving, The high-voltage power supply comprises an HP1 driving tube, an HP2 driving tube, an HP3 driving tube and an HP4 driving tube which form a level shift circuit, the output of the level shift circuit is connected with a grid electrode of the HP5 driving tube, the source electrode of the HP5 driving tube is connected with the drain electrode of the HP6 driving tube, the source electrode of the HP6 driving tube is connected with the drain electrode of the HN3 driving tube, the HN3 driving tube, the HP6 driving tube and the HP5 driving tube form a driver, the output voltage is connected with the grid electrode of the HP7 driving tube, the HN4 driving tube is driven in a step-by-step amplification mode through INV 4-INV 7 drivers, the source electrode of the HP7 driving tube is connected with the drain electrode of the HN4 driving tube, the INV1 driver is connected with an INV3 driver, the INV.

As an improvement of the invention, the N1MOS tube, the N2MOS tube, the N3MOS tube and the N4MOS tube form a current mirror, and the Q1 triode and the Q2 triode form a power supply structure with stronger current capability.

As a modification of the invention, the gates of the HP3 driving tube, the HP4 driving tube and the HP6 driving tube are connected with VDDH high voltage signals.

As a modification of the invention, the drains of the HP1 driving tube, the HP2 driving tube, the HP5 driving tube and the HP7 driving tube are connected, and the sources of the HN1 driving tube, the HN2 driving tube and the HN3 driving tube are connected.

As an improvement of the invention, the circuit further comprises an INV4 driver, an INV5 driver, an INV6 driver and an INV7 driver, wherein the INV1 driver is sequentially connected with the INV4 driver, the INV5 driver, the INV6 driver and the INV7 driver, the INV7 driver is connected with a grid electrode of the HN4 driving tube, and the INV 4-INV 7 drivers have a step-by-step driving enhancement effect.

As an improvement of the present invention, the INV 1-INV 7 drivers are low voltage drivers, and the power source thereof is VDDL.

The invention has the beneficial effects that: the gate source voltage of the MOS device in the gate drive circuit provided by the invention does not exceed 4.8V, the requirement on the withstand voltage of gate oxide is not high, the MOS device can work safely even in a thin gate oxide process, the MOS device is very suitable for processes without gate oxide thickness selection, and the application prospect of the drive circuit structure provided by the invention is continuously good along with the continuous reduction of the photoetching size.

Drawings

Fig. 1 is a structural diagram of a conventional driving circuit described in the background art.

Fig. 2 is a structural diagram of a gate driving circuit described in the present invention.

Fig. 3 is a left side circuit configuration diagram described in the present invention.

Fig. 4 is a structural diagram of a driving circuit described in the present invention.

Detailed Description

The present invention will be further illustrated with reference to the accompanying figures 2 to 4 and the following detailed description, which should be understood to illustrate the invention only and not to limit the scope of the invention.

Example (b): the circuit comprises a left side circuit and a driving circuit, wherein the left side circuit generates a low-voltage power supply VDDL and a high-voltage signal VDDH, the right side circuit is a driving circuit, VCC is a high-voltage power supply and supplies power to the left and right side circuits, the left side circuit comprises a high-voltage power supply VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 zener diode, a dz2 zener diode, a dz3 zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1MOS transistor, an N2MOS transistor, an N3MOS transistor and an N4MOS transistor, an I1 bias current source is connected with the drain electrode of the N1MOS transistor, an I1 bias current source provides bias current for the N1MOS transistor, an I2 bias current source is connected with the base electrode of the Q1 triode, the grid electrode of the N1MOS transistor is connected with the grid electrode of the N2MOS transistor, the drain electrode and the grid electrode of the N2MOS transistor are connected, a d1 diode and a dz1 zener diode are connected with the base electrode of the Q1 triode, and the emitter of, the emitter of the Q2 triode is connected with the drain output VDDL of the N3MOS tube, VDDL has a zener diode dz2 to the ground, normally does not break down and plays a role of protection, the drain of the N4MOS tube is connected with a high voltage power VCC through a dz3 zener diode and a C1 capacitor, the driving circuit comprises an INV1 driver, an INV1 driver is connected with an INV2 driver, an INV2 driver is connected with an HN1 driving tube, the drain of the HN1 driving tube is connected with the source of an HP3 driving tube, the drain of the HP3 driving tube is connected with the source of an HP1 driving tube and the gate of an HP1 driving tube, the source of the HP1 driving tube is connected with the drain of the HP1 driving tube, the drain of the HP1 driving tube is connected with the gate of the HP1 driving tube, the HN1 driving tube, the drain of the HN1 driving tube, the HP1 and the source of the HP1 are connected with the drain of the HP1, and the gate of the HP1 are connected with the HP1, the drain of the HP1, the, the source electrode of the HP6 driving tube is connected with the drain electrode of the HN3 driving tube, the HN3 driving tube, the HP6 driving tube and the HP5 driving tube form a driver, the output voltage is connected with the grid electrode of the HP7 driving tube, the HN4 driving tube is driven by a multi-stage driver in a step-by-step amplification mode, the source electrode of the HP7 driving tube is connected with the drain electrode of the HN4 driving tube, the INV1 driver is connected with the INV3 driver, the INV3 driver is connected with the grid electrode of the HN3 driving tube, DRV is a low-voltage driving signal, and Gate is a.

The circuit comprises an N1MOS tube, an N2MOS tube, an N3MOS tube and an N4MOS tube which form a current mirror, a Q1 triode and a Q2 triode form a power supply mechanism with stronger current capacity, the grids of the HP3 driving tube, the HP4 driving tube and the HP6 driving tube are connected with VDDH high-voltage signals, the drains of the HP1 driving tube, the HP2 driving tube, the HP5 driving tube and the HP7 driving tube are connected, the sources of the HN1 driving tube, the HN2 driving tube and the HN3 driving tube are connected, the circuit further comprises an INV4 driver, an INV5 driver, an INV6 driver and an INV7 driver, the INV1 driver is sequentially connected with the INV4 driver, the INV5 driver, the INV6 driver and the INV7 driver, the INV7 driver is connected with the grid of the HN4 driving tube, the INV 1-INV 7 driver is a low-voltage.

The working principle is as follows: left circuit: the base voltage of the Q1 triode is clamped at Vdz + Vd1, about 6.2V, so that the generated low-voltage power supply VDDL is Vdz + Vd1-2Vbe, about 4.8V; and the generated high voltage signal VDDH is VCC-Vdz, i.e. VDDH always maintains a level 5.5V lower than VCC.

The right circuit: when DRV is high level, the gate voltage of HN1 driving transistor is VDDL (4.8V), the gate voltage of HN2 driving transistor is 0V, the source terminal voltage of HP3 driving transistor is pulled down to VDDH + VSG _ HP3, where VSG _ HP3 is the threshold voltage of HP3 driving transistor, which is about 0.7V, and for HP2 driving transistor, the gate source voltage is VCC-VDDH-VSG _ HP3, which is about 4.8V, and similarly, when DRV is low level, the gate voltage of HN1 driving transistor is 0V, the gate voltage of HN2 driving transistor is VDDL (4.8V), the gate source voltage of HP1 driving transistor is also 4.8V, when DRV is high level, the gate voltage of HN3 driving transistor is 4.8V, the gate voltage of HP 36 driving transistor is VDDL (4.8V), the gate voltage of HP6 driving transistor is VCC + VSG 6, the source terminal voltage of HP 368938 is conductive gate source voltage of HP 36898V; and the Gate voltage of the HN4 driving tube is 0V, the output Gate of the driving circuit is high level VCC, and similarly, when DRV is low level, the Gate-source voltage of the HP7 driving tube is 0V, the Gate voltage of the HN4 driving tube is VDDL (4.8V), and the output Gate of the driving circuit is 0V.

In the description of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for convenience of describing the present invention and simplifying the description, rather than to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting, and unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection, or integrally connected, mechanically or electrically, directly or indirectly through intervening media, or through both elements, the specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various modifications can be made to the embodiments described in the foregoing embodiments, or some or all of the technical features of the embodiments can be equivalently replaced, and the modifications or the replacements do not make the essence of the corresponding technical solutions depart from the scope of the embodiments of the present invention.