阅读说明：本技术 功率变换器 (Power converter ) 是由 张望 赵晨 于 2020-12-25 设计创作，主要内容包括：公开了一种功率变换器。该功率变换器在实现高电压变换比的基础上,避免了在电流断续模式下出现负电流的情况,使得功率变换器在轻载下能够正常工作,从而提高变换器的效率和可靠性。(A power converter is disclosed. On the basis of realizing high voltage conversion ratio, the power converter avoids the condition of negative current in a current interrupted mode, so that the power converter can normally work under light load, and the efficiency and the reliability of the converter are improved.)

1. A power converter, comprising:

at least one first power stage circuit; and

a second power stage circuit, wherein a first terminal of said second power stage circuit is coupled to an adjacent first power stage circuit, wherein each of said first power stage circuits comprises:

at least one power tube is used as a main power tube;

a first energy storage element configured to be coupled in common with an adjacent power stage circuit at a first node in the first power stage circuit and to be charged or discharged via the adjacent power stage circuit; and

an auxiliary module configured such that a current flowing through a first magnetic element in the first power stage circuit is not less than zero in a current chopping mode.

2. The power converter of claim 1, wherein the first magnetic element is coupled between the auxiliary module and the second end of the first power stage circuit.

3. The power converter of claim 1, wherein the auxiliary module is configured to cause the current of the first magnetic element to flow through the auxiliary module to the output of the power converter during a first operating phase, and to provide a charging or discharging loop for the first energy storage element during a second operating phase to avoid a current reversal of the first magnetic element.

4. The power converter of claim 1, wherein the auxiliary module is connected between the second end of the first energy storage element and the first end of the first magnetic element.

5. The power converter of claim 4, wherein the auxiliary module comprises a first power transistor and a second power transistor, wherein the first power transistor is connected between the second terminal of the first energy storage element and a ground reference, the second power transistor is connected between the second terminal of the first energy storage element and the first terminal of the first magnetic element, and the first terminal of the first energy storage element is connected to the first node.

6. The power converter according to claim 5, wherein the conduction interval of the first power transistor in the current first power stage circuit overlaps with at least the conduction interval of the power transistor or the rectifier transistor connected to the first terminal of the next adjacent power stage circuit, and the conduction interval of the second power transistor overlaps with at least the conduction interval of the power transistor or the rectifier transistor connected to the first terminal of the current power stage circuit.

7. The power converter according to claim 6, wherein the maximum on time of the first power transistor is an off time of a power transistor or a rectifier connected to the first terminal of the current power stage circuit, and the maximum on time of the second power transistor is an off time of the first power transistor.

8. The power converter of claim 1, wherein each power stage circuit further comprises a rectifier tube, wherein the rectifier tube is a synchronous rectifier power tube or a rectifier diode.

9. The power converter of claim 8, wherein the main power transistor of each of the first power stage circuits is connected between the first terminal of the current first power stage circuit and a first node, and the rectifier transistor of each of the first power stage circuits is connected between the first terminal of the first magnetic element and a ground reference.

10. The power converter of claim 8, wherein the rectifier tube of each of the first power stage circuits is connected between the first terminal of the current first power stage circuit and a first node, and the main power tube of each of the first power stage circuits is connected between the first terminal of the first magnetic element and a reference ground.

11. The power converter of claim 9 or 10, wherein when the power converter is in a current continuous mode, the main power transistor and the rectifier transistor of the at least one first power stage circuit are in complementary conduction; when the power converter is in a current interruption mode, the rectifier tubes in the at least one first power stage circuit are turned on when the corresponding main power tube is turned off and turned off when the current flowing through the first magnetic element crosses zero.

12. The power converter of claim 1, wherein the second power stage circuit comprises a switching power stage circuit, wherein the switching power stage circuit comprises a main power transistor, a rectifier transistor, and a second magnetic element to form a buck or boost power stage circuit.

13. The power converter of claim 12, wherein the first terminal of a first one of the first power stage circuits is connected to the first terminal of the power converter, the first terminal of each of the other first power stage circuits is connected in turn to the first node of the immediately preceding adjacent first power stage circuit, the first terminal of the second power stage circuit is coupled to the first node of the last first power stage circuit, and the second terminals of the at least one first and second power stage circuits are connected in parallel.

14. The power converter of claim 1, wherein the main power transistors of the at least one first and second power stage circuits are sequentially switched in phase-staggered fashion, and are out of phase by less than 360 °/N, where N is the total number of the first and second power stage circuits.

15. The power converter according to claim 1, wherein when the power converter comprises (N-1) first power stage circuits and a second power stage circuit, the driving signals of the main power transistors in the (2j-1) th power stage circuit are the same, the driving signals of the main power transistors in the 2j power stage circuit are the same, and the phase difference between the driving signals is 180 °, wherein j and N are positive integers, N is greater than or equal to 2, and j is less than or equal to (N + 1)/2.

16. The power converter of claim 1, wherein the conduction time of a main power tube in the at least one first power stage circuit and the second power stage circuit is the same and the output voltage of the power converter is adjusted by adjusting the duty cycle of the main power tube.

17. The power converter of claim 1, wherein the switching frequency of the power converter is fixed and the output voltage of the power converter is adjusted by adjusting the on-time of the main power transistor in the at least one first power stage circuit and the second power stage circuit.

18. The power converter of claim 1, wherein the conduction time of the main power transistor in the at least one first power stage circuit and the second power stage circuit is fixed, and the output voltage of the power converter is adjusted by adjusting the switching frequency of the power converter.

19. The power converter of claim 1, wherein a first terminal of a first one of the first power stage circuits is configured as an input terminal of the power converter to receive an input voltage, and wherein a second terminal of the at least one of the first power stage circuit and the second power stage circuit is configured in parallel as an output terminal of the power converter to generate an output voltage; or the second ends of the at least one first power stage circuit and the second power stage circuit are connected in parallel to serve as the input end of the power converter to receive the input voltage, and the first end of the first power stage circuit serves as the output end of the power converter to generate the output voltage.

20. A power converter according to claim 12, wherein the first magnetic element and/or the first and second magnetic elements are coupled to each other.

Technical Field

The invention relates to the technical field of power electronics, in particular to a power converter.

Background

With the continuous development of power electronics technology, high-gain power converters have become an indispensable part in energy utilization. A hybrid power converter is known in the art that can achieve high voltage conversion ratios. As shown in fig. 1, the power converter includes a first power stage circuit and a second power stage circuit, wherein the first power stage circuit includes a main power transistor Q1, a capacitor Cf, a rectifier tube Qsr1 and an inductor Lo1, the second power stage circuit includes a buck circuit composed of a main power transistor Q2, a rectifier tube Qsr2 and an inductor Lo2, and an input terminal of the second power stage circuit is connected to a common point of the main power transistor Q1 and the capacitor Cf. In addition to being turned on when the main power transistor Q1 is turned off to provide a freewheeling circuit for the inductor Lo1, the rectifier Qsr1 is also turned on during the period when the main power transistor Q2 is turned on to provide a discharge circuit for the capacitor Cf to provide energy as an input source for the second power stage circuit. In addition, when the rectifier tubes Qsr1 and Qsr2 are replaced with rectifier diodes, a negative current or a circuit that cannot operate normally also occurs in the discontinuous mode.

Fig. 2 is a waveform diagram showing the operation of a high conversion ratio power converter in a discontinuous mode in the prior art. As shown in fig. 2, when the power converter operates in the current interruption mode, since the main power transistor Q2 is turned on and the rectifier Qsr1 must be turned on, the inductor current iLo1 will have a negative current, as shown by the waveform in the dashed line. The negative current will reduce the efficiency of the converter, and in addition, the voltage of the capacitor Cf will deviate from 1/2Vin, so that the two paths of inductor currents are unbalanced, which is not favorable for the reliable operation of the converter.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a power converter, so as to avoid a negative current in a current interruption mode on the basis of realizing a high voltage conversion ratio, so that the power converter can normally operate under a light load, thereby improving the efficiency and reliability of the converter.

The power converter provided by the invention comprises:

at least one first power stage circuit; and

a second power stage circuit, wherein a first terminal of said second power stage circuit is coupled to an adjacent first power stage circuit, wherein each of said first power stage circuits comprises:

at least one power tube is used as a main power tube;

a first energy storage element configured to be coupled in common with an adjacent power stage circuit at a first node in the first power stage circuit and to be charged or discharged via the adjacent power stage circuit; and

an auxiliary module configured such that a current flowing through a first magnetic element in the first power stage circuit is not less than zero in a current chopping mode.

Specifically, the first magnetic element is coupled between the auxiliary module and the second end of the first power stage circuit.

Specifically, the auxiliary module is configured to enable the current of the first magnetic element to flow to the output end of the power converter through the auxiliary module in a first operation stage, and provide a charging or discharging loop for the first energy storage element in a second operation stage so as to avoid the current reversal of the first magnetic element.

In particular, the auxiliary module is connected between the second end of the first energy storage element and the first end of the first magnetic element.

Specifically, the auxiliary module comprises a first power tube and a second power tube, wherein the first power tube is connected between the second end of the first energy storage element and the reference ground, the second power tube is connected between the second end of the first energy storage element and the first end of the first magnetic element, and the first end of the first energy storage element is connected with the first node.

Specifically, in the current first power stage circuit, the conduction interval of the first power tube at least overlaps with the conduction interval of the power tube or the rectifier tube connected to the first end of the next adjacent power stage circuit, and the conduction interval of the second power tube at least overlaps with the conduction interval of the power tube or the rectifier tube connected to the first end of the current power stage circuit.

Specifically, the maximum on time of the first power tube is the off time of the power tube or the rectifier tube connected to the first end of the current power stage circuit, and the maximum on time of the second power tube is the off time of the first power tube.

Specifically, each power stage circuit further comprises a rectifier tube, wherein the rectifier tube is a synchronous rectification power tube or a rectification diode.

Specifically, the main power tube in each first power stage circuit is connected between the first end of the current first power stage circuit and the first node, and the rectifier tube in each first power stage circuit is connected between the first end of the first magnetic element and the reference ground.

Specifically, the rectifier tube in each first power stage circuit is connected between the first end of the current first power stage circuit and the first node, and the main power tube in each first power stage circuit is connected between the first end of the first magnetic element and the reference ground.

Specifically, when the power converter is in a current continuous mode, a main power tube and a rectifier tube in the at least one first power stage circuit are conducted complementarily; when the power converter is in a current interruption mode, the rectifier tubes in the at least one first power stage circuit are turned on when the corresponding main power tube is turned off and turned off when the current flowing through the first magnetic element crosses zero.

Specifically, the second power stage circuit comprises a switch-type power stage circuit, wherein the switch-type power stage circuit comprises a main power tube, a rectifying tube and a second magnetic element to form a buck or boost power stage circuit.

Specifically, the first end of the first power stage circuit is connected to the first end of the power converter, the first end of each of the other first power stage circuits is connected to the first node of the last adjacent first power stage circuit, the first end of the second power stage circuit is coupled to the first node of the last first power stage circuit, and the second ends of the at least one first power stage circuit and the second power stage circuit are connected in parallel.

Specifically, the main power tubes in the at least one first power stage circuit and the second power stage circuit are sequentially conducted in a phase-staggered mode, and the phase difference of the phase-staggered mode is smaller than 360 degrees/N, wherein N is the total number of the first power stage circuit and the second power stage circuit.

Specifically, when the power converter comprises (N-1) first power stage circuits and a second power stage circuit, the driving signals of the main power tubes in the (2j-1) th power stage circuit are the same, the driving signals of the main power tubes in the 2j power stage circuit are the same, and the phase difference between the driving signals of the two is 180 degrees, wherein j and N are positive integers, N is larger than or equal to 2, and j is smaller than or equal to (N + 1)/2.

Specifically, the conduction time of a main power tube in the at least one first power stage circuit and the second power stage circuit is the same, and the output voltage of the power converter is adjusted by adjusting the duty ratio of the main power tube.

Specifically, the switching frequency of the power converter is fixed, and the output voltage of the power converter is adjusted by adjusting the conduction time of a main power tube in the at least one first power stage circuit and the second power stage circuit.

Specifically, the conduction time of a main power tube in the at least one first power stage circuit and the second power stage circuit is fixed, and the output voltage of the power converter is adjusted by adjusting the switching frequency of the power converter.

Specifically, a first end of a first power stage circuit is used as an input end of the power converter to receive an input voltage, and second ends of the at least one first power stage circuit and the second power stage circuit are connected in parallel to be used as output ends of the power converter to generate an output voltage; or the second ends of the at least one first power stage circuit and the second power stage circuit are connected in parallel to serve as the input end of the power converter to receive the input voltage, and the first end of the first power stage circuit serves as the output end of the power converter to generate the output voltage.

In particular, the first magnetic elements are coupled to each other and/or the first and second magnetic elements are coupled to each other.

In summary, the power converter of the present invention avoids the negative current in the discontinuous current mode on the basis of realizing the high voltage conversion ratio, so that the power converter can normally operate under light load, thereby improving the efficiency and reliability of the converter.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a high conversion ratio power converter of the prior art;

FIG. 2 is a waveform diagram illustrating operation of a high conversion ratio power converter in a discontinuous mode according to the prior art;

FIG. 3 is a circuit diagram of a power converter according to a first embodiment of the present invention;

FIG. 4 is a first waveform illustrating operation of a power converter in accordance with a first embodiment of the present invention;

FIG. 5 is a waveform illustrating a second operation of the power converter according to the first embodiment of the present invention;

FIG. 6 is a circuit diagram of a power converter in accordance with a second embodiment of the present invention;

FIG. 7 is a circuit diagram of a power converter according to a third embodiment of the present invention;

FIG. 8 is a waveform illustrating a first operation of a power converter according to a third embodiment of the present invention; and

fig. 9 is a waveform illustrating a second operation of a power converter according to a third embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 3 is a circuit diagram of a power converter according to a first embodiment of the present invention. As shown in fig. 3, the power converter includes a first power stage circuit 1 and a second power stage circuit 2, wherein a first terminal of the second power stage circuit 2 is coupled to the adjacent first power stage circuit 1. In the present embodiment, the first terminal of the second power stage circuit 2 is connected to the first node a of the first power stage circuit 1, and the second terminals of the first power stage circuit 1 and the second power stage circuit 2 are connected together. The first terminal of the power converter is taken as an input terminal, and the second terminal is taken as an output terminal. Specifically, the first terminal of the first power stage circuit 1 is a first terminal i of the power converter, where the first terminal is an input terminal of the power converter to receive the input voltage Vin, and the second terminals of the first power stage circuit 1 and the second power stage circuit 2 are connected in parallel as a second terminal o of the power converter, where the second terminal is an output terminal of the power converter to generate the output voltage Vout.

Specifically, the first power stage circuit 1 includes a power transistor Q1 (i.e. the main power transistor of the first power stage circuit 1) connected between a first terminal i and a first node a; a first energy storage element, here a capacitor Cf, coupled in common with an adjacent power stage circuit (i.e. the second power stage circuit 2) at the first node a, and configured to discharge via the second power stage circuit 2; and an auxiliary module 11 configured such that the current flowing through the first magnetic element in the first power stage circuit 1 is not less than zero in the current interruption mode. Wherein the first magnetic element is an inductor Lo1, and is coupled between the auxiliary module 11 and the second terminal of the first power stage circuit 1.

In particular, the auxiliary module 11 in the first power stage circuit 1 is connected between the second terminal of the capacitance Cf and the first terminal of the inductance Lo 1. The auxiliary module 11 is configured to enable the current of the inductor Lo1 to flow to the output terminal o through the auxiliary module 11 in the first operation phase, and to provide a discharge loop for the capacitor Cf in the second operation phase to avoid the current reversal of the inductor Lo 1.

In this embodiment, the auxiliary module 11 includes a first power transistor Qa connected between the second terminal of the capacitor Cf and the reference ground, and a second power transistor Qb connected between the second terminal of the capacitor Cf and the first terminal of the inductor Lo 1. It should be understood that in the first operation phase of the present embodiment, the input voltage Vin stores energy to the capacitor Cf and the inductor Lo1 through the second power transistor Qb, and in the second operation phase, the capacitor Cf discharges to the output terminal through the second power stage circuit 2 and the first power transistor Qa.

In addition, the first power stage circuit 1 further includes a power tube Qsr1 as a rectifying tube connected between the first end of the inductor Lo1 and the reference ground to provide a freewheeling loop for the first power stage circuit. In this embodiment, the presence of the first power transistor Qa provides a discharge circuit for the capacitor Cf, thereby eliminating the need for discharging through the rectifier Qsr1 as in the prior art.

The second power stage circuit 2 comprises a switching type power stage circuit, here a buck power stage circuit. The second power stage circuit 2 comprises in particular a power transistor Q2 as main power transistor and a power transistor Qsr2 as rectifier transistor connected in series between the first terminal of the second power stage circuit 2 and ground, and a second magnetic element, here an inductance Lo2, connected between the output o and an intermediate node of the main power transistor Q2 and the rectifier transistor Qsr 2. In some embodiments, the first magnetic element and the second magnetic element may be coupled to each other.

It should be understood that, since the first terminal i of the power converter is an input terminal and the second terminal o is an output terminal, the capacitor Cf stores energy during a period when the second power transistor Qb is turned on (i.e., a first operation period), and releases energy to the output terminal o as an input source of the second power stage circuit 2 via the second power stage circuit 2 and the first power transistor Qa during a period when the first power transistor Qa is turned on (i.e., a second operation period).

In principle, the first power transistor Qa replaces part of the function of the rectifier Qsr1 in fig. 1, so that the maximum on-time of the first power transistor Qa is the off-time of the main power transistor Q1 connected to the first end of the first power stage circuit 1, that is, the first power transistor Qa and the main power transistor Q1 are complementarily turned on. Meanwhile, the maximum on-time of the second power tube Qb is the off-time of the first power tube Qa, that is, the second power tube Qb and the first power tube Qa are complementarily turned on.

Preferably, the conduction interval of the first power transistor Qa at least overlaps with the conduction interval of the main power transistor Q2 connected to the first end of the next adjacent power stage circuit (i.e., the second power stage circuit 2), that is, when the main power transistor Q2 is in the conduction state, the first power transistor Qa is also in the conduction state, and the conduction time of the first power transistor Qa is equal to or longer than the conduction time of the main power transistor Q2. The conduction interval of the second power tube Qb is at least overlapped with the conduction interval of the main power tube Q1 connected with the first end of the current power stage circuit. That is, when the main power transistor Q1 is in the on state, the second power transistor Qb is also in the on state, and the on time of the second power transistor Qb is equal to or longer than the on time of the main power transistor Q1.

When the duty ratio is less than 0.5, the on-time of the first power transistor Qa is less than the maximum on-time, but is the same as the on-off state of the power transistor Q2, so that when the power transistor Q2 is turned on, a path is provided for the capacitor Cf to discharge through the second power stage circuit to avoid the reverse of the inductor current. The conduction time of the second power transistor Qb is also shorter than the maximum conduction time, but is the same as the switching state of the power transistor Q1, so that when the power transistor Q1 is turned on, a path is provided for the input voltage Vin to store energy for the capacitor Cf and the inductor Lo1, and the current of the inductor Lo1 flows to the output o of the power converter through the auxiliary module 11. It should be understood that the above preferred embodiment is the minimum on-time of the power transistors Qa and Qb, and other switch states between the minimum on-time and the maximum on-time can achieve the function of the auxiliary module, and therefore, are within the protection scope of the present invention.

Fig. 4 shows a first operating waveform diagram of the power converter according to the first embodiment of the present invention, and fig. 5 shows a second operating waveform diagram of the power converter according to the first embodiment of the present invention, all with a duty cycle less than 0.5 as an example. Fig. 4 shows driving signals and inductor current waveforms of the power converter operating in the current continuous mode. Fig. 5 illustrates various drive signals and inductor current waveforms for a power converter operating in a current chopping mode. As can be seen from fig. 4 and 5, the driving signal G1 of the main power transistor Q1 in the first power stage circuit 1 is the same as the driving signal Gb of the second power transistor Qb, and the driving signal G2 of the main power transistor Q2 in the second power stage circuit is the same as the driving signal Ga of the first power transistor Qa in the first power stage circuit 1. In the current continuous mode, the driving signal Gsr1 of the rectifier Qsr1 in the first power stage circuit 1 is complementary to the driving signal G1 of the main power transistor Q1, and the driving signal Gsr2 of the rectifier Qsr2 in the second power stage circuit 2 is complementary to the driving signal G2 of the main power transistor Q2. In the current interrupt mode, the rectifier Qsr1 in the first power stage circuit 1 is turned on when the main transistor Q1 is turned off and turned off when the current iLo1 flowing through the inductor Lo1 crosses zero, while the rectifier Qsr2 in the second power stage circuit 2 is turned on when the main transistor Q2 is turned off and turned off when the current iLo2 flowing through the inductor Lo2 crosses zero. In addition, in the present embodiment, the rectifier tubes Qsr1 and Qsr2 are synchronous rectifier power tubes, and those skilled in the art will appreciate that the rectifier tubes Qsr1 and Qsr2 may be replaced by rectifier diodes, which do not affect the operation of the converter.

In addition, in the present embodiment, the conduction time of the main power transistor Q1 in the first power stage circuit 1 and the conduction time of the main power transistor Q2 in the second power stage circuit 2 are the same, and the conduction time of the two transistors has a certain phase difference, preferably 180 ° (i.e., time difference Ts/2 in the figure). The control circuit in the power converter can adjust the size of the output voltage Vout by changing the duty ratio D of the main power tube in the first and second power stage circuits to generate the desired output voltage.

It should be understood that there are many ways to control the output voltage by varying the duty cycle, for example, the control circuit may regulate the output voltage Vout by adjusting the on-time of the main power transistor in the first and second power stage circuits at a fixed switching frequency. Of course, the control circuit may also keep the on-time of the power transistor in each power stage circuit unchanged, and adjust the output voltage Vout by adjusting the switching frequency of the power converter. In addition, other control methods for controlling the power converter in the prior art may also be applied to the present embodiment, and are not limited herein.

The operation of the first power converter of the embodiment of the present invention is explained in detail below. When the power converter operates in the current continuous mode and the duty ratio is less than 0.5, as shown in fig. 4, in a stage t0-t1, the main power tube Q1 and the second power tube Qb are turned on, the input voltage Vin stores energy in the capacitor Cf and the inductor Lo1, and provides energy to the output terminal o, so that the current iLo1 of the inductor Lo1 rises; at the same time, the rectifier Gsr2 is turned on, so that the current iLo2 flowing through the inductor Lo2 freewheels through the rectifier Qsr2 and drops. In the period from t1 to t2, the main power tube Q1 and the second power tube Qb are turned off, the rectifier tube Gsr1 is turned on, and the rectifier tube Gsr2 is kept on, so that the currents iLo1 and iLo2 both drop. In the period from t2 to t3, the main power tube Q2 and the first power tube Qa are turned on, the rectifier tube Gsr1 is kept on, and the rectifier tube Gsr2 is turned off. The capacitor Cf discharges through the second power stage circuit 2 and the first power transistor Qa to provide energy to the output terminal, wherein the voltage Vcf across the capacitor Cf serves as the input source of the second power stage circuit 2, so that the current iLo2 flowing through the inductor Lo2 rises; at the same time, current iLo1 freewheels through rectifier tube Qsr1 and drops. During the period t3-t4, the rectifier Gsr1 remains conductive while the rectifier Gsr2 remains conductive and both currents iLo1 and iLo2 drop. Because the two power stage circuits are conducted in a staggered phase mode, the current ripple of the output end is reduced. In the present embodiment, Vo/Vin is D/2, and therefore a higher voltage conversion ratio can be achieved.

When the power converter operates in the current interruption mode, as shown in fig. 5, in a period from t0 to t1, the main power tube Q1 and the second power tube Qb are conducted, the input voltage Vin stores energy in the capacitor Cf and the inductor Lo1 and provides energy to the output end, and thus the current iLo1 flowing through the inductor Lo1 rises; after time t1, the main power transistor Q1 and the second power transistor Qb are turned off, the rectifier Qsr1 is turned on, and the current iLo1 freewheels through the rectifier Qsr1 and drops; at time t2, current iLo1 drops to zero and rectifier Qsr1 turns off. In the stages t2-t3, all power devices in the circuit are in an off state, and no current flows in the circuit. In the stage t3-t4, the main power tube Q2 and the first power tube Qa are turned on, the voltage Vcf across the capacitor Cf serves as an input source of the second power stage circuit 2 to provide energy to the output end through the second power stage circuit 2 and the first power tube Qa, and thus the current iLo2 flowing through the inductor Lo2 rises; after time t4, the main power transistor Q2 is turned off, the rectifier Qsr2 is turned on, the current iLo2 flows through the rectifier Qsr2 and drops, and at time t5, the current iLo2 drops to zero, and the rectifier Qsr2 is turned off. At time t5-t6, all power devices in the circuit are in an off state.

As can be seen from fig. 5, when the rectifiers Qsr1 and Qsr2 are turned off after the inductor current in the respective power stage circuit is turned off to zero, the first power transistor Qa in the auxiliary module forms a discharge loop of the additional capacitor Cf instead of the original rectifier Qsr1, so that the rectifier Qsr1 does not need to be turned on again. Therefore, the current in the first power stage circuit 1 does not have a negative current condition, thereby ensuring the efficiency of the converter. In addition, the voltage Vcf on the capacitor Cf is always equal to 1/2Vin due to the symmetry of the two paths of inductive currents, so that the voltage offset on the capacitor Cf is avoided, and the reliability of the converter is ensured.

Fig. 6 shows a circuit diagram of a power converter according to a second embodiment of the present invention. As shown in fig. 6, in the present embodiment, the structure of the power converter is the same as that described above, except that the first terminal i of the power converter is taken as an output terminal and the second terminal o is taken as an input terminal, the second terminals of the first power stage circuit 1 and the second power stage circuit 2 are connected in parallel as the input terminal o of the power converter to receive the input voltage Vin, and the first terminal of the first power stage circuit 1 is taken as the output terminal i of the power converter to generate the output voltage Vout. Other specific circuit connection structures are the same as those of the first embodiment described above, and will not be described here.

In contrast, in the present embodiment, the second power stage circuit 2 constitutes a boost power stage circuit. The power tubes Qsr1 and Qsr2 are used as main power tubes and are conducted in a staggered mode with the same conduction time, the power tube Q1 and the power tube Q2 are used as rectifier tubes, and the rectifier tubes Q1 and Q2 are conducted complementarily with the main power tubes Qsr1 and Qsr2 respectively when the power converter works in a current continuous mode; when the power converter is operating in current chopping mode, rectifiers Q1 and Q2 turn on when the main power transistors Qsr1 and Qsr2, respectively, turn off when currents iLo1 and iLo2, respectively, cross zero. It should be understood that in the present embodiment, the rectifier tube is a synchronous rectification power tube, which may also be a rectification diode.

The driving signals of the first power transistor Qa and the second power transistor Qb are the same as those of the first embodiment, the maximum on time of the first power transistor Qa is the off time of the rectifier transistor Q1 connected to the first terminal of the current power stage circuit, and the maximum on time of the second power transistor Qb is the off time of the first power transistor Qa. Preferably, the first power transistor Qa is also in a conducting state during the conducting period of the rectifier Q2 connected to the first end of the next adjacent power stage circuit, and the second power transistor Qb is also in a conducting state during the conducting period of the rectifier Q1 connected to the first end of the current power stage circuit.

In addition, the capacitor Cf is charged through the second power stage circuit 2 at the stage (i.e. the second working stage) when the first power transistor Qa is turned on, that is, the first power transistor Qa provides a charging loop for the capacitor Cf at this time, and the voltage across the capacitor Cf at this time is the output voltage of the second power stage circuit 2. At the same time, the capacitor Cf discharges during the conducting phase (i.e., the first operating phase) of the second power transistor Qb, and supplies power to the output terminal o together with the input voltage Vin, so that the current of the inductor Lo1 flows to the output terminal i of the power converter through the auxiliary module.

Fig. 7 shows a circuit diagram of a power converter according to a third embodiment of the present invention. As shown in fig. 6, the power converter including the first power stage circuits 1 to 3 and the second power stage circuit 4 is taken as an example for explanation, so that one skilled in the art can easily expand the application of more first power stage circuits and one second power stage circuit.

As shown in fig. 7, the first terminal of the first power stage circuit 1 is connected to the first terminal i of the power converter, the first terminals of each of the other power stage circuits are respectively coupled to the first node of the previous adjacent power stage circuit, specifically, the first terminal of the second first power stage circuit 2 is connected to the first node a1 of the first power stage circuit 1, the first terminal of the third second power stage circuit 3 is connected to the first node a2 of the second first power stage circuit 2, the first terminal of the second power stage circuit 4 is connected to the first node of the adjacent first power stage circuit (the last power stage circuit), that is, the first node a3 of the third first power stage circuit 3, and the second terminals of each of the first and second power stage circuits are connected in parallel as the second terminal o of the power converter. Here, the first terminal i of the power converter is taken as an input terminal for receiving the input voltage Vin, and the second terminal o is taken as an output terminal for generating the output voltage Vout. It should be understood that the case where the first terminal i is an output terminal and the second terminal o is an input terminal also falls within the protection scope of the present invention.

Specifically, the first power stage circuit 1 includes a power transistor Q1, here a main power transistor, connected between a first terminal i and a first node a 1; a first energy storage element, here a capacitor C1, configured to couple with an adjacent power stage circuit (first power stage circuit 2) at a first node a1 and discharge via the adjacent power stage circuit; and an auxiliary module 11 configured such that the current flowing through the first magnetic element in the first power stage circuit 1 is not less than zero in the current interruption mode. Wherein the first magnetic element, here an inductor Lo1, is coupled between the auxiliary module 11 and the second terminal o of the first power stage circuit 1. It should be understood that in the case where the first terminal i is an output terminal and the second terminal o is an input terminal, the capacitor C1 is charged via the adjacent power stage circuit.

In particular, the auxiliary module 11 in the first power stage circuit 1 is connected between the second terminal of the capacitor C1 and the first terminal of the inductor Lo 1. The auxiliary module 11 is configured to allow the input voltage Vin to store energy in the inductor Lo1 during the first operation phase, so that the inductor current flows to the output terminal o through the auxiliary module 11, and provide a discharge loop for the capacitor C1 during the second operation phase to avoid the current reversal of the inductor Lo 1.

In the present embodiment, the auxiliary module 11 includes a first power transistor Qa1 connected between the second terminal of the capacitor C1 and the reference ground, and a second power transistor Qb1 connected between the second terminal of the capacitor C1 and the first terminal of the inductor Lo 1. In addition, the first power stage circuit 1 further includes a power tube Qsr1 (herein, a rectifier tube) connected between the first terminal of the inductor Lo1 and the reference ground to provide a free-wheeling loop for the first power stage circuit 1.

The first power stage circuit j (where j is 2, 3) includes a power tube Qj as a main power tube of each first power stage circuit j, and is connected between the first end of the current first power stage circuit j, that is, the first node a (j-1) of the last adjacent power stage circuit (j-1), and the first node aj of the current first power stage circuit j; a first energy storage element, here a capacitor Cj, configured to be coupled in common with a next adjacent power stage circuit (j +1) to the first node aj and to be discharged via said adjacent power stage circuit (j + 1); and an auxiliary module jj configured such that a current flowing through the first magnetic element in the first power stage circuit j is not less than zero in the current chopping mode. Wherein the first magnetic element, here an inductor Loj, is coupled between the auxiliary module jj and the second terminal o. It should be understood that in the case where the first terminal i is an output terminal and the second terminal o is an input terminal, the capacitor Cj is charged via the adjacent power stage circuit.

In particular, the auxiliary module jj in the first power stage circuit j is connected between the second terminal of the capacitor Cj and the first terminal of the inductor Loj. The auxiliary module jj is configured to allow the input voltage Vin to charge the capacitor Cf and the inductor Lo1 during the first operation phase, so that the current of the inductor Loj flows to the output terminal o through the auxiliary module jj, and a discharge loop is provided for the capacitor Cj during the second operation phase to avoid the current reversal of the inductor Loj.

In this embodiment, the auxiliary module jj includes a first power transistor Qaj connected between the second terminal of the capacitor Cj and the reference ground, and a second power transistor Qbj connected between the second terminal of the capacitor Cj and the first terminal of the inductor Loj. In addition, the first power stage circuit j further includes a power transistor Qsrj as a rectifying transistor connected between the first terminal of the inductor Loj and the reference ground to provide a free-wheeling circuit for the first power stage circuit j.

The second power stage circuit 4 comprises a power transistor Q4 (as the main power transistor) and a power transistor Qsr4 (as the rectifier transistor) connected in series between the first terminal of the second power stage circuit 4 and ground, and a second magnetic element, here an inductor Lo 4.

In some embodiments, the first magnetic elements and/or the first and second magnetic elements may be coupled to each other.

Fig. 8 shows a first operating waveform of a power converter according to a third embodiment of the present invention. Here, the current interruption mode when the duty ratio is less than 0.5 is merely described as an example, and otherwise, the power converter of the first embodiment may be referred to. As can be seen from the figure, the driving signal Gbm of the second power transistor Qbm in the first power stage circuit m (m is 1, 2, 3) is the same as the driving signal Gm of the power transistor Qm connected to the first end of the current power stage circuit m, while the driving signal Gam of the first power transistor Qm is the same as the driving signal Gm +1 of the power transistor Qm +1 connected to the first end of the next adjacent power stage circuit (m + 1). When the main power transistor Qm in the power stage circuit m is turned on, since the second power transistor Qbm is also turned on, the capacitor Cm is charged, and the current flowing through the inductor Lom flows to the output terminal o through the auxiliary module 11, and iLom rises. The capacitor Cm discharges when the power transistor Q (m +1) and the first power transistor Qam in the next adjacent power stage circuit (m +1) are turned on.

It should be understood that only one of the embodiments is given here, and the setting of the driving signals of the first power transistor Qa and the second power transistor Qb is the same as that in the first embodiment, so that other situations described in the first embodiment can be applied to this, and are not described herein again.

In the current continuous mode, the driving signal Gsrm of the rectifier Qsrm in the first power stage circuit m is complementary to the driving signal Gm of the main power transistor Qm, and the driving signal Gsr4 of the rectifier Qsr4 in the second power stage circuit 4 is complementary to the driving signal G4 of the main power transistor Q4. In the current interruption mode, the rectifier Qsrm in the first power stage circuit m is turned on when the main power transistor Qm is turned off and turned off when the current iLom flowing through the inductor Lom crosses zero, while the rectifier Qsr4 in the second power stage circuit 4 is turned on when the main power transistor Q4 is turned off and turned off when the current iLo4 flowing through the inductor Lo4 crosses zero.

In the present embodiment, the rectifiers Qsrm and Qsr4 are all synchronous rectification power transistors, and those skilled in the art will understand that the rectifiers Qsrm and Qsr4 may be replaced by rectification diodes, which do not affect the operation of the converter.

In addition, in the present embodiment, the conduction time of the main power transistor Qm in the first power stage circuit m and the conduction time of the main power transistor Q4 in the second power stage circuit 4 are the same, and each of the power transistor conduction times has a phase difference, preferably, the phase difference is 360 °/(m +1) (i.e., 90 °, time difference Ts/4 on the figure). Therefore, the inductive currents of all stages of circuits are staggered, and the current ripple is reduced. As shown in the figure, the invention realizes that the inductive current in each stage of power stage circuit is not less than zero in the current discontinuous mode, and simultaneously ensures the reliable operation of the power converter. The specific operation principle is similar to that of the first embodiment and will not be described here.

Meanwhile, the control circuit in the power converter can adjust the size of the output voltage Vout by adjusting the duty ratio D of the main power tube in the first and second power stage circuits to generate the desired output voltage. It should be understood that the control circuit may regulate the output voltage Vout by adjusting the on-time of the main power transistor in the first and second power stage circuits at a fixed switching frequency. Of course, the control circuit may also keep the on-time of the main power transistor in each power stage circuit unchanged, and adjust the output voltage Vout by adjusting the switching frequency of the power converter. In addition, other control methods for controlling the power converter in the prior art may also be applied to the present embodiment.

Fig. 9 shows a second operating waveform of a power converter according to a third embodiment of the present invention. Besides the above control method of staggered phase shift of each stage, a second control method can also be adopted. When the total number of the first power stage circuit and the second power stage circuit is N, the power stage circuit comprises N-1 first power stage circuits and one second power stage circuit, the driving signals of the main power tubes in the (2j-1) th (i.e. the ordinal number is odd) power stage circuit are the same (marked as a first driving signal), and the driving signals of the main power tubes in the 2j (i.e. the ordinal number is even) power stage circuit are the same (marked as a second driving signal), so that a phase difference of 180 degrees exists between the first driving signal and the second driving signal. Wherein j and N are positive integers, N is more than or equal to 2, and j is less than or equal to (N + 1)/2. As shown in the figure, taking N as an example for explanation, in this embodiment, the driving signal of the main power transistor in the first power stage circuit (i.e., the driving signal G1 of the power transistor Q1) is the same as the driving signal of the main power transistor in the third power stage circuit (i.e., the driving signal G3 of the power transistor Q3), the driving signal of the main power transistor in the second power stage circuit (i.e., the driving signal G2 of the power transistor Q2) is the same as the driving signal of the main power transistor in the fourth power stage circuit (i.e., the driving signal G4 of the power transistor Q4), and the driving signal G1 and the driving signal G2 have a phase difference of 180 ° (i.e., a time difference Ts/2). In addition, the driving signal Gbm of the second power transistor Qbm in the first power stage circuit m (m is 1, 2, 3) is the same as the driving signal Gm of the power transistor Qm connected to the first end of the current power stage circuit m, while the driving signal Gam of the first power transistor Qm is the same as the driving signal Gm +1 of the power transistor Qm +1 connected to the first end of the next adjacent power stage circuit (m + 1). The switching states of the first power tube and the second power tube are the same as those in the first embodiment. And thus can be generalized to a power converter including N power stage circuits.

In this control mode, the inductor currents in the odd power stage circuits are the same, and the inductor currents in the even power stage circuits are the same, as shown in the figure, the currents iLo1 and iLo3 are the same, and the currents iLo2 and iLo4 are the same, and are respectively staggered by 180 °. Also, in this control mode, the control circuit in the power converter can adjust the magnitude of the output voltage Vout by adjusting the duty cycle D of the main power transistor in the first and second power stage circuits to generate the desired output voltage. The manner of adjusting the duty cycle D is the same as described above and will not be further described herein.

In addition, the invention realizes that the inductive current in each stage of power stage circuit is not less than zero in the current discontinuous mode, so that the power converter can work normally under light load, and the reliable operation of the power converter is ensured.

It should be understood that the following architecture exists among other power converters: the first end of the magnetic element is connected to an energy storage element through a power tube, the energy storage element is coupled to the first end of a magnetic element, and when the first end of the magnetic element is connected to a reference ground through a power tube, referring to this embodiment, the auxiliary module in the embodiment of the present invention is added between the second end of the energy storage element and the first end of the magnetic element to avoid a negative current in a discontinuous current mode.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.