阅读说明：本技术 一种新型的电流型交错pwm控制电路 (Novel current type staggered PWM control circuit ) 是由 纪清锋 刘绍辉 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种新型的电流型交错PWM控制电路,包括交错时钟信号控制器、峰值电流检测器及驱动控制器；交错时钟信号控制器用于设定频率及占空比的相互交错的时钟信号,并将时钟信号分别发送给对应的峰值电流检测器和驱动控制器；峰值电流检测器用于逐周期检测电路中的峰值电流,并根据峰值电流和接收到的时钟信号下发控制信号给驱动控制器；驱动控制器根据接收到的时钟信号和控制信号提供相互交错的驱动信号给驱动,并控制驱动的最大占空比。本发明提供了一种新型的电流型交错PWM控制电路,其中交错时钟信号控制器、峰值电流检测器及驱动控制器之间采用分离器件搭建,相互作用控制,具有响应快、可靠性高、成本低等特点。(The invention discloses a novel current type staggered PWM control circuit, which comprises a staggered clock signal controller, a peak current detector and a drive controller, wherein the peak current detector is connected with the peak current detector; the staggered clock signal controller is used for setting the frequency and the duty ratio of clock signals which are staggered with each other, and respectively sending the clock signals to the corresponding peak current detector and the corresponding driving controller; the peak current detector is used for detecting the peak current in the circuit cycle by cycle and sending a control signal to the drive controller according to the peak current and the received clock signal; the driving controller provides driving signals which are mutually staggered to the driving according to the received clock signal and the control signal, and controls the maximum duty ratio of the driving. The invention provides a novel current type staggered PWM control circuit, wherein a staggered clock signal controller, a peak current detector and a driving controller are built by adopting separating devices and are controlled by interaction, and the circuit has the characteristics of quick response, high reliability, low cost and the like.)

1. A novel current type staggered PWM control circuit is characterized by comprising a staggered clock signal controller, a peak current detector and a driving controller;

the staggered clock signal controller is used for setting mutually staggered clock signals of frequency and duty ratio and respectively sending the clock signals to the corresponding peak current detector and the corresponding driving controller;

the peak current detector is used for detecting the peak current in the circuit cycle by cycle and sending a control signal to the drive controller according to the peak current and the received clock signal;

and the driving controller provides mutually staggered driving signals for driving according to the received clock signals and the control signals and controls the maximum duty ratio of the driving.

2. The novel current mode interleaved PWM control circuit according to claim 1, wherein said driver is turned on when both said clock signal and said control signal received by said driver controller are low level signals;

when one of the clock signal and the control signal received by the driving controller is a high level signal, the driving is turned off.

3. A novel current mode interleaved PWM control circuit according to claim 1, wherein said clock signal comprises a first clock signal and a second clock signal, said first clock signal and said second clock signal are two interleaved clock signals, said peak current detector comprises a first peak current detector and a second peak current detector, said drive controller comprises a first drive controller and a second drive controller, said drive signals comprise a first drive signal and a second drive signal, said first drive signal and said second drive signal are two interleaved drive signals;

the staggered clock signal controller respectively sends a first clock signal to the first peak current detector and the first driving controller, and sends a second clock signal to the second peak current detector and the second driving controller;

the first peak current detector sends a first control signal to the first driving controller according to the peak current and the received first clock signal;

the second peak current detector sends a second control signal to the second driving controller according to the peak current and the received second clock signal;

the first driving controller provides the first driving signal according to the received first clock signal and the first control signal;

the second driving controller provides the second driving signal according to the received second clock signal and the second control signal.

4. The novel current-mode interleaved PWM control circuit as claimed in claim 3, wherein said interleaved clock signal controller comprises a first flip-flop U1, a second flip-flop U2, a first diode group D1, a second diode group D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and an oscillator B10, wherein an output terminal of said first flip-flop U1 is connected to said first clock signal, an input terminal of said first flip-flop U1 is connected to one terminal of said first resistor R1, one terminal of said second resistor R2, a third pin of said first diode group D1 and one terminal of said first capacitor C1, the other terminal of said first resistor R1 and a second pin of said first diode group D1 are connected to VREF, the other terminal of said first diode group D2 is connected to ground, and the first diode group D1 is connected to ground, the other end of the first capacitor C1 is connected to a first pulse signal output end of the oscillator B10, the output end of the second flip-flop U2 is connected to the second clock signal, the input end of the second flip-flop U2 is connected to one end of the third resistor R3, one end of the fourth resistor R4, the third pin of the second diode group D2, and one end of the second capacitor C2, the other end of the third resistor R3 and the second pin of the second diode group D2 are both connected to a reference voltage VREF, the other end of the fourth resistor R4 is grounded, the first pin of the second diode group D2 is grounded, and the other end of the second capacitor C2 is connected to a second pulse signal output end of the oscillator B10.

5. A novel current mode interleaved PWM control circuit as claimed in claim 4, wherein said oscillator B10 comprises a third flip-flop U3, a fourth flip-flop U4, a fifth flip-flop U5, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3 and a fourth capacitor C4, a positive power terminal of said third flip-flop U3 and one terminal of said seventh resistor R7 are all connected to a reference voltage VREF, an input terminal of said third flip-flop U3 is respectively connected to another terminal of said seventh resistor R7, one terminal of said sixth resistor R6 and one terminal of said fourth capacitor C4, another terminal of said fourth capacitor C4 is connected to ground, a negative power terminal of said third flip-flop U3 is connected to ground, an output terminal of said third flip-flop U3 is respectively connected to one terminal of said fifth resistor R5 and another terminal of said first capacitor C1, an input terminal of said fourth flip-flop U5 is connected to said third terminal of said fifth flip-flop U599 and said third capacitor C599, the other end of the third capacitor C3 is grounded, the output end of the fourth flip-flop U4 is connected to the input end of the fifth flip-flop U5, and the output end of the fifth flip-flop U5 is connected to the other end of the sixth resistor R6 and the other end of the second capacitor C2, respectively.

6. A novel current-mode interleaved PWM control circuit as claimed in claim 3, wherein said first peak current detector comprises a first operational amplifier U11, a first switch S1, a first diode D11, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and an eleventh capacitor C11, a first power current detection signal IS1+ IS connected to the first terminal of said first switch S1, the one terminal of said eleventh capacitor C11, the one terminal of said first diode D11 and the positive input terminal of said transport amplifier U11 through said eleventh resistor R11, respectively, the second terminal of said first switch S1 IS connected to the one terminal of said thirteenth resistor R13 and the one terminal of said fourteenth resistor R14, respectively, the other terminal of said thirteenth resistor R13 IS connected to said first clock signal, the first terminal S1 of said first switch and the other terminal of said fourteenth resistor R14 are connected to ground, the other end of the eleventh capacitor C11 is grounded, the other end of the first diode D11 is connected to the output end of the transport amplifier U11 and the first control signal through the twelfth resistor R12, the inverting input end of the transport amplifier U11 is connected to the feedback loop signal voltage VF and one end of the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded.

7. A novel current-mode interleaved PWM control circuit as claimed in claim 6, wherein said second peak current detector comprises a second operational amplifier U21, a second switch S2, a second diode D21, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a twenty-first capacitor C21, a second power current detection signal IS2+ IS connected to the first terminal of said second switch S2, the one terminal of said twenty-first capacitor C21, the one terminal of said second diode D21 and the positive input terminal of said transport amplifier U21 through said twenty-first resistor R21, the second terminal of said second switch S2 IS connected to the one terminal of said twenty-third resistor R23 and the one terminal of said twenty-fourth resistor R24, respectively, the other terminal of said twenty-third resistor R23 IS connected to said second clock signal, the third end of the second switch S2 is connected to the other end of the twenty-fourth resistor R24, the other end of the twenty-first capacitor C21 is grounded, the other end of the second diode D21 passes through the twenty-second resistor R22 and is connected to the output end of the transport amplifier U21 and the first control signal, the reverse input end of the transport amplifier U21 is connected to the feedback loop signal voltage VF and one end of the twenty-fifth resistor R25, and the other end of the twenty-fifth resistor R25 is grounded.

8. The novel current-mode interleaved PWM control circuit as claimed in claim 7, wherein said first switch S1 and said second switch S2 are MOS transistors or triodes.

9. The novel current-mode interleaved PWM control circuit according to claim 3, wherein said first driver controller comprises a first nand gate U12, a third diode D12 and a sixteenth resistor R16, said first clock signal is connected to the first input terminal of said first nand gate U12, the second input terminal of said first nand gate U12 and one end of said sixteenth resistor R16 through said third diode D12, the other end of said sixteenth resistor R16 is connected to said first control signal, the positive power terminal of said first nand gate U12 is connected to a reference voltage VREF, the negative power terminal of said first nand gate U12 is grounded, and the output terminal of said first nand gate U12 is connected to said first driver signal.

10. The novel current-mode interleaved PWM control circuit according to claim 9, wherein said second driver controller comprises a second nand gate U22, a fourth diode D22 and a twenty-sixth resistor R26, said second clock signal is connected to the first input terminal of said second nand gate U22, the second input terminal of said second nand gate U22 and one end of said twenty-sixth resistor R26 through said fourth diode D22, the other end of said twenty-sixth resistor R26 is connected to said second control signal, the positive power terminal of said second nand gate U22 is connected to a reference voltage VREF, the negative power terminal of said second nand gate U22 is grounded, and the output terminal of said second nand gate U22 is connected to said second driver signal.

Technical Field

The invention relates to the technical field of switching power supplies, in particular to a novel current type staggered PWM control circuit.

Background

The switching power supply generally comprises a main power stage circuit and a switching power supply control circuit, wherein the control circuit of the switching power supply is connected with the main power stage circuit to output a switching control signal to control the on and off of a main switching tube in the main power stage circuit, so that the switching power supply converts an input voltage into a voltage required by a load and outputs the voltage.

However, the conventional switching power supply circuit generally has a complex structure, a low response speed and low reliability, and is difficult to meet the requirement of localization in the background of trade battles.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a novel current type staggered PWM control circuit.

The technical scheme of the invention is as follows:

a novel current type staggered PWM control circuit comprises a staggered clock signal controller, a peak current detector and a driving controller;

the staggered clock signal controller is used for setting mutually staggered clock signals of frequency and duty ratio and respectively sending the clock signals to the corresponding peak current detector and the corresponding driving controller;

the peak current detector is used for detecting the peak current in the circuit cycle by cycle and sending a control signal to the drive controller according to the peak current and the received clock signal;

and the driving controller provides mutually staggered driving signals for driving according to the received clock signals and the control signals and controls the maximum duty ratio of the driving.

According to the invention of the above scheme, further, when the clock signal and the control signal received by the driving controller are both low level signals, the driving is turned on;

when one of the clock signal and the control signal received by the driving controller is a high level signal, the driving is turned off.

According to the invention of the above scheme, further, the clock signal includes a first clock signal and a second clock signal, the first clock signal and the second clock signal are two clock signals interleaved with each other, the peak current detector includes a first peak current detector and a second peak current detector, the driving controller includes a first driving controller and a second driving controller, the driving signal includes a first driving signal and a second driving signal, and the first driving signal and the second driving signal are two driving signals interleaved with each other;

the staggered clock signal controller respectively sends a first clock signal to the first peak current detector and the first driving controller, and sends a second clock signal to the second peak current detector and the second driving controller;

the first peak current detector sends a first control signal to the first driving controller according to the peak current and the received first clock signal;

the second peak current detector sends a second control signal to the second driving controller according to the peak current and the received second clock signal;

the first driving controller provides the first driving signal according to the received first clock signal and the first control signal;

the second driving controller provides the second driving signal according to the received second clock signal and the second control signal.

According to the present invention of the above solution, further, the staggered clock controller includes a first flip-flop U1, a second flip-flop U2, a first diode group D1, a second diode group D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and an oscillator B10, an output terminal of the first flip-flop U1 is connected to the first clock signal, an input terminal of the first flip-flop U1 is connected to one terminal of the first resistor R1, one terminal of the second resistor R2, a third pin of the first diode group D1 and one terminal of the first capacitor C1, the other terminal of the first resistor R1 and the second pin of the first diode group D1 are connected to a reference voltage VREF, the other terminal of the second diode R2 is grounded, and the first terminal 67676726 of the first diode group D1 is grounded, the other end of the first capacitor C1 is connected to a first pulse signal output end of the oscillator B10, the output end of the second flip-flop U2 is connected to the second clock signal, the input end of the second flip-flop U2 is connected to one end of the third resistor R3, one end of the fourth resistor R4, the third pin of the second diode group D2, and one end of the second capacitor C2, the other end of the third resistor R3 and the second pin of the second diode group D2 are both connected to a reference voltage VREF, the other end of the fourth resistor R4 is grounded, the first pin of the second diode group D2 is grounded, and the other end of the second capacitor C2 is connected to a second pulse signal output end of the oscillator B10.

According to the present invention of the above solution, further, the oscillator B10 includes a third flip-flop U3, a fourth flip-flop U4, a fifth flip-flop U5, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3, and a fourth capacitor C4, a positive power terminal of the third flip-flop U3 and one end of the seventh resistor R7 are both connected to a reference voltage VREF, an input terminal of the third flip-flop U3 is respectively connected to the other end of the seventh resistor R7, one end of the sixth resistor R6, and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, a negative power terminal of the third flip-flop U3 is grounded, an output terminal of the third flip-flop U3 is respectively connected to one end of the fifth resistor R5 and the other end of the first capacitor C1, an input terminal of the fourth flip-flop U4 is respectively connected to the first end of the fifth resistor R3 and the other end of the fifth resistor R5, the other end of the third capacitor C3 is grounded, the output end of the fourth flip-flop U4 is connected to the input end of the fifth flip-flop U5, and the output end of the fifth flip-flop U5 is connected to the other end of the sixth resistor R6 and the other end of the second capacitor C2, respectively.

According to the invention of the above solution, further, the first peak current detector includes a first operational amplifier U11, a first switch S1, a first diode D11, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and an eleventh capacitor C11, a first power current detection signal IS1+ IS connected to the first terminal of the first switch S1, the one terminal of the eleventh capacitor C11, the one terminal of the first diode D11 and the positive input terminal of the transport amplifier U11 through the eleventh resistor R11, the second terminal of the first switch S1 IS connected to the one terminal of the thirteenth resistor R13 and the one terminal of the fourteenth resistor R14, the other terminal of the thirteenth resistor R13 IS connected to the first clock signal, the third terminal of the first switch S1 and the other terminal of the fourteenth resistor R14 are grounded, the other end of the eleventh capacitor C11 is grounded, the other end of the first diode D11 is connected to the output end of the transport amplifier U11 and the first control signal through the twelfth resistor R12, the inverting input end of the transport amplifier U11 is connected to the feedback loop signal voltage VF and one end of the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded.

According to the invention of the above solution, further, the second peak current detector includes a second operational amplifier U21, a second switch S2, a second diode D21, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, and a twenty-first capacitor C21, a second power current detection signal IS2+ IS connected to the first end of the second switch S2, the one end of the twenty-first capacitor C21, the one end of the second diode D21, and the forward input end of the transport amplifier U21 through the twenty-first resistor R21, respectively, the second end of the second switch S2 IS connected to the one end of the twenty-third resistor R23 and the one end of the twenty-fourth resistor R24, respectively, the other end of the twenty-third resistor R23 IS connected to the second clock signal, the second end of the second switch S2 IS connected to the other end of the twenty-fourth resistor R24, the other end of the twenty-first capacitor C21 is grounded, the other end of the second diode D21 is connected to the output end of the transport amplifier U21 and the first control signal through the twenty-second resistor R22, the reverse input end of the transport amplifier U21 is connected to the feedback loop signal voltage VF and one end of the twenty-fifth resistor R25, and the other end of the twenty-fifth resistor R25 is grounded.

According to the present invention of the above solution, further, the first switch S1 and the second switch S2 are MOS transistors or triodes.

According to the present invention with the above scheme, further, the first driving controller includes a first nand gate U12, a third diode D12 and a sixteenth resistor R16, the first clock signal is connected to the first input terminal of the first nand gate U12, the second input terminal of the first nand gate U12 and one end of the sixteenth resistor R16 through the third diode D12, the other end of the sixteenth resistor R16 is connected to the first control signal, the positive power terminal of the first nand gate U12 is connected to the reference voltage VREF, the negative power terminal of the first nand gate U12 is grounded, and the output terminal of the first nand gate U12 is connected to the first driving signal.

According to the present invention with the foregoing scheme, further, the second driving controller includes a second nand gate U22, a fourth diode D22, and a twenty-sixth resistor R26, the second clock signal is connected to the first input terminal of the second nand gate U22, the second input terminal of the second nand gate U22, and one end of the twenty-sixth resistor R26 through the fourth diode D22, the other end of the twenty-sixth resistor R26 is connected to the second control signal, the positive power terminal of the second nand gate U22 is connected to the reference voltage VREF, the negative power terminal of the second nand gate U22 is grounded, and the output terminal of the second nand gate U22 is connected to the second driving signal.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a novel current type staggered PWM control circuit, wherein a staggered clock signal controller, a peak current detector and a driving controller are built by adopting separating devices and are controlled by interaction, and the circuit has the characteristics of quick response, high reliability, low cost and the like; the generated staggered PWM driving signal can be used for topological applications such as double-circuit BUCK staggered parallel connection, double-circuit BOOST staggered parallel connection and the like, the requirement of localization of 100% of devices is met, and the method can be widely applied to the industries such as laser, medicine, industry, military and the like.

Drawings

FIG. 1 is a schematic frame diagram of the present invention;

FIG. 2 is a circuit diagram of an interleaved clock signal controller according to the present invention;

FIG. 3 is a timing diagram of the staggered clock controller according to the present invention;

FIG. 4 is a schematic diagram of a staggered clock controller according to the present invention;

FIG. 5 is a circuit diagram of the peak current detector of the present invention;

FIG. 6 is a circuit diagram of the driving controller according to the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

Referring to fig. 1, an embodiment of the present invention provides a novel current-mode interleaved PWM control circuit, which includes an interleaved clock signal controller, a peak current detector, and a driving controller.

The staggered clock signal controller is used for setting the frequency and duty ratio of the clock signals which are staggered with each other, and respectively sending the clock signals to the corresponding peak current detector and the corresponding driving controller. Wherein, the frequency and the duty ratio of the clock signal can be set according to requirements.

The peak current detector is used for detecting the peak current in the circuit cycle by cycle and sending a control signal to the drive controller according to the peak current and the received clock signal. When the peak current reaches the detection set value, the peak current rapidly sends a control signal to the drive controller, and the drive controller is fast in response and high in reliability.

The driving controller provides a driving signal for driving according to the received clock signal and the control signal, controls the maximum duty ratio of the driving, and ensures that the circuit can operate reliably and efficiently. When the clock signal and the control signal received by the driving controller are both low level signals, the driving is started; when one of the clock signal and the control signal received by the driving controller is a high level signal, the driving is closed.

The invention provides a novel current type staggered PWM control circuit, wherein a staggered clock signal controller, a peak current detector and a driving controller are built by adopting separating devices and are controlled by interaction, and the circuit has the characteristics of quick response, high reliability, low cost and the like; the generated staggered PWM driving signal can be used for topological applications such as double-circuit BUCK staggered parallel connection, double-circuit BOOST staggered parallel connection and the like, the requirement of localization of 100% of devices is met, and the method can be widely applied to the industries such as laser, medicine, industry, military and the like.

Referring to fig. 1, in the present embodiment, the clock signals include a first clock signal CLK1 and a second clock signal CLK2, the first clock signal CLK1 and the second clock signal CLK2 are two clock signals interleaved with each other, the peak current detector includes a first peak current detector and a second peak current detector, the driving controller includes a first driving controller and a second driving controller, the driving signals include a first driving signal DRVA and a second driving signal DRVB, and the first driving signal DRVA and the second driving signal DRVB are two driving signals interleaved with each other; the staggered clock signal controller transmits a first clock signal CLK1 to the first peak current detector and the first drive controller, respectively, and transmits a second clock signal CLK2 to the second peak current detector and the second drive controller, respectively; the first peak current detector sends a first control signal IS1_ signal to the first driving controller according to the peak current and the received first clock signal CLK 1; the second peak current detector sends a second control signal IS2_ signal to the second driving controller according to the peak current and the received second clock signal CLK 2; the first driving controller provides a first driving signal DRVA according to the received first clock signal CLK1 and a first control signal IS1_ signal; the second driving controller provides the second driving signal DRVB according to the received second clock signal CLK2 and the second control signal IS2_ signal.

Referring to fig. 2, in detail, the staggered clock controller includes a first flip-flop U1, a second flip-flop U2, a first diode group D1, a second diode group D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and an oscillator B10, an output terminal of the first flip-flop U1 is connected to the first clock signal CLK1, an input terminal of the first flip-flop U1 is respectively connected to one end of the first resistor R1, one end of the second resistor R2, a third pin of the first diode group D1 and one end of the first capacitor C1, the other end of the first resistor R1 and a second pin of the first diode group D7 are both connected to a reference voltage, the other end of the second resistor R2 is grounded, a first pin of the first diode group D1 is grounded, the other end of the first capacitor C874 of the first diode group D1 is connected to the first clock signal output terminal 1 of the first flip-flop U1, an input end of the second flip-flop U2 is connected to one end of the third resistor R3, one end of the fourth resistor R4, the third pin of the second diode group D2, and one end of the second capacitor C2, the other end of the third resistor R3 and the second pin of the second diode group D2 are both connected to the reference voltage VREF, the other end of the fourth resistor R4 is grounded, the first pin of the second diode group D2 is grounded, and the other end of the second capacitor C2 is connected to the second pulse signal output end of the oscillator B10. The first pulse signal output terminal outputs a first falling edge pulse signal B12, the second pulse signal output terminal outputs a second falling edge pulse signal B14, one end of the first capacitor C1 generates a first falling edge trigger signal a11, and one end of the second capacitor C2 generates a second falling edge trigger signal a 12.

The oscillator B10 comprises a third flip-flop U3, a fourth flip-flop U4, a fifth flip-flop U5, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3 and a fourth capacitor C4, wherein a positive power terminal of the third flip-flop U3 and one end of the seventh resistor R7 are both connected to the reference voltage VREF, an input terminal of the third flip-flop U3 is respectively connected to the other end of the seventh resistor R7, one end of the sixth resistor R6 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, a negative power terminal of the third flip-flop U3 is grounded, an output terminal of the third flip-flop U3 is respectively connected to one end of the fifth resistor R5 and the other end of the first capacitor C1, an input terminal of the fourth flip-flop U4 is respectively connected to the other end of the fifth resistor R5 and one end of the third capacitor C5, and an output terminal of the fourth flip-flop U5 are respectively connected to the ground, an output terminal of the fifth flip-flop U5 is connected to the other terminal of the sixth resistor R6 and the other terminal of the second capacitor C2, respectively. The flip-flops (U1-U5) are all logic not gate flip-flops, one end of the fourth capacitor C4 generates a first signal B11, and one end of the third capacitor C3 generates a second signal B13.

Referring to fig. 3, the staggered clock signal controller employs a nor flip-flop and generates two staggered first falling edge pulse signals B12 and second falling edge pulse signals B14 through an oscillator B10, according to the following principle:

the positive trigger pulse threshold voltage of the triggers (U1-U5) is Vp, and the negative trigger pulse threshold voltage is Vn; the time period T1-T2 is the time required for the voltage V13_ max at the two ends of the third capacitor C3 to be discharged to Vn through the fifth resistor R5, and is set as a time period T12; the time period T2-T3 is the time required for the voltage V11_ max at the two ends of the fourth capacitor C4 to be discharged to Vn through the sixth resistor R6, and is set as a time period T23; the time from T3 to T4 is the time required for charging the third capacitor C3 from V13_ min to Vp by charging the third capacitor C3 through the fifth resistor R5 by using the reference VREF voltage, and is set as a time period T34; the time period from T4 to T5 is the time period T45 when the fourth capacitor C4 is charged by the reference VREF voltage through the sixth resistor R6 and the time required for charging from V11_ min to Vp is set;

one cycle of the first falling edge pulse signal B12 and the second falling edge pulse signal B14 is composed of 4 periods (T12, T23, T34, T45). In order to make the falling edges of the first falling edge pulse signal B12 and the second falling edge pulse signal B14 (i.e., at the time t1 and the time t 2) form an angle of 180 degrees with each other, the following relations need to be satisfied:

namely: T12-T23 + T34+ T45-is

Therefore, the parameters of the fifth resistor R5, the sixth resistor R6, the third capacitor C3 and the fourth capacitor C4 are set to satisfy the relation (2), so that the falling edges of the pulse signals which are staggered with each other can be obtained.

Referring to fig. 4, fig. 4 is a schematic diagram of the wave-generating of the staggered clock signal controller, in which the falling edges of each of the first falling edge pulse signal B12 and the second falling edge pulse signal B14 trigger the first falling edge trigger signal a11 and the second falling edge trigger signal a12 to be pulled down, so as to invert the first clock signal CLK1 and the second clock signal CLK2, and generate the first clock signal CLK1 and the second clock signal CLK2 which are staggered with each other. The periods of the first clock signal CLK1 and the second clock signal CLK2 are T12+ T23+ T34+ T34; the high time of the first clock signal CLK1 is the time required for the reference voltage VREF to charge the first capacitor C1 to the Vp threshold through the first resistor R1, and the high time of the second clock signal CLK2 is the time required for the reference voltage VREF to charge the second capacitor C2 to the Vp threshold through the third resistor R3.

Therefore, the staggered clock signal controller can provide the first clock signal CLK1 and the second clock signal CLK2 which are staggered with each other, and the frequency and the duty ratio of the clock signals can be adjusted by changing parameters.

Referring to fig. 5, in detail, the first peak current detector includes a first operational amplifier U11, a first switch S1, a first diode D11, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and an eleventh capacitor C11, the first power current detection signal IS 28 + IS respectively connected to a first end of a first switch S1, one end of an eleventh capacitor C11, one end of a first diode D11 and a positive input end of a transport amplifier U6327 through the eleventh resistor R11, a second end of the first switch S1 IS respectively connected to one end of a thirteenth resistor R13 and one end of a fourteenth resistor R14, the other end of the thirteenth resistor R13 IS connected to a first clock signal CLK 13, the first end of the first switch S13 and the other end of the fourteenth resistor R13 are grounded, the other end of the eleventh capacitor C13 IS grounded, the other end of the first diode D13 IS respectively connected to a first control signal output end of the first operational amplifier S13 and the twelfth capacitor C13, the inverting input terminal of the transport amplifier U11 is connected to the feedback loop signal voltage VF and one end of the fifteenth resistor R15, respectively, and the other end of the fifteenth resistor R15 is grounded.

The second peak current detector includes a second operational amplifier U21, a second switch S2, a second diode D21, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25 and a twenty-first capacitor C21, the second power current detection signal IS2+ IS respectively connected to the first end of the second switch S2, one end of the twenty-first capacitor C21, one end of the second diode D21 and the positive input end of the transport amplifier U21 through the twenty-first resistor R21, the second end of the second switch S2 IS respectively connected to one end of the twenty-third resistor sigr 23 and one end of the twenty-fourth resistor R24, the other end of the twenty-third resistor R23 IS connected to the second clock signal CLK 23, the third end of the second switch S23 IS connected to the other end of the twenty-fourth resistor sigr 23, the other end of the first capacitor C23 IS connected to the ground, and the second end of the second diode D23 IS 23 controls the twelfth output end of the transport amplifier U23 and the twelfth capacitor C23 And the reverse input end of the transport amplifier U21 is respectively connected with the feedback loop signal voltage VF and one end of a twenty-fifth resistor R25, and the other end of the twenty-fifth resistor R25 is grounded.

The peak current detector adopts a high-speed operational amplifier, and the feedback loop signal voltage VF is respectively sent to the inverting input ends of the first operational amplifier U11 and the second operational amplifier U21 to be used as reference signals. The first power current detection signal IS1+ and the second power current detection signal IS2+ which pass through two parallel topologies are filtered by RC (an eleventh resistor R11, an eleventh capacitor C11, a twenty-first resistor R21 and a twenty-first capacitor C21) and are respectively sent to the positive input ends of a first operational amplifier U11 and a second operational amplifier U21, and when the level of the positive input end IS lower than that of the negative input end, the output end sends (low level) control signals (IS1_ signal and IS2_ signal) to the driving controller. When the level of the positive input terminal IS higher than that of the negative input terminal, the output terminal sends (high level) control signals (IS1_ signal, IS2_ signal) to the driving controller. Meanwhile, if the set value of the peak current has not been reached in one cycle, the first clock signal CLK1 and the second clock signal CLK2 pull down the voltages of the positive input terminals of the first operational amplifier U11 and the second operational amplifier U21 through the first switch S1 and the second switch S2 (the first switch S1 and the second switch S2 may be MOS transistors, or the like that implement the switching function), and the output terminals of the first operational amplifier U11 and the second operational amplifier U21 send (low level) control signals (IS1_ signal, IS2_ signal) to the driving controller. Meanwhile, since the first clock signal CLK1 and the second clock signal CLK2 are interlaced signals, the generated first control signal IS1_ signal and the generated second control signal IS2_ signal are also interlaced signals.

Referring to fig. 6, in detail, the first driving controller includes a first nand gate U12, a third diode D12, and a sixteenth resistor R16, the first clock signal CLK1 IS connected to the first input terminal of the first nand gate U12, the second input terminal of the first nand gate U12, and one end of the sixteenth resistor R16 through the third diode D12, the other end of the sixteenth resistor R16 IS connected to the first control signal IS1_ signal, the positive power terminal of the first nand gate U12 IS connected to the reference voltage VREF, the negative power terminal of the first nand gate U12 IS grounded, and the output terminal of the first nand gate U12 IS connected to the first driving signal DRVA.

The second driving controller comprises a second nand gate U22, a fourth diode D22 and a twenty-sixth resistor R26, the second clock signal CLK2 IS connected with the first input end of the second nand gate U22, the second input end of the second nand gate U22 and one end of the twenty-sixth resistor R26 through the fourth diode D22, the other end of the twenty-sixth resistor R26 IS connected with the second control signal IS2_ signal, the positive power end of the second nand gate U22 IS connected with the reference voltage VREF, the negative power end of the second nand gate U22 IS grounded, and the output end of the second nand gate U22 IS connected with the second driving signal DRVB.

The driving controller adopts logic NAND gate control and is responsible for sending a first driving signal DRVA and a second driving signal DRVB which are mutually alternated. Since the first driving signal DRVA and the second driving signal DRVB are controlled by the first clock signal CLK1, the first control signal IS1_ signal, the second clock signal CLK2, and the second control signal IS2_ signal through a logic nand gate, the negative duty cycles of the first clock signal CLK1 and the second clock signal CLK2 are the maximum duty cycles of the first driving signal DRVA and the second driving signal DRVB, so that the control of the maximum duty cycles IS realized, and the reliability of the control IS ensured.

Since the first clock signal CLK1, the second clock signal CLK2, the first control signal IS1_ signal, and the second control signal IS2_ signal are signals that alternate with each other, the output first driving signal DRVA and the output second driving signal DRVB are two current-type control PWM driving signals that are interleaved with each other and have set frequencies and maximum duty ratios.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

The invention is described above with reference to the accompanying drawings, which are illustrative, and it is obvious that the implementation of the invention is not limited in the above manner, and it is within the scope of the invention to adopt various modifications of the inventive method concept and technical solution, or to apply the inventive concept and technical solution to other fields without modification.