阅读说明：本技术 内存芯片，内存模块以及用来假性存取其记忆库的方法 (Memory chip, memory module and method for pseudo-accessing memory bank of memory chip ) 是由 黄沛杰 姚泽华 于 2019-11-05 设计创作，主要内容包括：本发明提供内存芯片包括多个记忆库,多个地址接脚以及虚拟地址决定电路。所述地址接脚用来接收分别对应所述记忆库的多个地址信号。所述虚拟地址决定电路具有多个输入接脚分别耦接至所述地址接脚,以及多个输出接脚耦接至所述记忆库。当所述内存芯片上电时,所述虚拟地址决定电路对所述记忆库产生虚拟地址表。所述虚拟地址表具有分别对应所述记忆库的多个虚拟地址。本发明也提供内存模块其整合所述内存芯片以及一种用来假性存取所述内存芯片的所述记忆库的方法。(The invention provides a memory chip which comprises a plurality of memory banks, a plurality of address pins and a virtual address decision circuit. The address pins are used for receiving a plurality of address signals respectively corresponding to the memory banks. The virtual address decision circuit has a plurality of input pins respectively coupled to the address pins and a plurality of output pins coupled to the memory banks. When the memory chip is powered on, the virtual address decision circuit generates a virtual address table for the memory bank. The virtual address table has a plurality of virtual addresses respectively corresponding to the memory banks. The invention also provides a memory module which integrates the memory chip and a method for falsely accessing the memory bank of the memory chip.)

1. A memory chip, the memory chip comprising:

a plurality of memory banks;

a plurality of address pins for receiving a plurality of address signals respectively corresponding to the memory banks; and

a virtual address determining circuit having a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, the virtual address determining circuit generates a virtual address table for the memory banks when the memory chip is powered on,

wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the banks, and each of the banks is arranged to be accessed according to the corresponding virtual address.

2. The memory chip of claim 1, wherein the virtual address determination circuit randomly generates the virtual address table for the memory banks.

3. The memory chip of claim 2, wherein the memory chip further comprises:

a controller coupled to the virtual address determination circuit and configured to issue a control signal having an address signal indicating a destination memory bank to which the control signal is to be sent,

wherein the virtual address decision circuit decides the virtual address based on the address signal indicating a destination bank and the virtual address table, and the virtual address decision circuit redirects the control signal to a dummy bank indicated by the virtual address.

4. The memory chip of claim 2, wherein the memory chip further comprises:

a controller coupled to the virtual address determination circuit and configured to issue a control signal having an address signal indicating a destination memory bank to which the control signal is to be sent,

wherein the virtual address decision circuit decides the virtual address based on the address signal indicating a destination bank and the virtual address table, and the controller redirects the control signal to a dummy bank indicated by the virtual address.

5. The memory chip of claim 1, wherein the virtual address determination circuit is disabled in response to a test mode enable signal.

6. A memory module, the memory module comprising:

a printed circuit board;

the control circuit is arranged on the printed circuit board; and

a plurality of memory chips disposed on the printed circuit board and coupled to the control circuit, wherein each of the memory chips includes:

a plurality of memory banks;

a plurality of address pins for receiving a plurality of address signals respectively corresponding to the memory banks; and

a virtual address determination circuit having a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, the virtual address determination circuit generates a virtual address table for the memory banks when the memory chip is powered on,

wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the banks, and each of the banks is arranged to be accessed according to the corresponding virtual address.

7. The memory module of claim 6 wherein the virtual address determination circuit randomly generates the virtual address table for the memory banks.

8. The memory module of claim 7, wherein each of the memory chips further comprises:

a controller coupled to the virtual address determination circuit and configured to issue a control signal having an address signal indicating a destination memory bank to which the control signal is to be sent,

wherein the virtual address decision circuit decides the virtual address based on the address signal indicating a destination bank and the virtual address table, and the virtual address decision circuit redirects the control signal to a dummy bank indicated by the virtual address.

9. The memory module of claim 7, wherein each of the memory chips further comprises:

a controller coupled to the virtual address determination circuit and configured to issue a control signal having an address signal indicating a destination memory bank to which the control signal is to be sent,

wherein the virtual address decision circuit decides the virtual address based on the address signal indicating a destination bank and the virtual address table, and the controller redirects the control signal to a dummy bank indicated by the virtual address.

10. The memory module of claim 6, wherein the virtual address determination circuit is disabled in response to a test mode enable signal.

11. A method for pseudo-accessing a plurality of memory banks of a memory chip, the method comprising:

generating a virtual address table for the memory banks when the memory chip is powered on, wherein the virtual address table is stored in a memory, and each of the memory banks corresponds to a virtual address in the virtual address table;

receiving a control signal having an address signal indicating a destination memory bank to which the control signal is to be transmitted;

determining a virtual address according to the address signal indicating the destination memory bank and the virtual address table; and

redirecting the control signal to a pseudo memory bank indicated by the virtual address.

12. The method of claim 11, wherein the step of generating the virtual address table for the memory banks is performed by randomly generating the virtual address table for the memory banks.

Technical Field

The present invention relates to a memory chip, and more particularly, to a memory chip capable of pseudo-accessing a memory bank.

Background

Random Access Memory (RAM) is a form of calculator data storage for storing currently used data and machine code. Random access memory devices may allow data to be read or written at approximately the same time regardless of the physical location of the data within the memory.

The RAM includes multiplexing and de-multiplexing circuitry for bringing data online to the address memory to read or write entries. Generally, more than one bit of storage can be accessed by the same address.

For practical purposes, the memory cells must be readable and writable. In a RAM device, multiplexing and de-multiplexing circuitry is used to select memory cells. Generally, a RAM device has a set of address lines A0... An, and for each byte pair that may be applied to these address lines, a corresponding set of memory cells may be activated. Due to this addressing mode, RAM devices almost always have a memory capacity of the second power.

Many RAM systems have a hierarchical structure of memory cells, banks, ranks, memory modules, and memory channels. Referring to FIG. 1, a block diagram of a hierarchy of a RAM system is shown. Coupled to one or more memory channels 2 a-2 b by a Central Processing Unit (CPU) 1. Each of the memory channels 2 a-2 b may include a plurality of memory modules 3. Each memory module 3 may have one or two memory ranks 4, which include several memory chips 5. Each memory chip 5 comprises several memory banks 6. The memory bank 6 is formed of a number of memory cells 7 arranged in an array.

Disclosure of Invention

Memory device manufacturers are accustomed to ensuring that their products have a certain age and even life-long security. Warranty years are generally estimated according to the following concept: the memory device can evenly distribute the total number of accessible operations in all the banks of the memory device. In some overly simplified embodiments, an application may have very low memory requirements (much less than the amount of memory that a deployed system can carry) but may require very frequent memory accesses, and such an application may access certain memory banks more frequently than others. Eventually, this will result in early decay of the heavily accessed memory banks.

It is therefore an object of the present invention to provide a memory chip which can falsely access its memory banks to prevent early failure of the memory banks.

To achieve the above objective, according to one aspect of the present invention, a memory chip is provided. The memory chip includes:

a plurality of memory banks;

a plurality of address pins for receiving a plurality of address signals respectively corresponding to the memory banks; and

a virtual address determining circuit having a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, the virtual address determining circuit generates a virtual address table for the memory banks when the memory chip is powered on,

wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the banks, and each of the banks is arranged to be accessed according to the corresponding virtual address.

To achieve the above objective, according to another aspect of the present invention, a memory module is provided. The memory module includes:

a printed circuit board;

the control circuit is arranged on the printed circuit board; and

a plurality of memory chips disposed on the printed circuit board and coupled to the control circuit, wherein each of the memory chips includes:

a plurality of memory banks;

a plurality of address pins for receiving a plurality of address signals respectively corresponding to the memory banks; and

a virtual address determination circuit having a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, the output pins are coupled to the memory banks, the virtual address determination circuit generates a virtual address table for the memory banks when the memory chip is powered on,

wherein the virtual address table has a plurality of virtual addresses respectively corresponding to the banks, and each of the banks is arranged to be accessed according to the corresponding virtual address.

To achieve the above objective, according to another aspect of the present invention, a method for falsely accessing a plurality of banks of a memory chip is provided. The method comprises the following steps:

generating a virtual address table for the memory banks when the memory chip is powered on, wherein the virtual address table is stored in a memory, and each of the memory banks corresponds to a virtual address in the virtual address table;

receiving a control signal having an address signal indicating a destination memory bank to which the control signal is to be transmitted;

determining a virtual address according to the address signal indicating the destination memory bank and the virtual address table; and

redirecting the control signal to a pseudo memory bank indicated by the virtual address.

With these arrangements, the memory chip, the memory module, and the method for falsely accessing the memory banks of the memory chip can change the virtual address table of the memory banks of the memory chip each time the memory chip is powered on. In this way, the frequency of accessing each bank will be evenly distributed across all banks regardless of the design or implementation of the application. In other words, the present invention can prevent the early decay of the memory bank due to the heavy access.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a block diagram of a hierarchy of a conventional RAM system;

FIG. 2 is a block diagram of a memory chip according to an embodiment of the invention;

FIG. 3 is an address table of a memory chip according to an embodiment of the present invention;

FIG. 4 is a table of virtual addresses of a memory chip according to various embodiments of the invention;

FIG. 5 is a table of virtual addresses of a memory chip according to various embodiments of the invention;

FIG. 6 is a block diagram of a memory chip and exemplary virtual address table according to another embodiment of the present invention;

FIG. 7 is a block diagram of a memory chip and exemplary virtual address table according to yet another embodiment of the invention;

FIG. 8 is a memory module according to various embodiments of the invention;

FIG. 9 is a memory module according to various embodiments of the invention;

FIG. 10 is a memory module according to various embodiments of the invention;

FIG. 11 is a flow chart of a method for falsely accessing a memory bank of a memory chip in accordance with an exemplary embodiment of the present invention.

Reference numerals

1 central processing unit

2a, 2b memory channel

3 memory module

4 memory rows

5 memory chip

6 memory bank

7 memory cell

10 memory chip

11. 12, 13, 14 memory bank

15 virtual address decision circuit

26. 36 controller

20. 30 memory chip

40. 50, 60 memory module

41 printed circuit board

42 control circuit

P1, P2 pin

S11, S12, S13, S14, S _ C signals

1100 method

1101. 1102, 1104 and 1106 steps

Detailed Description

The invention will now be described by some preferred embodiments thereof and with reference to the accompanying drawings.

Referring to fig. 2, a block diagram of a memory chip according to an embodiment of the invention is shown. In FIG. 2, the memory chip 10 includes a plurality of banks 11-14, a plurality of address pins P1-P2, and a virtual address determination circuit 15.

The address pins P1-P2 are used to receive the address signals S11-S14 corresponding to the memory banks 11-14, respectively. That is, the address signals S11-S14 constitute 4 possible results of the voltage levels of the address pins P1-P2. Referring to fig. 3, fig. 3 is an address table of the memory chip 10 according to an embodiment of the invention. In FIG. 3, the address signal S11 causes the voltage levels of both position pins P1 and P2 to be relatively high (indicated by the number "1"), the address signal S12 causes the voltage level of address pin P1 to be relatively high and the voltage level of address pin P2 to be relatively low (indicated by the number "0"), the address signal S13 causes the voltage level of address pin P1 to be relatively low and the voltage level of address pin P2 to be relatively high, and the address signal S14 causes the voltage levels of both position pins P1 and P2 to be relatively low. In this embodiment, if a one-bit address signal is received and causes the voltage levels of both address pins P1-P2 to be relatively high, then the address signal S11 is received. The memory chip 10 then determines that the bank 11 is a target bank for the upcoming operation. In the previous embodiment, it was also helpful to consider the location pin P1 as a column address and the address pin P2 as a row bit pin. In other words, the address pins P1 are configured to receive voltage levels for determining which column of the array of banks 11-14 the target bank is located on, and the address pins P2 are configured to receive voltage levels for determining which column of the array of banks 11-14 the target bank is located on. Please note that the number of address pins in this embodiment is for illustrative purposes only and is not meant to be a limitation of the present invention. Modifications and variations may be effected by those skilled in the art, without departing from the spirit of the invention, in light of the practical design and requirements of the application.

Referring again to fig. 2, in fig. 2, the virtual address determining circuit 15 has a plurality of input pins and a plurality of output pins. The input pins of the virtual address determination circuit 15 are coupled to the address pins P1-P2, respectively. The output pins of the virtual address determination circuit 15 are coupled to the memory banks 11-14. In another design, the output pins of the virtual address determination circuit 15 may be coupled to the memory banks 11-14 through a column address controller and a row address controller. In this manner, the output pins coupled to the column address controller will send a column select signal to the column address controller to determine which column of the array of memory banks 11-14 the target memory bank is located on, and the output pins coupled to the row address controller will send a row select signal to the row address controller to determine which row of the array of memory banks 11-14 the target memory bank is located on. In any of the above designs, the signal output from the output interface of the virtual address determination circuit 15 will determine the address of the bank where the operation is to be performed.

In addition, each time the memory chip 10 is powered on, the virtual address determining circuit 15 will generate a virtual address table for the memory banks 11-14. The virtual address table may then be stored in a register and looked up in the register. For example, please refer to fig. 3, fig. 4, and fig. 5 simultaneously. Fig. 4 and 5 illustrate virtual address tables of the memory chip 10 according to various embodiments of the present invention. In the virtual address table of FIG. 4, the virtual address table is generated such that the banks 11-14 correspond to the address signals S11-S14, and the address signals S11-S14 are different row addresses represented by shifts in the banks 11-14 for the address table of FIG. 3. In FIG. 4, the address signal S11 now corresponds to bank 12, the address signal S12 now corresponds to bank 13, the address signal S13 now corresponds to bank 14, and the address signal S14 now corresponds to bank 11. Specifically, the corresponding locations of the banks 11-14 in FIG. 4 are the corresponding locations of the banks 11-14 in FIG. 3 that are "cyclically shifted" one step down. In other words, in the embodiment of FIG. 4, the memory bank 12 can only be accessed by the address signal S13. When the developer intends to access the memory bank 13, he will instead "falsely access" the memory bank 12. In an application in which the memory bank 13 is severely over-accessed, the above-described virtual address voting circuit 15 generated from the virtual address would secretly shift some of the operational burden of the memory bank 13 to the memory bank 12 without any further configuration, so that this approach can prevent the memory bank 13 from being prematurely worn out. The virtual address determination circuit 15 generates a new virtual address table each time the memory chip 10 is powered on. This will distribute the load of the memory bank 13 that should otherwise be heavily accessed to another memory bank.

In fig. 5, the virtual address table is randomly generated by the virtual address decision circuit 15. For example, the virtual address table is generated by copying the address table and then replacing the row addresses of the banks 11-14 indicating the copied address table with the randomly ordered row addresses of the banks 11-14. Statistically, if the virtual address is randomly generated when the iteration of the virtual address increases, the reliability of the memory chip 10 will increase.

Referring now to FIG. 6, shown is a block diagram of a memory chip and an exemplary virtual address table in accordance with another embodiment of the present invention. Note that the memory chip 20 shares some components with the memory chip 10. If the components in the memory chip 20 are substantially the same as the components in the memory chip 10, the same symbols will be used to avoid confusion. In fig. 6, the memory chip 20 further includes a controller 26. The controller 26 is coupled to the virtual address determining circuit 15 and is configured to issue a control signal S _ C having an address signal indicating a destination memory bank to which the control signal S _ C is to be sent. For example, the controller 26 is about to write data to the memory bank 11. The controller 26 issues a control signal S _ C indicating a write operation and the address signal S11 indicating that the target memory bank is the memory bank 11. In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11, i.e., the memory bank 13, according to the location signal S11 and the virtual address table of FIG. 6. The virtual address determination circuit 15 then redirects the control signal S _ C to the memory bank 13.

Referring to FIG. 7, a block diagram of a memory chip and an exemplary virtual address table according to yet another embodiment of the invention is shown. Note that a memory chip 30 shares some components with the memory chips 10 and 20. If the components in the memory chip 30 are substantially the same as the components in the memory chips 10 and 20, the same symbols are used to avoid confusion. In fig. 7, the memory chip 30 further includes a controller 36. The controller 36 is coupled to the virtual address determination circuit 15 and the memory banks 11-14. The controller 36 is configured to issue a control signal S _ C having an address signal indicating a destination memory bank to which the control signal S _ C is to be sent. In this embodiment, the address signal indicating the destination bank is sent to the virtual address decision circuit 15. The virtual address determining circuit 15 determines a virtual address according to the received address signal and the virtual address table, and sends the address signal corresponding to the virtual address back to the controller 36. The controller 36 then redirects the control signal S _ C to the dummy memory bank indicated by the virtual address. For example, the controller 26 is about to write data to the memory bank 11. The controller 36 issues a control signal S _ C indicating a write operation and the address signal S11 indicating that the destination bank is the bank 11. In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11, i.e., the memory bank 14, according to the location signal S11 and the virtual address table of FIG. 7. The virtual address determination circuit 15 then sends the address signal S14 back to the controller 36. The controller 36 then redirects the control signal S _ C to the memory bank 14.

The memory chips 10,20 and 30 may be further incorporated into a memory module. Referring to fig. 8, a memory module according to an embodiment of the invention is shown. In fig. 8, the memory module 40 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 10. The control circuit 42 is disposed on the printed circuit board 41 and is used to select a target memory chip 10. The memory chips 10 are disposed on the printed circuit board 41 and connected to the control circuit 42. The structure and operation of the memory chips 10 can be found in the above paragraphs. A detailed description will be omitted herein for the sake of brevity.

Referring to fig. 9, a memory module according to an embodiment of the invention is shown. Note that the memory module 50 shares some components with the memory module 40. If the components in the memory module 40 are substantially identical to the components in the memory module 50, they will be denoted by the same symbols to avoid confusion. In fig. 9, the memory module 50 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 20. The structure and operation of the memory chips 20 can be found in the above paragraphs. A detailed description will be omitted herein for the sake of brevity.

Referring to fig. 10, a memory module according to an embodiment of the invention is shown. Note that the memory module 60 shares some components with the memory modules 40 and 50. If the components in the memory module 60 are substantially identical to the components in the memory modules 40 and 50, the same symbols will be used to avoid confusion. In fig. 10, the memory module 60 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 30. The structure and operation of the memory chips 30 can be found in the above paragraphs. A detailed description will be omitted herein for the sake of brevity.

The virtual address determining circuit 15 may also be disabled by a test mode enable signal. When testing the reliability of the memory chip 10, it is critical that the tester be able to test the actual target bank without spurious accesses. Disabling the virtual address determination circuit 15 using a test mode enable signal provides flexibility in the application of the memory chip 10,20 or 30.

Referring to fig. 11, fig. 11 is a flowchart illustrating a method for falsely accessing a memory bank of a memory chip according to an exemplary embodiment of the invention. If the results are substantially the same, the steps need not be performed in the exact order shown in FIG. 11. The exemplary method may be implemented by the memory chip 10 shown in fig. 2, the memory chip 20 shown in fig. 6, the memory chip 30 shown in fig. 7, the memory module 40 in fig. 8, the module 50 in fig. 9, and the memory module 60 in fig. 10. The steps of the method can be summarized as follows.

Step 1101: when the memory chip is powered on, a virtual address table is generated for the memory.

Step 1102: a control signal is received, wherein an address signal is provided which indicates a destination memory bank to which the control signal is to be sent.

Step 1104: a virtual address indicating a destination bank and the virtual address table are determined according to the address signal.

Step 1106: the control signal is redirected to the dummy memory bank indicated by the virtual address.

In the method 1100, the virtual address table is stored in a memory, and each of the banks corresponds to a virtual address in the virtual address table. Step 1101 may be performed by the virtual address determining circuit 15 of the memory chip 10,20 or 30. Step 1102 may be performed by the virtual address decision circuit 15. The address signal is issued by the controller 26 or step 1104 may be performed by the virtual address determination circuit 15 of the memory chip 10,20 or 30. Step 1106 may be performed by the virtual address determination circuit 15 or the controller 26 or 36.

The present invention has been described above with reference to some preferred embodiments thereof, and it should be understood that the preferred embodiments are illustrative only and are not intended to be limiting of the invention in any way, and that many changes and modifications may be made without departing from the embodiments of the invention. The scope and spirit of the present invention are intended to be limited only by the appended claims.