阅读说明：本技术 一种基于GaN HEMT的开关集成芯片与制作方法 (Switch integrated chip based on GaN HEMT and manufacturing method ) 是由 樊永辉 许明伟 樊晓兵 于 2021-01-15 设计创作，主要内容包括：本申请实施例公开了一种基于氮化镓高电子迁移率晶体管GaN HEMT的开关集成芯片与制作方法,包括：提供硅基GaN晶圆(包括硅基衬底和GaN外延层X),GaN外延层X包括目标区域GaN外延层X1和非目标区域GaN外延层X2；采用刻蚀工艺去除非目标区域GaN外延层X2,在硅基衬底的上端面形成用于制作Si CMOS开关控制电路的Si CMOS器件区域；在目标区域GaN外延层X1上形成用于制作GaN HEMT开关电路的GaN HEMT器件区域。采用本申请实施例的方法,实现了在同一芯片上集成制作GaN HEMT开关电路和Si CMOS开关控制电路,提升器件集成度、减小芯片面积和成本、提升器件性能。(The embodiment of the application discloses a switch integrated chip based on a GaN HEMT and a manufacturing method thereof, wherein the switch integrated chip comprises the following steps: providing a silicon-based GaN wafer (comprising a silicon-based substrate and a GaN epitaxial layer X), wherein the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2; removing the GaN epitaxial layer X2 in the non-target region by adopting an etching process, and forming a Si CMOS device region for manufacturing a Si CMOS switch control circuit on the upper end surface of the silicon substrate; a GaN HEMT device region for fabricating a GaN HEMT switching circuit is formed on the target region GaN epitaxial layer X1. By adopting the method of the embodiment of the application, the GaN HEMT switch circuit and the Si CMOS switch control circuit are integrally manufactured on the same chip, the integration level of a device is improved, the area and the cost of the chip are reduced, and the performance of the device is improved.)

1. A method for manufacturing a switch integrated chip based on a gallium nitride high electron mobility transistor (GaN HEMT), the switch integrated chip comprising a switch circuit based on the GaN HEMT and a Complementary Metal Oxide Semiconductor (CMOS) switch control circuit based on a silicon process, the method comprising:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are adjacently arranged;

removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit;

forming a GaN HEMT device region on the target region GaN epitaxial layer X1, wherein the GaN HEMT device region is used for manufacturing a GaN HEMT switch circuit.

2. The method of claim 1, wherein the Si CMOS switch control circuit comprises at least one PMOS transistor and at least one NMOS transistor, and wherein the manufacturing the Si CMOS switch control circuit comprises:

generating an N well and a P well on the silicon-based substrate by adopting a double-well process, wherein the positions of the N well and the P well correspond to the positions of each PMOS tube in the at least one PMOS tube and each NMOS tube in the at least one NMOS tube;

manufacturing a grid electrode on the silicon-based substrate according to the grid electrode position of each PMOS tube and each NMOS tube, and forming an active region on the silicon-based substrate according to the source electrode position and the drain electrode position of each PMOS tube and each NMOS tube;

forming a contact hole on the silicon-based substrate by using a mask, wherein the contact hole is in contact with the N well and the P well;

and performing at least one layer of metal interconnection process for forming pins on the contact holes for electrical connection.

3. The method of claim 1 or 2, wherein the GaN HEMT switching circuit includes a field effect transistor therein, the method further comprising: implementing a GaN HEMT device process on the GaN HEMT device region to manufacture a GaN HEMT switch circuit, comprising:

etching a groove on the target region GaN epitaxial layer X1 to form a source electrode and a drain electrode of the field effect transistor;

etching a grid groove on the target region GaN epitaxial layer X1, depositing a passivation layer Z and a metal layer G1 on the upper end face of the grid groove to form a grid, arranging a dielectric layer Y between the metal layer G1 and the passivation layer Z, and forming a pin by using the metal layer G1 for electric connection.

4. The method according to claim 3, characterized in that the passivation layer Z is Si3N4 or SiO 2.

5. The method of claim 3, wherein the gate is T-shaped or Y-shaped.

6. The method of claim 3, wherein the GaN HEMT switch circuit based on the GaN HEMT region and the Si CMOS switch control circuit based on the Si CMOS region are turned on by a metal interconnect process.

7. The method of claim 1, wherein the switch integrated chip further has integrated thereon an input matching circuit and/or an output matching circuit.

8. The method of claim 1, wherein the GaN epitaxial layer X comprises at least one of:

the nucleation layer is used for providing a film growth environment of the channel layer;

the transition layer is used for filling transition materials and realizing lattice adaptation between the GaN epitaxial layer X and the silicon-based substrate material and reducing stress;

a channel layer including a GaN crystal thin film;

the isolation layer is used for limiting the upward movement of electrons and improving the density of the two-dimensional electron gas;

a barrier layer for supplying electrons to the channel layer;

a cap layer for preventing oxidation of the barrier layer.

9. The method of claim 8,

the thickness of the nucleating layer is 1-10 nm;

the thickness of the transition layer is 0.5-4 um;

the thickness of the channel layer is 0.1-1 um;

the thickness of the isolation layer is 0.2-2 nm;

the thickness of the barrier layer is 10-50 nm;

the thickness of the cap layer is 2-10 nm.

10. A GaN HEMT-based switch integrated chip, the switch integrated chip comprising:

the silicon-based GaN wafer comprises a silicon-based substrate, wherein the silicon-based substrate comprises a Si CMOS device region, and a Si CMOS switch control circuit is loaded on the Si CMOS device region;

the silicon-based substrate further comprises a GaN epitaxial layer X and a GaN HEMT device region arranged above the GaN epitaxial layer X, and the GaN HEMT device region is loaded with a GaN HEMT switch circuit;

the Si CMOS device region and the GaN HEMT device region are arranged adjacent to each other, and the Si CMOS device region and the GaN HEMT device region are manufactured according to the method of claim 1.

11. The switching integrated chip of claim 10, wherein the Si CMOS switch control circuit and the GaN HEMT switch circuit are fabricated according to the method of any one of claims 2-6.

12. The switch integrated chip of claim 10 or 11, wherein the silicon-based substrate is a p-type silicon substrate, a high resistance silicon substrate, or a silicon-on-insulator (SOI) substrate, and the silicon-based substrate has a size of 3-12 feet.

13. The switch integrated chip of any one of claims 10-12, further integrated with an input matching circuit and/or an output matching circuit.

14. The switch integrated chip of claim 13, wherein the GaN HEMT switch circuit, the Si CMOS switch control circuit, the input matching circuit, and the output matching circuit are electrically connected by metal wires to form a loop.

Technical Field

The application relates to the field of chip manufacturing, in particular to a switch circuit chip and a control circuit chip, and particularly relates to a switch integrated chip based on a gallium nitride high electron mobility transistor (GaN HEMT) and a manufacturing method thereof.

Background

With the advent of the 5G era, terminal products have higher requirements for radio frequency systems of devices: high integration, miniaturization, high performance, etc. The Si CMOS switch control circuit has the advantages of low power consumption, wide voltage range, strong anti-interference capability and the like, and is widely applied in manufacturing due to high integration level and low cost. The GaN HEMT based on the gallium nitride has the advantages of high output power, high efficiency, high switching frequency, high breakdown voltage and the like, so that the GaN HEMT switching circuit has the advantages of high switching speed, high working voltage, low driving loss and the like, and becomes a core switching circuit in the field of wireless communication and the field of power electronic application at present.

Disclosure of Invention

The embodiment of the application provides a switch integrated chip and a manufacturing method based on a GaN HEMT (high electron mobility transistor), which realize the integrated manufacturing of a GaN HEMT switch circuit and a Si CMOS switch control circuit on the same chip, ensure the overall performance of a chip device, reduce the area of the chip, save the cost of a terminal product and further meet the application requirements in the fields of 5G communication and power electronics.

In a first aspect, an embodiment of the present application provides a method for manufacturing a switching integrated chip based on a GaN HEMT, where the switching integrated chip includes a switching circuit based on a GaN HEMT and a CMOS control circuit based on a silicon process, and the method for manufacturing the switching integrated chip includes:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are adjacently arranged;

removing the GaN epitaxial layer X2 in the non-target region by adopting an etching process, so that a Si device region is formed on the upper end surface of the silicon substrate, and the Si device region is used for manufacturing a Si CMOS switch control circuit;

a GaN HEMT device region for fabricating a GaN HEMT switching circuit is formed on the target region GaN epitaxial layer X1.

In a second aspect, an embodiment of the present application provides a switch integrated chip based on a GaN HEMT, where the switch integrated chip includes:

the silicon-based GaN wafer comprises a silicon-based substrate, wherein the silicon-based substrate comprises a Si CMOS device region, and the Si CMOS device region is loaded with a Si CMOS switch control circuit;

the silicon-based substrate further comprises a GaN epitaxial layer X and a GaN HEMT device region arranged above the GaN epitaxial layer X, and the GaN HEMT device region is loaded with a GaN HEMT switch circuit;

the Si CMOS device region and the GaN HEMT device region are disposed adjacent to each other, and the Si CMOS device region and the GaN HEMT device region are fabricated according to the method for fabricating a switch integrated chip based on a GaN HEMT as described in the first aspect, and the specific method is as follows:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are adjacently arranged;

removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit;

a GaN HEMT device region for fabricating a GaN HEMT switching circuit is formed on the target region GaN epitaxial layer X1.

In a third aspect, embodiments of the present application provide a device manufacturing system, including: the GaN-based HEMT switch integrated chip comprises a processor, a memory and a communication interface, wherein one or more programs are stored in the memory, and the processor executes the one or more programs, and the programs comprise instructions for executing part or all of the steps in the manufacturing method embodiment of the GaN-based HEMT switch integrated chip.

In a fourth aspect, the embodiments of the present application provide a GaN HEMT-based switch integrated chip manufacturing apparatus, applied to a device manufacturing system for manufacturing a GaN HEMT-based switch integrated chip, the manufacturing apparatus including a processing unit and a communication unit,

wherein the processing unit is configured to:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are arranged adjacently;

removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit;

forming a GaN HEMT device region on the target region GaN epitaxial layer X1, wherein the GaN HEMT device region is used for manufacturing a GaN HEMT switching circuit;

the communication unit is used for receiving data input from the outside to the switch integrated chip manufacturing device based on the GaN HEMT and sending the data to the processing unit so that the processing unit can execute part or all of the steps of the manufacturing method.

In a fifth aspect, embodiments of the present application provide a computer program product, where the computer program product comprises a computer program, and the computer program is operable to execute some or all of the steps described in any of the methods of the first aspect of the embodiments of the present application.

It can be seen that, in the embodiment of the present application, the switch integrated chip includes a GaN HEMT device region for manufacturing the GaN HEMT switch circuit and a Si CMOS device region for manufacturing the Si CMOS switch control circuit, and the switch integrated chip is formed with the GaN HEMT device region and the Si CMOS device region at the same time, so that the integration level of the switch integrated chip can be increased, the chip area is reduced, the manufacturing cost is reduced, the overall performance of the device is improved, and the application capability of the switch integrated chip in a power electronic system and a wireless communication radio frequency system is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1A is a schematic diagram of a switching circuit;

FIG. 1B is a schematic diagram of the operating principle of a switch;

fig. 1C is a schematic flowchart of a method for manufacturing a switch integrated chip based on a GaN HEMT disclosed in an embodiment of the present application;

fig. 1D is a schematic structural diagram of a silicon-based GaN wafer provided in a process for manufacturing a GaN HEMT-based switch integrated chip disclosed in an embodiment of the present application;

fig. 1E is a schematic structural diagram of a GaN epitaxial layer X disclosed in an embodiment of the present application;

fig. 1F is a schematic diagram of an intermediate process of a manufacturing process of a GaN HEMT-based switch integrated chip disclosed in an embodiment of the present application;

fig. 1G is a schematic diagram of an intermediate process of a manufacturing process of a GaN HEMT-based switch integrated chip disclosed in an embodiment of the present application;

fig. 2A is a schematic flow chart of a method for fabricating a Si CMOS switch control circuit on a Si CMOS device region according to an embodiment of the present application;

FIG. 2B is a schematic diagram of a Si CMOS circuit according to an embodiment of the present disclosure;

FIG. 2C is a schematic structural diagram of a Si CMOS circuit disclosed in the embodiments of the present application;

fig. 3A is a schematic flow chart of a method of fabricating a GaN HEMT switch circuit on a GaN HEMT device region as disclosed in embodiments of the present application;

fig. 3B is a schematic structural diagram of a gate disclosed in the embodiment of the present application;

fig. 3C is a schematic structural diagram of a GaN HEMT switching circuit disclosed in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a switch integrated chip based on a GaN HEMT disclosed in an embodiment of the present application;

FIG. 5 is a schematic diagram of an apparatus for integrating a GaN monolithic microwave integrated circuit and a Si CMOS switch control circuit on the same chip according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a device manufacturing system according to an embodiment of the disclosure.

Fig. 7 is a block diagram of functional units of a device for manufacturing a switch integrated chip based on a GaN HEMT disclosed in an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps is not limited to only those steps recited, but may alternatively include other steps not recited, or may alternatively include other steps inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

GaN is a typical representative of third-generation semiconductors, and compared with first-generation (silicon and germanium) and second-generation semiconductor materials (gallium arsenide and indium phosphide), the third-generation semiconductor material has superior properties such as a large forbidden band width, a high breakdown electric field, a high thermal conductivity, a large electron saturation velocity, and a high radiation resistance, so that a semiconductor device prepared by using the third-generation semiconductor material gallium nitride can stably operate at a higher temperature, and a working state at a high voltage is stable, and a higher operation capability can be obtained with less power consumption.

Since GaN devices have significant technical advantages in power management, power generation and power output. The method is more and more widely applied to the fields of power electronics and radio frequency communication. In particular, due to the high efficiency, low loss and high frequency of GaN, GaN is widely used in the field of power electronics; due to the high efficiency, large bandwidth and high power of GaN, GaN is widely applied in the field of radio frequency.

High electron mobility transistors based on GaN materials are an emerging technology, mainly aimed at high power applications such as radio frequency, microwave and millimeter wave frequencies. Based on the advantages of GaN, GaN HEMT devices have shown their performance advantages in processing, amplifying and delivering high power signals, thus applying GaN HEMT switching circuits in broadband amplifiers, wireless infrastructure applications, voltage controlled oscillators. With the development of the technology, the application range of the GaN HEMT switching circuit will be wider and wider. With the advent of the 5G communications era and the popularity of handheld mobile devices, GaN has gradually replaced the once dominant gallium arsenide in the rf front-end industry today based on GaN performance and cost considerations.

The radio frequency switch is a key device in a radio frequency front-end chip and has the function of communicating any one or more signal paths in a plurality of radio frequency signals through control logic, so that different signal paths are switched, and the aim of saving the cost of a terminal product is fulfilled.

The main product types of the radio frequency switch include a mobile communication conduction switch, a WiFi switch, an antenna tuning switch and the like, and the radio frequency switch is widely applied to mobile intelligent terminals such as smart phones. In order to meet the requirement of 5G communication, antenna theory and radio frequency bands are newly added in a transceiving system, the using number of switches is greatly increased, and the performance requirement of the switches is more strict.

In the existing technical scheme, a switch circuit and a control circuit in a switch are separately manufactured, that is, a GaN HEMT switch circuit and a Si CMOS switch control circuit are separately manufactured.

Referring to fig. 1A, as shown in fig. 1A, a switching circuit is schematically illustrated, wherein a first gan hemt Q1 is controlled by a control voltage V1, and a second gan hemt Q2 is controlled by a control voltage V2; and a control voltage V1 and a control voltage V2, one of which is zero and the other is negative and lower than the pinch-off voltage of the transistor, under the condition that the port 1 is connected to the common port through the low on-resistance of the GaN HEMT, and the other port 2 is in the pinch-off mode, and is isolated from the common port through the large drain-source resistance value, so that the function of the switch is achieved. The switch circuit further comprises a first resistor R1 and a first capacitor C1 which are connected with the first gallium nitride high electron mobility transistor Q1, and a second resistor R2 and a second capacitor C2 which are connected with the second gallium nitride high electron mobility transistor Q2.

Referring to fig. 1B, fig. 1B is a schematic diagram illustrating an operating principle of a radio frequency switch, where the radio frequency switch includes a switch circuit and a control circuit, where the control circuit includes a power voltage VCC, a ground GND, a first not gate, a second not gate, a first control terminal 1, and a second control terminal 2, and the control circuit is connected to a TTL level control and a dc voltage VDC. In fig. 1B, a single pole double throw Switch (SPDT Switch) is taken as an example, and the core of the Switch is the aforementioned GaN HEMT. Under the action of TTL level control, VDC of 0V is converted into-5V, and acts on the grid electrode of the GaN HEMT to turn off the grid electrode; VDC, 5V, is then converted to 0V, acting on the gate of the GaN HEMT to turn it on.

The on and off conditions of the GaN HEMT SPDT switch driven by the CMOS circuit are shown in table 1:

TABLE 1

Control terminal 1	Control terminal 2	Port 1	Port 2
				TTL Low	TTL height	Conduction of	Switch off
TTL height	TTL Low	Switch off	Conduction of

It is seen that, in view of the superior performance of GaN HEMT switching circuits and the increasing demand for GaN HEMT switching circuits, it becomes important to reduce the area of the rf switching chip carrying the GaN HEMT switching circuits, save PCB space, and reduce the cost of the terminal products, especially for the rf switching system integrated with the switching control circuit based on the CMOS process.

Based on this, the embodiment of the present application provides a switch integrated chip based on a GaN HEMT and a manufacturing method thereof, and specifically, a GaN HEMT switch circuit and a Si CMOS switch control circuit are integrated on the same chip, and the embodiment of the present application is described in detail below with reference to the accompanying drawings.

The switch integrated chip includes a switch circuit based on a gallium nitride high electron mobility transistor (GaN HEMT) and a Complementary Metal Oxide Semiconductor (CMOS) control circuit based on a silicon process, specifically referring to fig. 1C, where fig. 1C is a schematic flow chart of a method for manufacturing the switch integrated chip based on the GaN HEMT according to an embodiment of the present application, as shown in fig. 1C, the method includes, but is not limited to, the following steps:

101: providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are arranged adjacently.

Referring to fig. 1D, fig. 1D is a schematic structural diagram of a silicon-based GaN wafer provided in a manufacturing process of a switch integrated chip based on a GaN HEMT according to an embodiment of the present invention, as shown in fig. 1D, wherein a size of the silicon-based substrate may be 3 to 12 feet.

The GaN epitaxial layer X includes at least one of the following, specifically referring to fig. 1E, where fig. 1E is a schematic structural diagram of a GaN epitaxial layer X provided in an embodiment of the present application, and the embodiment of the present application is described in detail below with reference to the accompanying drawings, as shown in fig. 1E:

1011: the nucleation layer is used for providing a film growth environment of the channel layer;

1012: the transition layer is used for filling transition materials and realizing lattice adaptation between the GaN epitaxial layer X and the silicon-based substrate material and reducing stress;

1013: a channel layer including a GaN crystal thin film;

1014: the isolation layer is used for limiting the upward movement of electrons and improving the density of the two-dimensional electron gas;

1015: a barrier layer for supplying electrons to the channel layer;

1016: and the cap layer is used for preventing the oxidation of the barrier layer.

Wherein, the thickness of the nucleation layer can be 1-10 nm;

the thickness of the transition layer can be 0.5-4 um;

the thickness of the channel layer can be 0.1-1 um;

the thickness of the isolation layer may be 0.2-2 nm;

the barrier layer may have a thickness of 10-50 nm;

the cap layer may have a thickness of 2-10 nm.

Wherein, the material of the nucleation layer is a layer of nitride film, including AlN or GaN, and the nucleation layer is manufactured at the temperature of 500-700 ℃; the material of the transition layer comprises AlGaN or other binary, ternary and quaternary nitrides; the manufacturing methods of the nucleation layer, the channel layer, the isolation layer and the barrier layer comprise an organic metal chemical vapor deposition method; the barrier layer is AlGaN or other binary, ternary and quaternary nitrides.

The GaN epitaxial layer X may have only a part or all of the above-described layered structure, but the arrangement order of the layered structures needs to be arranged in the top-bottom order positional relationship as shown in fig. 1E, and exemplarily, a transition layer needs to be located between the channel layer and the silicon-based substrate.

102: and removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit.

103: a GaN HEMT device region for fabricating a GaN HEMT switching circuit is formed on the target region GaN epitaxial layer X1.

For example, referring to fig. 1F in detail, fig. 1F is a schematic diagram of an intermediate process of a manufacturing process of a switch integrated chip based on a GaN HEMT according to an embodiment of the present invention, as shown in fig. 1F, a GaN epitaxial layer X is grown on a silicon-based substrate, the GaN epitaxial layer X includes a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are adjacently disposed, and a photolithography process including steps of glue coating, alignment, exposure, development and the like is first performed, so that the target region GaN epitaxial layer X1 is covered with a photoresist, and the non-target region GaN epitaxial layer X2 is not covered with a photoresist. And removing the GaN epitaxial layer X2 of the non-target region without the photoresist coverage by adopting an etching process so as to expose the silicon-based substrate, further forming a Si CMOS device region for manufacturing a Si CMOS switch control circuit on the upper end surface of the silicon-based substrate, and removing the photoresist coverage on the GaN epitaxial layer X1 of the target region by adopting a photoresist removing process so as to form a GaN HEMT device region for manufacturing a GaN HEMT switch circuit on the GaN epitaxial layer X1 of the target region.

The etching of the GaN epitaxial layer X generally adopts a dry etching process, i.e., is performed in a plasma etching apparatus, such as Reactive Ion Etching (RIE), electron cyclotron resonance plasma (ECR), Inductively Coupled Plasma (ICP), and the like. The plasma etching GaN material gas source generally uses Cl2, BCl3, SiCl4, I2, Br2, CH4, SF6, etc. as gas sources, and mixes with Ar, H2, N2, etc. as etching reaction gases, and can achieve the best etching effect by selecting a proper etching reaction gas and a proper mixture ratio of the etching reaction gases.

Referring to fig. 1G, fig. 1G is a schematic diagram of an intermediate process of a manufacturing process of a switch integrated chip based on a GaN HEMT according to an embodiment of the present invention, as shown in fig. 1G, wherein the photoresist stripping process means that photoresist remaining after etching, which is no longer used as a protective layer, needs to be removed from the GaN epitaxial layer X, and the photoresist stripping process may be a wet photoresist stripping process. For example, by spraying a cleaning solution to the photoresist, the photoresist remaining after etching is removed from the GaN epitaxial layer X, thereby forming a GaN HEMT device region for fabricating a GaN HEMT switching circuit.

Illustratively, the cleaning solution for removing the photoresist left after etching is a mixture of hydrogen peroxide and a sulfuric acid solution, and the hydrogen peroxide and sulfuric acid generate an exothermic reaction to form a high-temperature cleaning solution, and the high-temperature cleaning solution is sprayed on the surface of the photoresist left after etching, so that the photoresist left after etching can be removed from the GaN epitaxial layer X; and then, washing the surface of the silicon-based GaN wafer without the photoresist by using deionized water to finish the cleaning work, so that a GaN HEMT device region is formed on the upper end surface of the GaN epitaxial layer X.

Therefore, in the embodiment of the application, the switch integrated chip comprises a GaN HEMT device region for manufacturing the GaN HEMT switch circuit and a Si CMOS device region for manufacturing the Si CMOS switch control circuit, and the switch integrated chip is simultaneously provided with the GaN HEMT device region and the Si CMOS device region, so that the integration level of the switch integrated chip can be increased, the area of the chip is reduced, the manufacturing cost is reduced, the overall performance of the device is improved, and the application capability of the switch integrated chip in a power electronic system and a wireless communication radio frequency system is further improved.

In a possible example, a Si CMOS switch control circuit is carried by a Si CMOS device region formed on an upper end surface of a silicon substrate, and the Si CMOS switch control circuit includes at least one PMOS transistor and at least one NMOS transistor, where the number of the PMOS transistors is the same as the number of the NMOS transistors, and the following detailed description of the embodiments of the present application is provided with reference to the accompanying drawings, specifically referring to fig. 2A, fig. 2A is a schematic flow chart of a method for manufacturing the Si CMOS switch control circuit on the Si CMOS device region according to the embodiments of the present application, and as shown in fig. 2A, a process for manufacturing the Si CMOS switch control circuit includes:

201: and generating an N well and a P well on the silicon substrate by adopting a double-well process, wherein the positions of the N well and the P well correspond to the positions of each PMOS tube in the at least one PMOS tube and each NMOS tube in the at least one NMOS tube.

The double-well process is used for manufacturing a PMOS tube and an NMOS tube on the same silicon substrate, an N-well is formed on the silicon substrate by using an N-well mask, and the N-well is used for manufacturing the PMOS tube; and forming a P well in a non-N well region on the silicon substrate by using a P well mask plate for manufacturing an NMOS tube.

202: manufacturing a grid electrode on the silicon-based substrate according to the grid electrode position of each PMOS tube and each NMOS tube, and forming an active region on the silicon-based substrate according to the source electrode position and the drain electrode position of each PMOS tube and each NMOS tube;

the gate can be made by a polysilicon gate structure. Illustratively, impurities and a formed oxide layer which are contaminated by a silicon-based substrate due to exposure in the air are cleaned, the cleaned silicon-based substrate is placed into an oxidation furnace to grow a layer of silicon dioxide, the silicon-based substrate is transferred into low-pressure chemical vapor deposition equipment which is communicated with silane, a layer of polycrystalline silicon structure is deposited and formed on the silicon-based substrate through the decomposition effect of the silane, the polycrystalline silicon structure is etched by adopting a photoetching process, and the etched polycrystalline silicon structure is etched, so that the polycrystalline silicon gate with the vertical section is obtained.

The active region is a region covered by the source electrode, the drain electrode and the conductive channel, and the active region normally works under the action of an externally applied proper bias voltage.

203: forming a contact hole on the silicon-based substrate by using a mask, wherein the contact hole is in contact with the N well and the P well;

wherein the contact holes are formed to form metal contacts in active areas on the silicon-based substrate, which can tightly bond the silicon-based substrate and a subsequently deposited metal layer G2.

204: and performing at least one layer of metal interconnection process for forming pins on the contact holes for electrical connection.

The metal interconnection process is to form a metal film on the contact hole by using a metal material to perform a metal deposition process, and to form wiring by performing corrosion processing on the metal film by using a photoetching process, so that pins are formed for electrical connection. The metal deposition process may employ evaporation, sputtering, chemical deposition, and the like. The metal material used for forming the metal thin film is required to be a metal material which has low resistivity, can form a good low ohmic contact with an electrode of an element, has good adhesion to SiO2, and facilitates metal deposition and photolithography processes, and for example, the metal material may be aluminum, copper, platinum, or the like.

Referring to fig. 2B, fig. 2B is a schematic diagram illustrating a Si CMOS circuit according to an embodiment of the present disclosure, as shown in fig. 2B, the CMOS circuit includes at least one PMOS transistor Qp and at least one NMOS transistor Qn, a voltage Vi at an input end is commonly connected to a gate of the PMOS transistor Qp and a gate of the NMOS transistor Qn, a drain of the PMOS transistor Qp is connected to a power supply voltage VDD, a source of the NMOS transistor Qn is grounded, and a voltage Vo at an output end is commonly connected to a source of the PMOS transistor Qp and a drain of the NMOS transistor Qn.

Referring to fig. 2C, fig. 2C is a schematic structural diagram of a Si CMOS circuit according to an embodiment of the present disclosure, as shown in fig. 2C, a P-well and an N-well are formed in a silicon substrate, the P-well has P + ions and N + ions, the N-well also has P + ions and N + ions, a metal layer G2 is formed on a contact hole, and the metal layer G2 is connected as a pin to an input terminal voltage Vi, an output terminal voltage Vo, a device power source terminal voltage VDD, and a ground.

Illustratively, aluminum is used as a material of a metal interconnection process, aluminum is formed into a metal aluminum film through a sputtering method, so as to form an interconnection lead of a circuit, and the chemical formula of the formed aluminum film is as follows: 3SiO2+4Al → 3Si +2Al2O3, it can be seen that Al and SiO2 generate Si and Al2O3 through chemical reaction, SiO2 on the surface of the silicon-based substrate is consumed, ohmic contact resistance between Al and Si is reduced, and meanwhile, the adhesion between Al lead and SiO2 in the integrated circuit is improved by the action of Al and SiO 2.

In a possible example, a GaN HEMT device region carries a GaN HEMT switching circuit, the GaN HEMT switching circuit includes a field effect transistor, the following detailed description of the embodiments of the present application is provided with reference to the accompanying drawings, please refer to fig. 3A, where fig. 3A is a schematic flow chart of a method for manufacturing the GaN HEMT switching circuit on the GaN HEMT device region according to the embodiments of the present application, and as shown in fig. 3A, the method for manufacturing the GaN HEMT switching circuit includes:

301: and etching grooves on the target region GaN epitaxial layer X1 to form a source electrode and a drain electrode of the field effect transistor.

Among them, the source and drain electrodes are generally alloyed by a metal composition including titanium, aluminum, nickel, gold through high temperature annealing to reduce the resistance value. Specifically, the metal composition is deposited layer by layer on the upper end surface of the GaN epitaxial layer X by a metal evaporation method.

302: etching a grid groove on the target region GaN epitaxial layer X1, depositing a passivation layer Z and a metal layer G1 on the upper end face of the grid groove to form a grid, arranging a dielectric layer Y between the metal layer G1 and the passivation layer Z, and using the metal layer G1 to form a pin for electric connection.

Referring to fig. 3B, fig. 3B is a schematic structural diagram of a gate according to an embodiment of the present disclosure, as shown in fig. 3B, a plurality of passivation layers may further be disposed on the passivation layer Z, and a plurality of metal layers may further be disposed on the metal layer G1. The grid generally comprises metals such as titanium, gold, platinum, titanium, aluminum and the like, a grid groove is formed on the GaN epitaxial layer X by adopting an etching method, and then the metals such as titanium, gold, platinum, titanium, aluminum and the like are deposited on the silicon-based substrate layer by a metal evaporation method; the shape of the grid can be rectangular, T-shaped or Y-shaped; the GaN HEMT device also includes other elements.

Referring to fig. 3C, fig. 3C is a schematic structural diagram of a GaN HEMT switching circuit according to an embodiment of the present application, in which the GaN HEMT operates in a depletion mode or an enhancement mode.

Alternatively, the GaN HEMT device is looped with a thin film resistor, capacitor, and inductor through metal wiring to make a monolithic integrated circuit. A dielectric layer Y is arranged between the metal layer G1 and the passivation layer Z, and the dielectric layer Y can be SiNx, SiO2, Al2O3 and the like.

In one possible example, the passivation layer Z is Si3N4 or SiO 2.

In one possible example, the shape of the gate is a T-shape or a Y-shape.

In one possible example, a GaN HEMT region-based GaN HEMT switch circuit and a Si CMOS switch control circuit based on a Si CMOS region are turned on through a metal interconnect process.

In one possible example, the switch integrated chip further has integrated thereon an input matching circuit and/or an output matching circuit.

The matching circuit is a circuit which enables the load impedance and the source impedance to be in conjugate matching to achieve impedance matching, so that the circuit on the switch integrated chip can obtain maximum power transmission and has high reliability. In the circuit design, whether the circuit is an active circuit or a passive circuit, the impedance matching problem of the circuit needs to be considered, if the impedance matching cannot be realized, the signal energy transmission efficiency is reduced if the impedance matching is light, and the reflection of the signal energy is formed if the impedance matching is heavy, so that equipment can be damaged. Specifically, the input matching circuit has the functions of improving the standing wave ratio performance, meeting the gain flatness and the like, the output matching circuit has the functions of suppressing harmonics, improving output power, improving nonlinearity and the like, and the input matching circuit and/or the output matching circuit are/is integrated on the switch integrated chip, so that the overall performance of devices of the switch integrated chip can be improved.

The embodiment of the application provides a switch integrated chip based on a GaN HEMT, in particular to a switch integrated chip simultaneously bearing a Si CMOS switch control circuit and a GaN HEMT switch circuit, and the embodiment of the application is explained in detail with reference to the attached drawings.

Specifically referring to fig. 4, fig. 4 is a schematic structural diagram of a switch integrated chip based on a GaN HEMT according to an embodiment of the present invention, and as shown in fig. 4, the switch integrated chip includes:

the silicon-based GaN wafer comprises a silicon-based substrate, wherein the silicon-based substrate comprises a Si CMOS device region, and the Si CMOS device region is loaded with a Si CMOS switch control circuit;

the silicon-based substrate further comprises a GaN epitaxial layer X and a GaN HEMT device region arranged above the GaN epitaxial layer X, and the GaN HEMT device region is loaded with a GaN HEMT switch circuit;

the Si CMOS device region and the GaN HEMT device region are disposed adjacent to each other, and the Si CMOS device region and the GaN HEMT device region are fabricated according to the method for fabricating a switch integrated chip based on a GaN HEMT as described in the first aspect, and the specific method is as follows:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are arranged adjacently;

etching and removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit;

a GaN HEMT device region for fabricating a GaN HEMT switching circuit is formed on the target region GaN epitaxial layer X1.

Since the non-target region GaN epitaxial layer X2 is removed by an etching process during the manufacturing process, the target region GaN epitaxial layer X1 is the remaining GaN epitaxial layer X, and therefore is not shown in the drawing.

It can be seen that, in the embodiment of the present application, the switch integrated chip includes a GaN HEMT device region for manufacturing the GaN HEMT switch circuit and a Si CMOS device region for manufacturing the Si CMOS switch control circuit, and the switch integrated chip is formed with the GaN HEMT device region and the Si CMOS device region at the same time, so that the integration level of the switch integrated chip can be increased, the chip area is reduced, the manufacturing cost is reduced, the overall performance of the device is improved, and the application capability of the switch integrated chip in a power electronic system and a wireless communication radio frequency system is further improved.

In one possible example, the Si CMOS switch control circuit is fabricated according to the fabrication method for fabricating the Si CMOS switch control circuit as described in the above first aspect, and the GaN HEMT switch circuit is fabricated according to the fabrication method for fabricating the GaN HEMT switch circuit as described in the above first aspect.

In one possible example, the Silicon-based substrate is a p-type Silicon substrate, a high resistance Silicon substrate, or a Silicon-on-insulator (SOI) substrate, with the Silicon-based substrate being 3-12 feet in size.

The silicon-based substrate can also be other types of silicon-based substrates;

wherein, the p-type silicon substrate refers to doping a trivalent element such as boron in pure silicon crystal to replace silicon atoms in crystal lattice so as to form the p-type silicon substrate;

wherein, the high-resistance silicon substrate refers to a silicon substrate with the resistivity of 1000-50000 omega-cm;

among them, a Silicon-on-insulator (SOI) SOI substrate refers to an SOI substrate formed by burying a layer of an insulating material, such as Silicon dioxide, between a thin Silicon layer and a thick Silicon layer.

In one possible example, the switch integrated chip further has integrated thereon an input matching circuit and/or an output matching circuit.

In one possible example, the GaN HEMT switch circuit, the Si CMOS switch control circuit, the input matching circuit and the output matching circuit are electrically connected through metal wires to form a loop.

Referring to fig. 5, fig. 5 is a schematic diagram of an apparatus for integrating a GaN monolithic microwave integrated circuit and a Si CMOS switch control circuit on the same chip according to an embodiment of the present disclosure, and as shown in fig. 5, a GaN HEMT, an input matching circuit, and an output matching circuit are integrated on the same chip to form a GaN monolithic microwave integrated circuit (GaN HEMT MMIC circuit).

Referring to fig. 6, in accordance with the embodiment shown in fig. 1C, fig. 6 is a schematic structural diagram of a device manufacturing system according to an embodiment of the present disclosure, as shown in fig. 6, the device manufacturing system includes a processor, a memory, and a communication interface, where the memory stores one or more programs, and the processor performs an operation on the one or more programs, and the program includes instructions for executing part or all of the embodiments of the method for manufacturing the GaN HEMT-based switch integrated chip.

The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It will be appreciated that the device fabrication system, in order to implement the above-described functionality, may include corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the device manufacturing system may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

Referring to fig. 7, fig. 7 is a block diagram of functional units of an apparatus for manufacturing a GaN HEMT-based switch integrated chip according to an embodiment of the present invention, and as shown in fig. 7, the apparatus for manufacturing a GaN HEMT-based switch integrated chip is applied to a device manufacturing system for manufacturing a GaN HEMT-based switch integrated chip, the apparatus for manufacturing a GaN HEMT-based switch integrated chip includes a processing unit and a communication unit,

wherein the processing unit is configured to:

providing a silicon-based GaN wafer, wherein the silicon-based GaN wafer comprises a silicon-based substrate and a GaN epitaxial layer X arranged on the upper end surface of the silicon-based substrate, the GaN epitaxial layer X comprises a target region GaN epitaxial layer X1 and a non-target region GaN epitaxial layer X2, and the target region GaN epitaxial layer X1 and the non-target region GaN epitaxial layer X2 are adjacently arranged;

removing the GaN epitaxial layer X2 in the non-target area by adopting an etching process, so that a Si CMOS device area is formed on the upper end surface of the silicon substrate, and the Si CMOS device area is used for manufacturing a Si CMOS switch control circuit;

forming a GaN HEMT device region on the target region GaN epitaxial layer X1, wherein the GaN HEMT device region is used for manufacturing a GaN HEMT switching circuit;

the communication unit is used for receiving data input from the outside to the switch integrated chip manufacturing device based on the GaN HEMT and sending the data to the processing unit so that the processing unit can execute part or all of the steps of the manufacturing method.

The device for manufacturing the switch integrated chip based on the GaN HEMT can further comprise a storage unit, and the storage unit is used for storing program codes and data of the terminal. The processing unit may be a processor, the communication unit may be a transceiver or a touch display screen, and the storage unit may be a memory.

The embodiments of the present application further provide a computer program product, where the computer program product includes a computer program, and the computer program is operable to execute part or all of the steps of any one of the methods for manufacturing a GaN HEMT-based switch integrated chip described in the above method embodiments.

It should be noted that, for the sake of simplicity, the above embodiments of the method for manufacturing the switching integrated chip based on the GaN HEMT are all described as a series of combinations of actions, but those skilled in the art should understand that the present application is not limited by the described order of actions, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

Those skilled in the art will understand and appreciate that, in the various methods in the description related to the above embodiments of the method for manufacturing the switching integrated chip based on the GaN HEMT, specific descriptions related to the circuit schematic diagram, the structural schematic diagram, the size of the material, the material of the material, the device structure, the device operation mode, the device manufacturing process, and the like are not limited, and the embodiments described in the description all belong to preferred embodiments, and the content of the description should not be construed as limiting the present application.

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Those skilled in the art will appreciate that all or part of the steps in the various methods of the embodiments of the method for manufacturing the GaN HEMT-based switching integrated chip may be implemented by a program that instructs associated hardware to perform the steps, where the program may be stored in a computer-readable memory, and the memory may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The embodiments of the present application are described in detail above, and the principle and the implementation of the method for manufacturing the switch integrated chip based on the GaN HEMT of the present application are explained herein by applying specific examples, and the description of the embodiments above is only used to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the method for manufacturing the switch integrated chip based on the GaN HEMT of the present application, the specific implementation and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, hardware products and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It is understood that all products controlled or configured to perform the processing methods of the flowcharts described in the embodiments of the method for fabricating a GaN HEMT-based switching integrated chip of the present application, such as the integrated chip of the flowcharts described above, and the computer program product, fall within the scope of the related products described in the present application.

It is apparent that those skilled in the art can make various changes and modifications to the GaN HEMT-based switching integrated chip provided herein without departing from the spirit and scope of the present application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.