阅读说明：本技术 一种nmos开关管共享限流电阻芯片电路 (NMOS switching tube sharing current-limiting resistance chip circuit ) 是由 孙德臣 于 2019-11-04 设计创作，主要内容包括：一种NMOS开关管共享限流电阻芯片电路,通过将相邻NMOS管之间的漏端限流电阻与源端限流电阻进行依次交错共享,既能够大大地减少限流电阻数量,又能够保证NMOS管的安全,从而有利于控制NMOS开关管芯片的面积和成本。(A current-limiting resistor chip circuit shared by NMOS switching tubes is characterized in that a drain-end current-limiting resistor and a source-end current-limiting resistor between adjacent NMOS switching tubes are sequentially and alternately shared, so that the number of the current-limiting resistors can be greatly reduced, the safety of the NMOS switching tubes can be ensured, and the area and the cost of the NMOS switching tube chip can be favorably controlled.)

1. A chip circuit of an NMOS switch tube sharing current-limiting resistor is characterized by comprising a plurality of NMOS tubes, wherein grids of the NMOS tubes are connected to an internal control signal end respectively, drain ends of adjacent NMOS tubes in the NMOS tubes are connected to a switch common high end through a same drain end current-limiting resistor, source ends of adjacent NMOS tubes in the NMOS tubes are connected to a switch common low end through a same source end current-limiting resistor, and substrates of all NMOS tubes in the NMOS tubes are connected to a grounding end.

2. The NMOS switching tube shared current-limiting resistor chip circuit of claim 1, wherein the drain-side current-limiting resistors and the source-side current-limiting resistors shared between adjacent NMOS tubes of the plurality of NMOS tubes are in sequential staggered sharing distribution.

3. The NMOS switch tube shared current-limiting resistor chip circuit of claim 1, the source electrode of the first NMOS tube in the plurality of NMOS tubes is connected to the common low end of the switch through a first source end current-limiting resistor, the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are connected with each other and then are connected with the common high end of the switch through a first drain end current limiting resistor, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected with each other and then are connected to the common low end of the switch through a second source end current-limiting resistor, the drain electrode of the third NMOS tube and the drain electrode of the fourth NMOS tube are connected with each other and then are connected with the common high end of the switch through a second drain end current limiting resistor, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected with the common low end of the switch through a third source end current limiting resistor after being interconnected, and the like, and the sharing of the drain-end current limiting resistor and the source-end current limiting resistor in sequence is realized in the NMOS tubes.

Technical Field

The invention relates to a chip circuit integration technology, in particular to an NMOS (N-channel metal oxide semiconductor) switching tube sharing current-limiting resistor chip circuit, which can greatly reduce the number of current-limiting resistors and ensure the safety of NMOS tubes by sequentially and alternately sharing the drain-end current-limiting resistor and the source-end current-limiting resistor between adjacent NMOS tubes, thereby being beneficial to controlling the area and the cost of the NMOS switching tube chip.

Background

The CMOS switch includes an NMOS, and usually the drain and source terminals of the NMOS are directly the input and output terminals of the switch, and the gate is the control terminal. However, in an actual design circuit, ESD (Electro-Static discharge) protection is required for the NMOS. The ESD simulation macro model of the NMOS switching tube can know that the drain electrode D of the NMOS switching tube is connected with the collector electrode c of the NPN triode (the current flowing into the collector electrode is Ic, and the current flowing into the drain electrode is Ids), the source electrode S is connected with the emitter electrode e of the NPN triode and then grounded, the substrate B is connected with the base electrode B of the NPN triode (the substrate outflow current comprises Isub which is grounded through the substrate resistor Rsub, and Isub flows on the substrate resistor Rsub), and the grid electrode G of the NMOS switching tube is a control end. When the drain terminal voltage Vd is increased from 0V, the drain terminal to substrate junction is reverse biased, and once Vd enters the avalanche breakdown region, the electric field in the depletion layer becomes high enough to generate many electron-hole pairs by impact ionization. The electrons flow to the drain as part of the drain current. Holes are injected into the substrate, generating a substrate current Isub. As Isub increases, the voltage drop Vbe across the substrate resistance increases, eventually the source-to-substrate junction is forward biased, causing electrons to be emitted from the source to the substrate. When Vbe reaches 0.5V, the transverse NPN tube is conducted, and the electron current reaches the drain end, so that the generated electron hole pairs are further increased. Since a high electric field is no longer required to sustain the impact ionization current, the drain voltage drops and snapback occurs. In contrast, the prior art takes measures to limit the substrate current Isub by connecting resistors in series at two ends of the NMOS transistor, thereby preventing the NMOS transistor snapback from occurring. An NMOS transistor is generally used as an example of the switch, i.e., the gate G of the NMOS transistor is connected to the internal control signal terminal S2n, the drain D of the NMOS transistor is connected to the switch common high terminal NO through the drain current-limiting resistor, the source S of the NMOS transistor is connected to the switch common low terminal COM through the source current-limiting resistor, the substrate of the NMOS transistor is connected to the ground terminal GND, and the GND represents the lowest potential of the chip. One NMOS tube is the minimum unit of the chip, the actual circuit is formed by connecting a plurality of small units in parallel, each NMOS tube is connected with a current-limiting resistor with enough magnitude, and the total on-resistance of the chip is reduced due to the parallel connection because the final resistor is the total resistance after the parallel connection. The inventor finds that since the source and the drain of each NMOS transistor are independent, each unit needs to be separated when performing corresponding layout design, that is, each NMOS transistor has a drain current-limiting resistor and a source current-limiting resistor which are independent from each other, which greatly increases the chip area and thus increases the cost. The inventor believes that if the drain end current-limiting resistor and the source end current-limiting resistor between the adjacent NMOS tubes are sequentially shared in a staggered mode, the number of the current-limiting resistors can be greatly reduced, the safety of the NMOS tubes can be guaranteed, and therefore the area and the cost of an NMOS switch chip can be controlled.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides the NMOS switching tube sharing current limiting resistor chip circuit, and the drain-end current limiting resistors and the source-end current limiting resistors between the adjacent NMOS tubes are sequentially and alternately shared, so that the number of the current limiting resistors can be greatly reduced, the safety of the NMOS tubes can be ensured, and the area and the cost of the NMOS switching tube chip can be favorably controlled.

The technical scheme of the invention is as follows:

a chip circuit of an NMOS switch tube sharing current-limiting resistor is characterized by comprising a plurality of NMOS tubes, wherein grids of the NMOS tubes are connected to an internal control signal end respectively, drain ends of adjacent NMOS tubes in the NMOS tubes are connected to a switch common high end through a same drain end current-limiting resistor, source ends of adjacent NMOS tubes in the NMOS tubes are connected to a switch common low end through a same source end current-limiting resistor, and substrates of all NMOS tubes in the NMOS tubes are connected to a grounding end.

And the shared drain-end current limiting resistors and the shared source-end current limiting resistors among adjacent NMOS tubes in the plurality of NMOS tubes are in sequential staggered shared distribution.

The source electrode of a first NMOS tube in the NMOS tubes is connected to the common low end of the switch through a first source end current limiting resistor, the drain electrode of the first NMOS tube and the drain electrode of a second NMOS tube are connected to the common high end of the switch through a first drain end current limiting resistor, the source electrode of the second NMOS tube and the source electrode of a third NMOS tube are connected to the common low end of the switch through a second source end current limiting resistor, the drain electrode of the third NMOS tube and the drain electrode of a fourth NMOS tube are connected to the common high end of the switch through a second drain end current limiting resistor, the source electrode of the fourth NMOS tube and the source electrode of a fifth NMOS tube are connected to the common low end of the switch through a third source end current limiting resistor, and so on, and sequential staggered sharing of the shared drain end current limiting resistor and the shared source end current limiting resistor is realized in the NMOS tubes.

The invention has the following technical effects: compared with the prior art, the NMOS switching tube sharing current-limiting resistor chip circuit changes the situation that each NMOS tube is provided with a drain current-limiting resistor and a source current-limiting resistor into the situation that the drain current-limiting resistor and the source current-limiting resistor between the adjacent NMOS tubes are shared in a staggered mode in sequence, so that the number of the current-limiting resistors is reduced by half basically, but for each NMOS tube, two resistors, namely one sharing drain current-limiting resistor and one sharing source current-limiting resistor, are seen at the same time, the two resistors guarantee the safety of the NMOS tube, and the area and the cost of the NMOS switching tube chip are controlled.

Drawings

FIG. 1 is a schematic diagram of a chip circuit of an NMOS switch tube sharing a current-limiting resistor according to the present invention.

The reference numbers are listed below: r11, R12-R1 n-first to nth drain current limiting resistors (n represents a plurality of, for example, n is a positive integer); mn1, Mn 2-Mnn-first NMOS tube to nth NMOS tube (Mn represents NMOS tube, second n in Mnn represents several, for example, n is more than 2); r21, R22-R2 n-a first source end current-limiting resistor to an n-th source end current-limiting resistor (n represents a plurality of, for example, n is a positive integer); NO-switch common high end; COM-switch common low side; GND-ground (lowest potential of chip); s2n — internal control signal terminal.

Detailed Description

The invention is described below with reference to the accompanying drawing (fig. 1).

FIG. 1 is a schematic diagram of a chip circuit of an NMOS switch tube sharing a current-limiting resistor according to the present invention. As shown in fig. 1, an NMOS switching tube-shared current-limiting resistor chip circuit includes a plurality of NMOS tubes (e.g., a first NMOS tube Mn1 to an nth NMOS tube Mnn) having gates respectively connected to an internal control signal terminal s2n, drain terminals of adjacent NMOS tubes of the plurality of NMOS tubes are connected to a common high terminal NO of a switch through a same drain current-limiting resistor (e.g., a first drain current-limiting resistor R11, a second drain current-limiting resistor R12, an nth drain current-limiting resistor R1n, etc.), source terminals of adjacent NMOS tubes of the plurality of NMOS tubes are connected to a common low terminal of the switch through a same source current-limiting resistor (e.g., a second source current-limiting resistor R22, a third source current-limiting resistor R23, an nth source current-limiting resistor R2n, etc.), and substrates of each NMOS tube of the plurality of NMOS tubes are connected to a ground terminal GND. And the shared drain-end current limiting resistors and the shared source-end current limiting resistors among adjacent NMOS tubes in the plurality of NMOS tubes are in sequential staggered shared distribution. A source of a first NMOS tube Mn1 of the plurality of NMOS tubes is connected to the switch common low-side COM, a drain of the first NMOS tube Mn1 and a drain of a second NMOS tube Mn2 are connected to the switch common high-side NO through a first drain current-limiting resistor R11 after being interconnected, a source of the second NMOS tube Mn2 and a source of a third NMOS tube Mn3 are connected to the switch common low-side COM through a second source current-limiting resistor R22 after being interconnected, a drain of the third NMOS tube Mn3 and a drain of a fourth NMOS tube Mn4 are connected to the switch common high-side NO through a second drain current-limiting resistor R12 after being interconnected, a source of the fourth NMOS tube Mn4 and a source of a fifth NMOS tube Mn5 are connected to the switch common low-side COM through a third source current-limiting resistor R23 after being interconnected, and so on, and sequential interleaved sharing of the shared drain current-limiting resistor and the shared source current-limiting resistor among the plurality of NMOS tubes is realized.

In order to provide an NMOS current limiting resistor, reduce the total switch resistance and avoid increasing the chip area, the invention improves the prior art as follows: one end of the minimum unit of the NMOS tube is shared, so that the two ends can be shared together during layout design, and then the two ends are connected with the resistor in series, and the shared ends can be connected together by all the minimum units of the NMOS tube all the time, so that the area is reduced. But two resistors are simultaneously seen for each NMOS tube, so that the safety of the NMOS tube is ensured.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.