阅读说明：本技术 一种滤波电路和滤波方法 (Filter circuit and filtering method ) 是由 张亮 马颖江 易冬柏 王静 于 2019-10-22 设计创作，主要内容包括：本发明公开了一种滤波电路和滤波方法,能够滤除信号中不同类型的毛刺,且不会对信号的固有特征造成影响。该滤波电路包括：边沿检测模块、复位置位模块和边沿延迟模块。边沿检测模块用于接收来自外部的输入信号,并根据输入信号和输出信号的相位差输出第一信号与第二信号,输出信号是输入信号经过滤波电路得到的；复位置位模块用于根据第一信号与第二信号生成第三信号；边沿延迟模块用于根据第三信号以及输入信号生成第四信号,第四信号是输入信号经过预设时长延时得到的,用于对输入信号进行滤波。(The invention discloses a filtering circuit and a filtering method, which can filter burrs of different types in a signal without influencing the inherent characteristics of the signal. The filter circuit includes: the device comprises an edge detection module, a reset setting module and an edge delay module. The edge detection module is used for receiving an input signal from the outside and outputting a first signal and a second signal according to the phase difference of the input signal and an output signal, and the output signal is obtained by the input signal through a filter circuit; the reset setting module is used for generating a third signal according to the first signal and the second signal; the edge delay module is used for generating a fourth signal according to the third signal and the input signal, wherein the fourth signal is obtained by delaying the input signal by a preset time length and is used for filtering the input signal.)

1. A filter circuit, comprising: the edge detection module, the reset setting module and the edge delay module, wherein the output end of the edge detection module is connected with the input end of the reset setting module, and the output end of the reset setting module is connected with the input end of the edge delay module;

the edge detection module is used for receiving an input signal from the outside and outputting a first signal and a second signal according to the phase difference of the input signal and an output signal, wherein the output signal is obtained by the input signal through the filter circuit;

the reset setting module is used for generating a third signal according to the first signal and the second signal;

the edge delay module is configured to generate a fourth signal according to the third signal and the input signal, where the fourth signal is obtained by delaying the input signal by a preset time duration and is used for filtering the input signal.

2. The circuit of claim 1, wherein the edge delay block comprises a positive edge delay block and a negative edge delay block, wherein:

when the third signal is at a low level and the input signal is at a high level, the edge delay module generates the fourth signal through the positive edge delay module;

when the third signal is at a low level and the input signal is at a low level, the edge delay module generates the fourth signal through the negative edge delay module.

3. The circuit of claim 2, wherein the positive edge delay block and the negative edge delay block comprise capacitors, and wherein values of the capacitors are determined according to the preset duration, and the preset duration is greater than a pulse width of a signal glitch.

4. The circuit of claim 3,

the level of the first signal changes from low to high, the level of the second signal changes to low, and the level of the third signal changes to low; or

The level of the second signal changes from high to low, the level of the first signal is high, and the level of the third signal is low.

5. The circuit of any of claims 1-4, further comprising a channel selection block, an input of the channel selection block connected to an output of the reset set block, an output of the channel selection block connected to an input of the edge detection block;

the channel selection module is used for selecting the reset setting module or the edge delay module to output an output signal from the reset setting module and the edge delay module according to the third signal.

6. The circuit of claim 5, wherein the channel selection module comprises a first not gate and a transmission gate, an input of the first not gate is configured to receive the third signal, an output of the first not gate is connected to the first input of the transmission gate, a second input of the transmission gate is configured to receive the third signal, a third input of the transmission gate is connected to the output of the delay unit, and an output of the transmission gate is connected to the reset setting module, wherein the third signal is high, the transmission gate is in a closed state, the third signal is low, and the transmission gate is in an open state.

7. The circuit of claim 3, wherein the edge detection module comprises a NAND gate and a first NOR gate, a first input of the NAND gate and a first input of the first NOR gate being connected to receive the output signal, a second input of the NAND gate and a second input of the first NOR gate being configured to receive the input signal, an output of the NAND gate being configured to output the first signal, and an output of the first NOR gate being configured to output the second signal.

8. A method of filtering, the method being applied to a filter circuit as claimed in any one of claims 1 to 7, the method comprising:

the edge detection module generates and outputs a first signal and a second signal according to the phase difference of a received input signal and an output signal, wherein the output signal is obtained by the input signal through the filter circuit;

the reset setting module generates a third signal according to the first signal and the second signal;

the edge delay module generates a fourth signal according to the third signal and the input signal, wherein the fourth signal is obtained by delaying the input signal by a preset time length and is used for filtering the input signal.

9. The method of claim 8, wherein: the edge delay module comprises a positive edge delay module and a negative edge delay module, and the edge delay module generates a fourth signal according to the third signal and the input signal, and comprises:

the edge delay module determines that the third signal is at a low level and the input signal is at a high level, and then starts the positive edge delay module to generate the fourth signal;

and the edge delay module determines that the third signal is at a low level and the input signal is at a low level, and then starts the negative edge delay module to generate the fourth signal.

10. The method of claim 9, wherein the circuit further comprises a channel select block, an input of the channel select block being connected to an output of the reset set block, an output of the channel select block being connected to an input of the edge detect block, the method further comprising:

and the channel selection module selects the reset setting module or the edge delay module to output an output signal from the reset setting module and the edge delay module according to the third signal.

Technical Field

The invention relates to the field of analog integrated circuits, in particular to a filter circuit and a filtering method.

Background

An integrated circuit is a circuit having a specific function obtained by integrating electronic components such as resistors, capacitors, transistors, and the like by a semiconductor process.

Since the electronic components are easily affected by external environments such as lightning and power grid fluctuation in the working process, burrs are easily generated on signals generated by the electronic components. A spur may be considered herein as a disturbance that affects the frequency and/or amplitude of the signal. The burrs not only affect the normal operation of the integrated circuit, but also cause damage to the integrated circuit when the burrs are serious. For this purpose, the burrs need to be filtered out.

One conventional method for filtering the glitch is to provide a filter circuit, such as a first-order passive RC filter circuit, a delay circuit, etc., on a signal interaction path to filter the glitch. However, the first-order passive RC filter circuit can only eliminate positive or negative burrs of a signal, that is, only single-side burrs can be eliminated, and high-frequency burrs cannot be eliminated; the delay circuit can only eliminate nanosecond delay and can affect the inherent characteristics of the signal, such as duty cycle. It can be seen that current filtering circuits are either only effective for a certain type of glitch or may change the inherent characteristics of the signal during the filtering process.

Disclosure of Invention

The embodiment of the invention provides a filtering circuit and a filtering method, which can filter burrs of different types in a signal and cannot influence the inherent characteristics of the signal.

In a first aspect, an embodiment of the present invention provides a filter circuit, where the filter circuit includes an edge detection module, a reset setting module, and an edge delay module, an output end of the edge detection module is connected to an input end of the reset setting module, and an output end of the reset setting module is connected to an input end of the edge delay module; wherein the content of the first and second substances,

the edge detection module is used for receiving an input signal from the outside and outputting a first signal and a second signal according to the phase difference of the input signal and an output signal, wherein the output signal is obtained by the input signal through the filter circuit;

the reset setting module is used for generating a third signal according to the first signal and the second signal;

the edge delay module is configured to generate a fourth signal according to the third signal and the input signal, where the fourth signal is obtained by delaying the input signal by a preset time duration and is used for filtering the input signal.

Optionally, the edge delay module includes a positive edge delay module and a negative edge delay module, where:

when the third signal is at a low level and the input signal is at a high level, the edge delay module generates the fourth signal through the positive edge delay module;

when the third signal is at a low level and the input signal is at a low level, the edge delay module generates the fourth signal through the negative edge delay module.

Optionally, the positive edge delay module and the negative edge delay module include capacitors, values of the capacitors are determined according to the preset time length, and the preset time length is greater than the pulse width of the signal glitch.

Optionally, the level of the first signal changes from low to high, the level of the second signal changes to low, and the level of the third signal changes to low; alternatively, the first and second electrodes may be,

the level of the second signal changes from high to low, the level of the first signal is high, and the level of the third signal is low.

Optionally, the circuit further includes a channel selection module, an input end of the channel selection module is connected to an output end of the reset setting module, and an output end of the channel selection module is connected to an input end of the edge detection module;

the channel selection module is used for selecting the reset setting module or the edge delay module to output an output signal from the reset setting module and the edge delay module according to the third signal.

Optionally, the channel selection module includes a first not gate and a transmission gate, an input end of the first not gate is configured to receive the third signal, an output end of the first not gate is connected to the first input end of the transmission gate, a second input end of the transmission gate is configured to receive the third signal, a third input end of the transmission gate is connected to an output end of the delay unit, an output end of the transmission gate is connected to the reset setting module, wherein the third signal is at a high level, the transmission gate is in a closed state, the third signal is at a low level, and the transmission gate is in an open state.

Optionally, the edge detection module includes a nand gate and a first nor gate, a first input of the nand gate is connected to a first input of the first nor gate and receives the output signal, a second input of the nand gate and a second input of the first nor gate are configured to receive the input signal, an output of the nand gate is configured to output the first signal, and an output of the first nor gate is configured to output the second signal.

Optionally, the reset and set module includes a first submodule and a second submodule, the first submodule is configured to generate the third signal according to the first signal and the second signal, and the second submodule is configured to charge or discharge the capacitor according to the first signal and the second signal.

Optionally, the first sub-module includes a second not gate, a second nor gate and a third not gate, an input terminal of the second not gate is connected to an output terminal of the nand gate, an output terminal of the second not gate is connected to a first input terminal of the second nor gate, a second input terminal of the second nor gate is connected to an output terminal of the first nor gate, an output terminal of the second nor gate is connected to an input terminal of the third not gate, and an output terminal of the third not gate is configured to output the third signal.

Optionally, the second sub-module includes a PMOS and an NMOS, an output end of the PMOS is connected to the power supply, a second input end of the PMOS is connected to an output end of the nand gate, a first input end of the PMOS is connected to a first input end of the NMOS, a second input end of the NMOS is connected to an output end of the first nor gate, and an output end of the NMOS is grounded.

In a second aspect, an embodiment of the present invention provides a filtering method, which is applied to the filtering circuit according to the first aspect, and the method includes:

the edge detection module generates and outputs a first signal and a second signal according to the phase difference of a received input signal and an output signal, wherein the output signal is obtained by the input signal through the filter circuit;

the reset setting module generates a third signal according to the first signal and the second signal;

the edge delay module generates a fourth signal according to the third signal and the input signal, wherein the fourth signal is obtained by delaying the input signal by a preset time length and is used for filtering the input signal.

Optionally, the edge delay module includes a positive edge delay module and a negative edge delay module, and the edge delay module generates a fourth signal according to the third signal and the input signal, including:

the edge delay module determines that the third signal is at a low level and the input signal is at a high level, and then starts the positive edge delay module to generate the fourth signal;

and the edge delay module determines that the third signal is at a low level and the input signal is at a low level, and then starts the negative edge delay module to generate the fourth signal.

Optionally, the circuit further includes a channel selection module, an input end of the channel selection module is connected to an output end of the reset setting module, an output end of the channel selection module is connected to an input end of the edge detection module, and the method further includes:

and the channel selection module selects the reset setting module or the edge delay module to output an output signal from the reset setting module and the edge delay module according to the third signal.

The filter circuit provided by the invention can filter an input signal, wherein the edge detection module can determine whether the burr of the input signal is positive or negative according to the phase difference between the input signal and the output signal and generate a first signal and a second signal. The first signal and the second signal can be used for resetting the setting module to generate a third signal so as to determine the opening and closing of the edge delay module. The edge delay module may generate a fourth signal for filtering a spur of the input signal, and the fourth signal may be a delayed signal of the input signal. Therefore, no matter whether the burr of the input signal is a positive burr or a negative burr, as long as the pulse width of the burr is smaller than that of the fourth signal, the burr can be filtered through the fourth signal. Namely, the filter circuit provided by the embodiment of the invention can filter different types of burrs in the input signal. And the fourth signal can generate delay action on the positive edge and the negative edge of the input signal, even if the input signal is delayed on the positive edge and the negative edge, the inherent characteristics of the input signal cannot be influenced.

Drawings

FIG. 1 is a schematic diagram of a burr type of an integrated circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a filter circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a specific logic circuit of a filter circuit according to an embodiment of the present invention;

fig. 4 is an equivalent circuit diagram of a filter circuit according to an embodiment of the present invention;

fig. 5 is an equivalent circuit diagram of a filter circuit according to an embodiment of the present invention;

fig. 6 is an equivalent circuit diagram of a capacitor according to an embodiment of the present invention;

fig. 7 is a schematic filtering diagram of a filter circuit according to an embodiment of the present invention;

fig. 8 is a flowchart illustrating a filtering method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.

The glitches can be roughly classified into 4 types such as a low-frequency positive glitch, a low-frequency negative glitch, a high-frequency positive glitch, and a high-frequency negative glitch. Referring to fig. 1, fig. 1 illustrates an example IN which an input signal (SIG _ IN) is divided into 5 stages IN time, where the 5 stages are a first stage, a second stage, a third stage, a fourth stage and a fifth stage, respectively, where the input signal IN the first stage has no glitch, the input signal IN the second stage has a low-frequency positive glitch, the input signal IN the third stage has a low-frequency negative glitch, the input signal IN the fourth stage has a high-frequency positive glitch, and the input signal IN the fifth stage has a high-frequency negative glitch. Fig. 1 is only for illustrating the 4 types of glitches, and one or more types of glitches may exist in the input signal. To ensure the normal operation of the integrated circuit, the following four methods are commonly used to filter the glitch.

In the first method, an analog low-pass filter, such as a first-order passive RC filter, is arranged on a signal interaction path, and the glitch can be eliminated by utilizing the integral effect of a capacitor on charges;

in the second method, a D flip-flop is arranged on a signal interaction path, a clock signal edge is used for sampling an input signal, and the input signal is captured only when the edge arrives. Because the probability of disturbance of the input signal at the edge moment is lower, the filtering effect is achieved;

the third method is to change the encoding mode of the signal, for example, convert a group of data from binary code to gray code, so that only one bit between any two adjacent code groups is changed to reduce the peak pulse current generated during digital state switching, thereby reducing the logic error during state switching to achieve the filtering effect;

in the fourth method, a delay unit is arranged on a signal interaction path, and the delay unit is used for delaying an input signal and then performing logic operations such as AND and OR and the like, so that the glitch elimination is realized.

The first method can only eliminate single-side burrs, namely, only positive burrs or negative burrs can be eliminated at a single time, and high-frequency burrs cannot be eliminated; the second method requires the participation of a high-frequency clock signal to complete filtering; the third method is only suitable for data composed of a plurality of signals, and burrs of a single signal cannot be filtered; the fourth method can only eliminate nanosecond glitches and can change the original inherent characteristics of signals, such as period, occupancy ratio and the like. It can be seen that the four current methods for filtering the glitches are either effective only for a certain type of glitch, or may change the inherent characteristics of the signal during the filtering process.

In view of the above, embodiments of the present invention provide a filter circuit and a filtering method, which can be used to filter different types of glitches in an input signal without changing the inherent characteristics of the input signal. The following describes a filtering circuit and a filtering method according to an embodiment of the present invention in detail with reference to the drawings.

Fig. 2 is a schematic diagram of a filter circuit according to an embodiment of the present invention. The filter circuit provided by the embodiment of the invention comprises an edge detection module 201, an edge delay module 202 and a reset setting module 203. The output end of the edge detection module 201 is connected with the input end of the reset setting module 203, and the output end of the reset setting module 203 is connected with the input end of the edge delay module 202.

The filter circuit provided by the embodiment of the present invention may be used to filter the glitch of the signal, and for convenience of description, the signal to be filtered is referred to as an input signal, such as the signal SIG _ IN fig. 2. The input signal is input to an input terminal of a filter circuit, and the glitch is filtered by the filter circuit, and a filtered signal is output. In the embodiment of the present invention, an input signal is input to an input end of the edge detection module 201, and the edge detection module 201 may be configured to detect an edge polarity of the input signal, that is, whether a spur of the input signal is a positive-going spur or a negative-going spur. The output signal of the input signal that has been output by the filter circuit before can be used by the edge detection module 201 to determine the polarity of the edge of the current input signal. That is, the output signal of the previous input signal outputted through the filter circuit is also inputted to the input terminal of the edge detecting module 201. That is, the input terminal of the edge detection module 201 receives the input signal and the output signal, and the edge detection module 201 can determine the polarity of the edge of the input signal according to the phase difference between the input signal and the output signal, that is, determine whether the edge of the incoming input signal is a positive edge or a negative edge. When the edge detection module 201 detects that the phase difference between the input signal and the output signal is negative, it may be determined that a negative edge exists in the input signal, and then a negative edge detection PDT _ n (negative Pulse detect) signal output by the edge detection module 201 generates a transition; when the edge detection module 201 detects that the phase difference between the input signal and the output signal is positive, it can be determined that a positive edge exists in the input signal, and then the PDT _ p (positive Pulse detect) signal output by the edge detection module 201 generates a transition. For convenience of description, hereinafter, the negative edge detection PDT _ n (negative Pulse detect) signal is referred to as a first signal, and the positive edge detection PDT _ p (positive Pulse detect) signal is referred to as a second signal.

The input end of the reset setting module 203 is connected with the output end of the edge detection module 201, and the output end of the reset setting module 203 is connected with the input end of the edge delay module 202. The edge detection module 201 outputs the first signal and the second signal to the reset and set module 203, and the reset and set module 203 may determine whether to reset or set according to the first signal and the second signal. If the first signal and the second signal are both at a high level, the reset setting module 203 is in a reset state; if the first signal and the second signal are both low level, the reset setting module 203 is in a set state.

When the first signal is at a high level and the second signal is at a low level, the reset/set block 203 neither resets nor sets, but turns on the edge delay block 202. It is also understood that the reset set block 203 may also determine whether the edge delay block 202 needs to be turned on or off based on the first signal and the second signal. Illustratively, the reset set module 203 may generate a PDT (pulse detect) signal, hereinafter referred to as a third signal, based on the first signal and the second signal, which may determine whether to turn on the edge delay module 202. For example, when the third signal is high, the edge delay block 202 is in an off state; when the third signal is low, the edge delay block 202 is in the on state. Thus, when determining that the input signal burr needs to be filtered, the edge delay module 202 is started; if it is determined that filtering of glitches of the input signal is not required, the edge delay block 202 is turned off, so that the edge delay block 202 does not need to be turned on all the time, wasting power.

The edge delay module 202 may include a positive edge delay module configured to filter positive-going glitches of the input signal and a negative edge delay module configured to filter negative-going glitches of the input signal, and the edge delay module 202 may determine whether to turn on the edge delay module 202 according to the third signal and the input signal. The input terminal of the edge delay module 202 is further connected to a signal source for providing an input signal from outside.

When the third signal is at a low level and the input signal is at a high level, it is determined in the edge delay module 202 that the positive edge delay module is turned on and the negative edge delay module is turned off; when the third signal is at a low level and the input signal is at a high level, the edge delay block 202 determines that the negative edge delay block is on and the positive edge delay block is off. For example, the edge delay module 202 may be configured to generate a signal for filtering a spur of the input signal, and the filtering of the input signal is implemented by the signal. For example, the edge delay module 202 may generate a fourth signal, where the fourth signal may be a delayed signal of the input signal, that is, the fourth signal is obtained by delaying the input signal for a preset time. Assuming that the predetermined time duration is Td, the fourth signal can filter OUT glitches with a pulse width smaller than Td in the input signal, while keeping the signal with a pulse width larger than Td, and output the output signal after Td, such as signal DLY _ OUT in fig. 2, hereinafter referred to as output signal, so as to filter OUT glitches of the input signal without changing the inherent characteristics of the input signal.

Considering that the input signal sometimes has no glitch, in this case, the edge delay block 202 may not be turned on, i.e., the input signal is directly output. To this end, please refer to fig. 2 again, the filter circuit according to the embodiment of the present invention may further include a channel selection module 204, an input end of the channel selection module 204 is connected to an output end of the reset setting module 203, and an output end of the channel selection module 204 is connected to an input end of the edge detection module 201. The channel selection module 204 may select the reset set module 203 or the edge delay module 202 from the reset set module 203 and the edge delay module 202 to output the output signal according to the third signal. That is, whether the input signal needs to be filtered to remove the glitch can be determined according to the third signal, if the input signal does not need to be filtered to remove the glitch, the input signal is output from the reset setting module 203, at this time, the output signal SIG _ OUT of the filter circuit can be considered as the output signal SH _ OUT of the reset setting module 203, if the glitch needs to be filtered, the input signal is output after the glitch is filtered through the edge delay module 202, and at this time, the output signal SIG _ OUT of the filter circuit can be considered as the output signal DLY _ OUT of the edge delay module 202. Thus, when the reset setting module 203 determines that the edge delay module 202 does not need to be turned on, the channel selection module 204 determines that the selection is output from the reset setting module 203, and the two modules work together to output signals in time.

For the sake of understanding, the above-provided respective module circuits will be described in detail below with reference to the drawings.

Fig. 3 is a schematic diagram of a specific logic circuit of a filter circuit according to an embodiment of the present invention. The edge detection module 201 includes nand gate nand1 and nor gate nor1, and for convenience of description, nand gate nand1 is referred to as a first nand gate, and nor gate nor1 is referred to as a first nor gate. The first input end of the first NAND gate is connected with the first input end of the first NOR gate and receives the output signal. The second input end of the first NAND gate and the second input end of the first NOR gate are used for receiving input signals. The output end of the first NAND gate is used for outputting a first signal, and the output end of the first NOR gate is used for outputting a second signal. When the level of the first signal transitions from low to high and the level of the second signal remains low, then the input signal may be considered to have a negative edge. When the level of the first signal is maintained high and the level of the second signal transitions from high to low, then the input signal may be considered to have a positive edge.

The reset and set block 203 includes a not gate inv1, a nor gate nor2, and a not gate inv2, and for convenience of distinction, the not gate inv1 is hereinafter referred to as a first not gate, the nor gate nor2 is hereinafter referred to as a second not gate, and the not gate inv2 is hereinafter referred to as a second not gate. The first not gate, the second not gate and the second not gate are connected in sequence, wherein an input end of the first not gate is connected with an output end of the first not gate, an output end of the first not gate is connected with a first input end of the second not gate, a second input end of the second not gate is connected with an output end of the first not gate, an output end of the second not gate is connected with the second not gate, and an output end of the second not gate outputs a third signal to act on the opening or closing edge delay module 202.

In some embodiments, the reset-set module 203 may further include a P-type Metal-Oxide-Semiconductor (PMOS) transistor and an N-type Metal-Oxide-Semiconductor (NMOS) transistor for controlling whether the reset-set module 203 resets or sets. The PMOS is indicated by PM6 and the NMOS is indicated by NM4 in fig. 3. The output terminal of PM6 is connected to the power supply, the first input terminal of PM6 is connected to the first input terminal of the fourth NM4, the second input terminal of PM6 is connected to the output terminal of the first nand gate, the second input terminal of NM4 is connected to the output terminal of the first nor gate, and the output terminal of NM4 is grounded. As shown in fig. 3, when the first signal and the second signal are both low, PM6 is in the on state, and NM4 is in the off state, the output SH _ OUT of the reset set block 203 is in the set state. When both the PDT _ N signal and the PDT _ P signal are high, PM6 is in an OFF state, NM4 is in an ON state, and the output SH _ OUT of the reset set module 203 is in a reset state.

The edge delay module 202 includes 5 PMOS transistors, PM1, PM2, PM3, PM4 and PM5, 3 NMOS transistors, NM1, NM2 and NM3, and a capacitor C1. The source electrode of the PMOS tube is defined as a first input end, the grid electrode is defined as a second input end, and the drain electrode is defined as an output end. The drain of the NMOS is defined as the first input terminal, the gate is defined as the second input terminal, and the source is defined as the output terminal. The current provided by the edge delay block 202 is referred to as the bias current IBIAS. A bias current IBIAS is input to a first input of PM1 and a second input of PM1 is connected to an output of the reset set block 203 and determines whether PM1 is on based on a third signal. For example, when the third signal is low, PM1 is in an on state; when the third signal is high, PM1 is in an off state. An output of PM1 is connected to a first input of PM2, to a second input, an output of PM1 is further connected to a second input of PM3, and to a second input of PM 4. The output terminals of PM2, PM3, and PM4 are connected to the power supply VDD. A first input of PM4 is connected with the output of PM5, a second input of PM5 is connected with a second input of NM3, a first input of PM5 is connected with a first input of NM3, and an output of NM3 is connected with a first input of NM 2. A first input terminal of PM3 is connected to a first input terminal of NM1, a second input terminal of NM1 and a second input terminal of NM2, and an output terminal of NM1 and an output terminal of NM2 are commonly grounded.

The edge delay module 202 may filter positive-going glitches of the input signal and may also filter negative-going glitches of the input signal, a module circuit for filtering the positive-going glitches of the input signal is referred to as a positive edge delay module, and a module circuit for filtering the negative-going glitches of the input signal is referred to as a negative edge delay module. In fig. 3, a circuit formed by PM1, PM2, PM4, PM5 and capacitor C1 is a positive edge delay block; the circuit formed by PM1, PM2, PM3, NM1, NM2, NM3 and capacitor C1 is a negative edge delay module. In addition, a second input terminal of the PM5 and a second input terminal of the NM3 are both nand gates inv4, i.e., a fourth not gate. The input signal may be input to an input terminal of a fourth not gate and output to PM5 and NM3 via the fourth not gate, so that the edge delay block 202 determines whether to turn on the edge delay block 202, i.e., turn on the positive edge delay block, or turn on the negative edge delay block, based on the input signal and the third signal. Illustratively, when the third signal is low and the input signal is high, the edge delay module 202 may generate the fourth signal through the positive edge delay module. The pulse width of the fourth signal is preset duration, and when the pulse width of the forward burr is smaller than the preset duration, the forward burr can be filtered. When the third signal is at a low level and the input signal is at a low level, the edge delay module 202 may generate a fourth signal through the negative edge delay module, where a pulse width of the fourth signal is a preset duration, and when the pulse width of the negative-going spur is less than the preset duration, the negative-going spur may be filtered.

In addition, PM1, PM2, PM3 and NM1, NM2 may also function as a current mirror to mirror current from the bias circuit IBIAS in a certain proportion. When the glitches with different pulse widths need to be filtered, for example, from a nanometer (ns) level to a micrometer (us) level, the purpose can be achieved by modifying the mirror current proportion of the current sources PM1, PM2, PM3, NM1 and NM2 or changing the parameter of the capacitor C1.

As an alternative, referring to fig. 4, the mirror current sources of PM2, PM3, PM4, NM1, and NM2 shown in fig. 3 may be replaced by resistors R1 and R2, respectively. Since the current mirror branch is removed, PM1 originally in the branch also needs to be designed equivalently, and a combination of an and gate, a nand gate and a nor gate can be used to realize equivalent functions. When the third signal is high, both PM5 and NM3 are turned off, and the charging/discharging path of the capacitor C1 is turned off. When the third level is low, the charging and discharging of the current source to the capacitor C1 is controlled by the input signal SIG _ IN. And is therefore logically functionally equivalent to the original circuit. However, the resistance is greatly affected by the temperature in the CMOS process manufacturing, so there is a limit to the material of the resistance, and the resistance with smaller temperature effect should be selected for replacement.

As another alternative, please refer to fig. 5, which is different from fig. 4 in that a resistor for charging and discharging, for example, R1 in fig. 5, is connected to the second input terminals of PM5 and NM 3.

As still another alternative, referring to fig. 6, the source, the drain, and the substrate of the MOS transistor may be shorted, and by using the dielectric characteristics of the gate oxide, when the voltage between the gate and the source exceeds the turn-on threshold of the MOS transistor, a capacitance is formed between the gate of the MOS transistor and the substrate. The MOS capacitor can be realized by adopting a PMOS (P-channel metal oxide semiconductor) tube or an NMOS (N-channel metal oxide semiconductor) tube.

The channel select block 204 includes a not gate inv3 and a transmission gate tg1, wherein for the sake of convenience of distinction, the not gate inv3 is hereinafter referred to as a third not gate, and the transmission gate tg1 is hereinafter referred to as a first transmission gate. The input of the third not gate is used to receive PDT signals, the output of the third not gate is connected to the first input of the first transmission gate, the second input of the first transmission gate is used to receive PDT signals, and the third input of the first transmission gate is connected to the output of the edge delay module 202 for receiving filtered input signals. The output of the first transmission gate is connected to the reset-set block 203. The first transmission gate determines whether to open the first transmission gate according to the PDT signals received by the first input end and the second input end. When the PDT signal is at a high level, the first transmission gate is in a closed state, or when the PDT signal is at a low level, the first transmission gate is in an open state. If the first transmission gate is in an open state, the output end of the first transmission gate is used for outputting the filtered input signal DLY _ OUT, and the output of the filter circuit is the filtered input signal; if the first transmission gate is in the closed state, the output of the filter circuit is the output SH _ OUT of the reset setting module 203.

In addition, the output end of the reset and set module 203 is connected to the input end of the nand gate inv5, the output end of the not gate inv5 is connected to the input end of the nand gate inv6, and the output end of the not gate inv6 is connected to the output end SIG _ OUT of the filter circuit. For the sake of convenience of distinction, the not gate inv5 is hereinafter referred to as a fifth not gate, and the not gate inv6 is hereinafter referred to as a sixth not gate. The fifth not gate and the sixth not gate are mainly used for performing waveform shaping and enhanced driving with the output signal SH _ OUT of the reset setting module 203 or the output signal DLY _ OUT of the edge delay module.

Consider that, as shown in fig. 1, a glitch generated in an integrated circuit can be classified as a low-frequency positive-going glitch, a low-frequency negative-going glitch, a high-frequency positive-going glitch, and a high-frequency negative-going glitch. A glitch signal may occur at any time of signal transmission, and thus the combination type of the glitch and the signal is various. However, when performing the glitch filter analysis, a fixed high level or a fixed low level may be regarded as a special case of a high-low alternating level signal (the high/low level is particularly long in duration), and a low-frequency positive/negative-direction glitch may be regarded as a special case of a high-frequency positive/negative-direction glitch (a case where the high-frequency positive/negative-direction glitch occurs only once). Therefore, in the embodiment of the present invention, it is sufficient to determine the high-low alternating level signal and the high-low alternating level signal on which the high-frequency glitch is superimposed. The filtering process will be described in detail below with reference to fig. 3 and 7.

Referring to fig. 7, the combination of the glitch and the signal is divided into three stages.

The first stage is as follows: and (5) a burr-free stage.

When the input signal is low IN the edge detection module 201, i.e., SIG _ IN is 0. Since the state of the output signal is uncertain, i.e., the state of SIG _ OUT is uncertain, it can be assumed in advance that SIG _ OUT is 0. On the one hand, since SIG _ IN is 0 and SIG _ OUT is 0, the output of the first nand gate is 1, i.e., PDT _ N is 1, the output of the first nor gate is 1, i.e., PDT _ P is 1, the PM6 IN the reset set module 203 is IN the off state, NM4 is IN the on state, and since the output of NM4 is grounded, the output SH _ OUT of the reset set module 203 is 0. At this time, the capacitor C1 discharges rapidly, and it can be considered that the reset set module 203 performs a reset operation on the capacitor C1. On the other hand, the PDT _ N signal and the PDT _ P signal pass through the first not gate, the second not gate and the second not gate to obtain the PDT signal, where PDT is equal to 1, the PM1 is in the off state, the entire edge delay module 202 has no current, i.e., the edge delay module 202 is in the off state, and the output of the entire filter circuit is equal to the output of the reset setting module 202, i.e., SIG _ OUT is equal to SH _ OUT is equal to 0, which is consistent with the pre-assumption. Therefore, when the input signal is at a low level, the state of the output signal follows the state of the input signal, and the low level is still maintained.

When the input signal is high IN the edge detection module 201, i.e., SIG _ IN is 1. Since the state of the output signal is uncertain, i.e., the state of SIG _ OUT is uncertain, it can be assumed in advance that SIG _ OUT is 1. On the one hand, since SIG _ IN is 1 and SIG _ OUT is 1, the output of the first nand gate is 0, i.e., PDT _ N is 0, and the output of the first nor gate 1 is 0, i.e., PDT _ P is 0, then PM6 IN the reset set module 203 is IN an on state, NM4 is IN an off state, and since the output of PM6 is connected to the power supply, the output SH _ OUT of the reset set module 203 is 1. At this time, the capacitor C1 is charged quickly, and it can be considered that the reset-set module 203 sets the capacitor C1. On the other hand, the PDT _ N signal and the PDT _ P signal pass through the first not gate, the second not gate and the second not gate to obtain the PDT signal, where PDT is equal to 1, the PM1 is in the off state, the entire edge delay module 202 has no current, i.e., the edge delay module 202 is in the off state, and the output of the entire filter circuit is equal to the output of the reset setting module 202, i.e., SIG _ OUT is equal to SH _ OUT is equal to 1, consistent with the pre-assumption. Therefore, when the input signal is high, the state of the output signal follows the state of the input signal, and the high level is still maintained.

When the input signal jumps from a low level to a high level IN the edge detection module 201, i.e., a positive edge exists IN SIG _ IN. From the above analysis, when SIG _ IN is low, SIG _ OUT follows SIG _ IN, i.e., SIG _ OUT is also low. On the one hand, when the positive edge of SIG _ IN arrives, at this time, the input signal SIG _ IN is 1, and the output signal SIG _ OUT is 0, then the output of the first nand gate is 1, i.e., PDT _ N is 1, and the output of the first nor gate is 0, i.e., PDT _ P is 0, then both PM6 and NM4 IN the reset set module 203 are IN the off state, so the output SH _ OUT of the reset set module 203 is not controlled by PM6 and NM 4. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second nor gate and the second not gate to obtain PDT signals, where PDT is 0, PM1 is in an on state, and there is current in PM1, PM2, PM3 and PM 4. Since SIG _ IN is 1 at this time, PM5 is IN the on state and NM3 is IN the off state, i.e., the positive edge delay block is IN the on state. And the first transmission gate is also turned on under the control of the PDT signal, then the capacitor C1 starts to charge from 0, when the voltage on the capacitor C1 is higher than the threshold voltage, the logic gate at the next stage can be forced to flip, and the time taken for the capacitor C1 to charge from 0 to the threshold voltage is defined as Td. That is, after Td time, the output DLY _ OUT of the edge delay block 202 flips and changes from low level to high level. At this time, the output SIG _ OUT of the filter circuit is the output DLY _ OUT of the edge delay block 202, i.e., SIG _ OUT is 1. Therefore, when the positive edge of the input signal comes, the positive edge of the output signal comes after a delay of time Td.

When the input signal jumps from high to low IN the edge detection module 201, i.e., SIG _ IN has a negative edge. From the above analysis, when SIG _ IN is high, SIG _ OUT follows SIG _ IN, i.e., SIG _ OUT is also high. On the one hand, when the negative edge of SIG _ IN arrives, at this time, the input signal SIG _ IN is 0, and the output signal SIG _ OUT is 1, then the output of the first nand gate is 1, i.e., PDT _ N is 1, and the output of the first nor gate is 0, i.e., PDT _ P is 0, then both PM6 and NM4 IN the reset setting module 203 are IN the off state, and therefore the output SH _ OUT of the reset setting module 203 is not controlled by PM6 and NM 4. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second nor gate and the second not gate to obtain PDT signals, where PDT is 0, PM1 is in an on state, and there is current in PM1, PM2, PM3 and PM 4. Since SIG _ IN is 0 at this time, PM5 is IN the off state and NM3 is IN the on state, i.e., the negative edge delay block is IN the on state. And the first transmission gate is also turned on under the control of the PDT signal, then the capacitor C1 discharges from 1, when the voltage on the capacitor C1 is lower than the threshold voltage, the logic gate at the next stage can be triggered to flip, and the time it takes for the capacitor C1 to discharge from 1 to the threshold voltage is defined as Td. That is, after Td time, the output DLY _ OUT of the edge delay block 202 flips and changes from high level to low level. At this time, the output SIG _ OUT of the filter circuit is the output DLY _ OUT of the edge delay block 202, i.e., SIG _ OUT is 0. Therefore, when the negative edge of the input signal comes, the negative edge of the output signal comes after a delay of a time period Td.

From the above, when the input signal is at a fixed level, the output signal is also at a fixed level of the same type. When there is a transition in the input signal, the same type of transition also exists after the delay time Td of the output signal. Since the positive and negative edges of the output signal are all delayed by the same delay time Td, the inherent characteristics of the signal, such as period, frequency, and pulse width, are not changed, but the output signal has a delay time Td with respect to the input signal as a whole.

And a second stage: there is a high frequency forward spur.

When a high-frequency positive-glitch positive edge arrives, IN the edge detection module 201, the input signal jumps from a low level to a high level, at this time, the input signal SIG _ IN is 1, and the output signal SIG _ OUT is 0, then the output of the first nand gate is 1, i.e., PDT _ N is 1, the output of the first nor gate is 0, i.e., PDT _ P is 0, then both PM6 and NM4 IN the reset setting module 203 are IN a closed state, and thus the output SH _ OUT of the reset setting module 203 is not controlled by PM6 and NM 4. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second nor gate and the second not gate to obtain PDT signals, where PDT is 0, PM1 is in an on state, and there is current in PM1, PM2, PM3 and PM 4. Since SIG _ IN is 1 at this time, PM5 is IN the on state and NM3 is IN the off state, i.e., the positive edge delay block is IN the on state. And the first transfer gate is also in an open state under control of the PDT signal, then the capacitor C1 is charged from 0. Since the pulse width of the glitch is less than Td, the voltage on the capacitor C1 cannot exceed the threshold voltage, i.e., cannot cause the logic gate of the subsequent stage to flip, the output DLY _ OUT of the edge delay block 202 will remain at a low level, and at this time, the output SIG _ OUT of the filter circuit is the output DLY _ OUT of the edge delay block 202, so SIG _ OUT is equal to 0.

When a negative edge of a high-frequency positive glitch arrives, IN the edge detection module 201, when the input signal changes from high level to low level, at this time, the input signal SIG _ IN is 0, the output signal SIG _ OUT is 0, then the output of the first nand gate is 1, i.e., PDT _ N is 1, the output of the first nor gate is 1, i.e., PDT _ P is 1, then the PM6 IN the reset setting module 203 is IN a closed state, and the NM4 is IN an open state. Since the output terminal of NM4 is grounded, the output SH _ OUT of the reset set block 203 is 0. At this time, the voltage accumulated on the capacitor C1 is drained quickly, and it can be considered that the reset set module 203 performs a reset operation on the capacitor C1. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second not gate and the second not gate to obtain PDT signals, where PDT is equal to 1, PM1 is in an off state, the entire edge delay module 202 has no current, i.e., the edge delay module 202 is in an off state, and the output of the entire filter circuit is equal to the output of the reset setting module 202, i.e., SIG _ OUT is equal to SH _ OUT is equal to 0.

When the positive edge of the second positive-going glitch arrives, the voltage accumulated by the capacitor C1 needs to be accumulated again in the capacitor C1 in the present period because the negative edge of the previous positive-going glitch discharges the voltage to the ground, and also because the pulse width of the glitch is less than Td, the voltage on the capacitor C1 cannot be inverted by the logic gate of the next stage, and the output SIG _ OUT of the filter circuit continues to maintain the low level.

When the negative edge of the second positive-going glitch arrives, the voltage accumulated on the capacitor C1 will be discharged to ground again by NM4, and thus the output SIG _ OUT of the filter circuit remains low.

From the above, when the pulse width of the forward glitch is less than Td, the output signal remains unchanged (low level), and since there is a reset at the falling edge of each glitch (i.e. the voltage on the capacitor C1 is quickly discharged to ground), the high frequency glitches can be considered independent of each other, and there is no memory effect accumulated. The pulse width of the normal signal is larger than Td, and after the delay of Td, the identical characteristic signal is sent out.

And a third stage: there are high frequency negative-going burrs.

When the negative edge of the high-frequency negative glitch arrives, IN the edge detection module 201, when the input signal changes from high level to low level, at this time, the input signal SIG _ IN is 0, and the output signal SIG _ OUT is 1, then the output of the first nand gate is 1, i.e., PDT _ N is 1, and the output of the first nor gate is 0, i.e., PDT _ P is 0, then both PM6 and NM4 IN the reset setting module 203 are IN the off state, and therefore the output SH _ OUT of the reset setting module 203 is not controlled by PM6 and NM 4. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second nor gate and the second not gate to obtain PDT signals, where PDT is 0, PM1 is in an on state, and there is current in PM1, PM2, PM3 and PM 4. Since SIG _ IN is 0 at this time, PM5 is IN the off state and NM3 is IN the on state, i.e., the negative edge delay block is IN the on state. And the first transfer gate is also in an open state under control of the PDT signal, then the capacitor C1 is discharged from 1. Since the pulse width of the glitch is less than Td, the voltage on the capacitor C1 cannot be lower than the threshold voltage, that is, the subsequent logic gate cannot be caused to flip, the output DLY _ OUT of the edge delay block 202 will remain at the high level, and at this time, the output SIG _ OUT of the filter circuit is the output DLY _ OUT of the edge delay block 202, so SIG _ OUT is equal to 1.

When a positive edge of a high-frequency negative glitch arrives, IN the edge detection module 201, when the input signal changes from a low level to a high level, at this time, the input signal SIG _ IN is 1, and the output signal SIG _ OUT is 1, then the output of the first nand gate is 0, that is, PDT _ N is 0, the output of the first nor gate is 0, that is, PDT _ P is 0, then the PM6 IN the reset setting module 203 is IN an on state, the NM4 is IN an off state, and since the output terminal of the PM6 is connected to the power supply, the output SH _ OUT of the reset setting module 203 is 1. At this time, the capacitor C1 is charged quickly, and it can be considered that the reset-set module 203 sets the capacitor C1. On the other hand, PDT _ N and PDT _ P pass through the first not gate, the second not gate and the second not gate to obtain PDT signals, where PDT is 1, the PM1 is in the off state, the entire edge delay module 202 has no current, i.e., the edge delay module 202 is in the off state, and the output of the entire filter circuit is equal to the output of the reset setting module 202, i.e., SIG _ OUT is 1.

When the negative edge of the second negative-going glitch arrives, the voltage on the capacitor C1 needs to be discharged again in the present period because the positive edge of the last negative-going glitch charges the capacitor C1 quickly, and also because the pulse width of the glitch is smaller than Td, the voltage on the capacitor C1 cannot flip the subsequent logic gate, and the output SIG _ OUT of the filter circuit continues to maintain high level.

When the positive edge of the second negative-going glitch arrives, the capacitor C1 will be quickly charged again by PM6, and therefore the output SIG OUT of the filter circuit remains high.

From the above, when the pulse width of the negative glitch is less than Td, the output signal remains unchanged (high level), and since there is a reset at the positive edge of each glitch (i.e. the voltage on the capacitor C1 is pulled up to the power voltage quickly), the high frequency glitches can be considered independent of each other, and there is no memory effect accumulated. The pulse width of the normal signal is larger than Td, and after the delay of Td, the identical characteristic signal is sent out.

Referring to fig. 8, based on the same inventive concept, an embodiment of the present invention provides a filtering method applied to a filtering circuit, and a flow of the method is described as follows.

Step 801: the edge detection module 201 generates and outputs a first signal and a second signal according to a phase difference between the received input signal and an output signal, where the output signal is obtained by the input signal passing through a filter circuit.

Step 802: the reset setting module 203 generates a third signal according to the first signal and the second signal.

Step 803: the edge delay module 202 generates a fourth signal according to the third signal and the input signal, where the fourth signal is obtained by delaying the input signal by a preset time duration and is used for filtering the input signal.

The filter circuit further comprises a channel selection module 204, and the channel selection module 204 selects the reset setting module 203 or the edge delay module 202 from the reset setting module 203 and the edge delay module 202 to output an output signal according to a third signal.

The filter circuit provided by the embodiment of the invention can filter different types of burrs in the input signal. And the fourth signal can generate delay action no matter at the positive edge or the negative edge of the input signal, even if the input signal is delayed at the positive edge and the negative edge, the inherent characteristics of the input signal can not be influenced.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.