阅读说明：本技术 一种新型高速ddr发送电路 (Novel high-speed DDR (double data Rate) sending circuit ) 是由 孔亮 陈捷 刘亚东 庄志青 于 2021-01-23 设计创作，主要内容包括：本发明提供了一种新型高速DDR发送电路,包括两个PMOS管PM1、PM2和两个NMOS管NM1、NM2；PM1的源极接高电压VDDQ,漏极与PM2的源极相连,PM2的漏极与一电阻相连,电阻的另一端与输出垫片相连；PM1的栅极和控制线netp相连,netp通过反向器INV1与数据输入DIN相连,INV1与netp之间设有电容C；INV1的工作电压为低电压VDD,电容C和netp为PM1的栅极提供一个电压VDDL,以对PM1进行保护；NM1的源极接地,漏极与NM2的源极相连,NM2的漏极与电阻相连；NM1的栅极通过反向器INV2与数据输入DIN相连；采用速度较快的低压器件做主驱动电路及前驱动电路,同时利用时钟信号和开关电容在不额外大幅增加功耗的情况下制造一个电压来保证低压器件的安全性,有效提高了电路的工作速度。(The invention provides a novel high-speed DDR (double data rate) sending circuit, which comprises two PMOS (P-channel metal oxide semiconductor) tubes PM1 and PM2 and two NMOS (N-channel metal oxide semiconductor) tubes NM1 and NM 2; the source electrode of the PM1 is connected with high voltage VDDQ, the drain electrode of the PM1 is connected with the source electrode of the PM2, the drain electrode of the PM2 is connected with a resistor, and the other end of the resistor is connected with the output gasket; a grid electrode of the PM1 is connected with a control line netp, the netp is connected with a data input DIN through an inverter INV1, and a capacitor C is arranged between the INV1 and the netp; the working voltage of INV1 is low voltage VDD, and capacitor C and netp provide a voltage VDDL for the gate of PM1 to protect PM 1; the source electrode of NM1 is grounded, the drain electrode is connected with the source electrode of NM2, and the drain electrode of NM2 is connected with the resistor; the gate of NM1 is connected to data input DIN through inverter INV 2; the low-voltage device with higher speed is used as the main driving circuit and the front driving circuit, and meanwhile, a clock signal and the switch capacitor are used for manufacturing a voltage under the condition that the power consumption is not additionally and greatly increased to ensure the safety of the low-voltage device, so that the working speed of the circuit is effectively improved.)

1. A novel high-speed DDR transmission circuit is characterized in that: the NMOS transistor comprises two PMOS transistors PM1 and PM2 and two NMOS transistors NM1 and NM2 which are connected with the PMOS transistors in parallel; the source of PM1 is connected to high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, the other end of the resistor is connected to the output pad; a grid electrode of the PM1 is connected with a control line netp, the netp is connected with a data input DIN through an inverter INV1, and a capacitor C is arranged between the INV1 and the netp; the working voltage of INV1 is low voltage VDD, and capacitors C and netp can provide a voltage VDDL (VDDL-VDD) for the gate of PM1 to protect PM 1;

the source electrode of the NM1 is grounded, the drain electrode is connected with the source electrode of the NM2, and the drain electrode of the NM2 is also connected with the resistor; the gate of NM1 is connected to the data input DIN through an inverter INV 2.

2. The novel high-speed DDR transmit circuit of claim 1, wherein: PM2 and NM2 are used as static switches for adjusting impedance and are normally open under the working state.

3. The novel high-speed DDR transmit circuit of claim 2, wherein: netp includes two nodes net1 and net2 arranged in parallel; one end of each of net1 and net2 is connected with a capacitor C1 and a capacitor C2 respectively, the other end of each of net1 and net2 is connected with an output gasket through a CLKN respectively, and a grounded voltage stabilizing capacitor C3 is connected between the two CLKN and the output gasket; the capacitor C1 and the net1 are connected with high voltage VDDQ through CLK, the other end of the capacitor C1 is connected with low voltage VDD through CLK and is grounded through CLKN; the capacitors C2 and net2 are grounded via CLK, and the other end of the capacitor C2 is connected to the low voltage VDD via CLK and the high voltage VDDQ via CLKN, respectively.

4. The novel high-speed DDR transmitter circuit of claim 3, wherein: the bypass of the capacitor C is provided with two high-voltage device transmission gates which are arranged in parallel, a high-voltage signal EL0H controls one transmission gate to transmit the voltage VDDL to netp, and a high-voltage signal EL1H controls the other transmission gate to transmit the voltage VDDQ to netp, so that the INV1 can drive the netp to rapidly flip between VDDQQ and VDDL through the capacitor C.

5. The novel high-speed DDR transmitter circuit as claimed in claim 4, wherein: the high voltage signal EL0H is derived from the phase inversion of DIN and DIN _ E exclusive OR, and DIN _ EB followed by OEB phase inversion or level inversion to high.

6. The novel high-speed DDR transmitter circuit of claim 5, wherein: the high voltage signal EL1H is derived from the AND of DIN and DIN _ E after XOR, and then converted to a high signal after level conversion.

Technical Field

The invention relates to the field of circuit design, in particular to a novel high-speed DDR (double data rate) sending circuit.

Background

The DDR output interface driving circuit is usually formed by using a cmos transistor as an output driving resistor, or combining a cmos transistor and a resistor, and is limited by the voltage regulation in the electrical specification, the conventional interface transmitting circuits such as DDR4, DDR5 and the like usually still use a high-voltage device with a slower speed as a main driving circuit and a front driving circuit, for example, the DDR4 power supply voltage is specified to be 1.2V, the main driving unit and the front driving circuit must use a cmos transistor (IO device) which can withstand a voltage of more than 1.2V, and as the process is improved, the speed of a low-voltage core device (core device) is faster and faster, but the withstand voltage is lower and the working speed is difficult to further improve.

Disclosure of Invention

In view of the above technical problems, the present invention provides a novel high-speed DDR transmit circuit.

A novel high-speed DDR sending circuit comprises two PMOS tubes PM1 and PM2, and two NMOS tubes NM1 and NM2 which are connected with the PMOS tubes in parallel; the source of PM1 is connected to high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, the other end of the resistor is connected to the output pad; a grid electrode of the PM1 is connected with a control line netp, the netp is connected with a data input DIN through an inverter INV1, and a capacitor C is arranged between the INV1 and the netp; the working voltage of INV1 is low voltage VDD, and capacitors C and netp can provide a voltage VDDL (VDDL-VDD) for the gate of PM1 to protect PM 1;

the source electrode of the NM1 is grounded, the drain electrode is connected with the source electrode of the NM2, and the drain electrode of the NM2 is also connected with the resistor; the gate of NM1 is connected to the data input DIN through an inverter INV 2.

Preferably, PM2 and NM2 are normally open in the operating state as static switches for adjusting impedance.

Preferably, netp comprises two nodes net1 and net2 arranged in parallel; one end of each of net1 and net2 is connected with a capacitor C1 and a capacitor C2 respectively, the other end of each of net1 and net2 is connected with an output gasket through a CLKN respectively, and a grounded voltage stabilizing capacitor C3 is connected between the two CLKN and the output gasket; the capacitor C1 and the net1 are connected with high voltage VDDQ through CLK, the other end of the capacitor C1 is connected with low voltage VDD through CLK and is grounded through CLKN; the capacitors C2 and net2 are grounded via CLK, and the other end of the capacitor C2 is connected to the low voltage VDD via CLK and the high voltage VDDQ via CLKN, respectively.

Preferably, the bypass of the capacitor C is provided with two high voltage device transmission gates arranged in parallel, the high voltage signal EL0H controls one transmission gate to transmit the voltage VDDL to netp, and the high voltage signal EL1H controls the other transmission gate to transmit the voltage VDDQ to netp, so that the INV1 can drive the netp to rapidly flip between VDDQ and VDDL through the capacitor C.

Preferably, the high voltage signal EL0H is derived from the signals after exclusive-or between DIN and DIN _ E and between and after and OEB phase of DIN _ EB or after level conversion to high.

Preferably, the high voltage signal EL1H is derived from the exclusive or of DIN and DIN _ E and the and of DIN _ E, and then is converted into a high signal by level conversion.

The invention has the beneficial effects that: the low-voltage device with higher speed is used as the main driving circuit and the front driving circuit, and meanwhile, a clock signal and the switch capacitor are used for manufacturing a voltage under the condition that the power consumption is not additionally and greatly increased to ensure the safety of the low-voltage device, so that the working speed of the circuit is effectively improved.

Drawings

The invention will be further described with reference to the accompanying drawings.

FIG. 1 is an overall circuit diagram of an embodiment of the present invention;

FIG. 2 is a circuit diagram of netp in an embodiment of the invention;

FIG. 3 is a circuit diagram of a bypass circuit of the capacitor C according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art without any creative work based on the embodiments of the present invention belong to the protection scope of the present invention.

The invention provides a novel high-speed DDR (double data rate) sending circuit, the whole circuit structure of which is shown in figure 1 and mainly comprises two PMOS (P-channel metal oxide semiconductor) tubes PM1 and PM2 and two NMOS (N-channel metal oxide semiconductor) tubes NM1 and NM2 which are connected with the PMOS tubes in parallel, wherein the PM2 and NM2 are used as static switches for adjusting impedance and are normally open in a working state, and the working speed is not influenced any more; PM1, NM1 are added low voltage devices that switch at high speed under data control.

The source of PM1 is connected to high voltage VDDQ, the drain is connected to the source of PM2, the drain of PM2 is connected to a resistor, the other end of which is connected to the output pad. The gate of PM1 is connected to a control line netp, which is connected to the data input DIN via an inverter INV1, and a capacitor C is provided between INV1 and netp. The operating voltage of INV1 is low voltage VDD, and capacitors C and netp can provide a voltage VDDL (VDDQ-VDD) to the gate of PM1 to protect PM 1. For example, in DDR4, VDDQ is 1.2V, while in 14nm technology, the gate-to-source withstand voltage difference (Vgs) of PM1 is 0.8V, so the pre-driver circuit needs to generate a signal with a signal amplitude of 1.2V to 0.4V (1.2V-0.8V) for the gate of PM 1.

When the INV1 output at the left end of the capacitor C is VDD, the initial voltage at the right end netp is VDDQ. When the next data INV1 is output as 0, the voltage of netp is abruptly changed to VDDQ-VDD under the constraint that the capacitor charge of the capacitor C remains unchanged. Otherwise, when the INV1 output is 0, the initial voltage of netp is VDDQ-VDD, and when the next data INV1 output is VDD, the voltage of netp is abruptly changed to VDDQ.

The source of NM1 is grounded, the drain is connected to the source of NM2, and the drain of NM2 is also connected to a resistor. The gate of NM1 is connected to the data input DIN through an inverter INV 2.

As shown in fig. 2, netp includes two nodes net1 and net2 arranged in parallel. The left ends of net1 and net2 are respectively connected with capacitor C1 and capacitor C2, the right ends are respectively connected with the output pad through CLKN, and a grounded voltage stabilizing capacitor C3 is connected between the two CLKN and the output pad. The capacitor C1 and net1 are connected with high voltage VDDQ through CLK, the left end of the capacitor C1 is connected with low voltage VDD through CLK, and is grounded through CLKN. The capacitors C2 and net2 are grounded via CLK, and the left end of the capacitor C2 is connected to the low voltage VDD via CLK and the high voltage VDDQ via CLKN, respectively. Wherein, CLKN is the inverse signal of CLK, when CLK or CLKN is high level, the switch is turned on, otherwise the switch is turned off.

When CLK is high, CLKN is low, the right end of the capacitor C1 is connected to VDDQ, the left end is connected to VDD, and the charge of C1 is (VDDQ-VDD) × C1; when CLK goes low, CLKN is high, and the left terminal of the capacitor C1 is grounded (0V), and the charge amount of C1 remains (VDDQ-VDD) × C1 without power charging, i.e., the voltage at the right terminal net1 becomes VDDQ-VDD. Under the charge sharing effect of the voltage stabilizing capacitor C3 on the capacitor C1, the VDDL voltage outputted can be gradually reduced from VDDQ and stabilized at VDDQ-VDD after several CLK periods.

Similarly, when CLK is at high level, CLKN is low, the right end of the capacitor C2 is grounded, the left end is connected to VDD, and the charge of C2 is VDD × C2; when CLK goes low, CLKN is high, VDDQ is turned on at the left end of the capacitor C2, and the charge amount of C2 remains VDD × C2 without power charging, i.e., the voltage at the right end net2 becomes VDDQ-VDD. Under the charge sharing effect of the voltage stabilizing capacitor C3 on the capacitor C2, the VDDL voltage outputted can be gradually increased from 0V and stabilized at VDDQ-VDD after several CLK periods.

Therefore, the branch C1 is connected in parallel with the branch C2, so that VDDL can reach 0.5 × VDDQ in the first clock cycle, thereby greatly improving the stability of VDDL while preventing excessive voltage from being generated.

As shown in fig. 3, the bypass of the capacitor C is provided with two high voltage device pass gates arranged in parallel, the high voltage signal EL0H controls one pass gate to transmit the voltage VDDL to netp, and the high voltage signal EL1H controls the other pass gate to transmit the voltage VDDQ to netp, so that INV1 can drive netp to rapidly flip between VDDQ and VDDL through the capacitor C.

The high voltage signal EL1H is derived from the XOR of DIN and DIN _ E (data before DIN) and the AND of DIN _ E, and then converted to a high signal by level conversion. Namely: when two consecutive data are 1, EL1H goes high with the first 1, and opens the transmission gate of the high voltage device controlled by it, and the netp voltage goes to VDDQ. If the third data (DIN _ L) does not continue to hold 1 (i.e., DIN _ E, DIN, DIN _ L is 110), EL1H ends with the end of the first data 1, thereby closing its corresponding transmission gate.

Similarly, the high voltage signal EL0H is derived from the AND phase of DIN _ EB (the inverted signal of DIN _ E) after XOR with DIN _ E and then OEB (the inverted signal of OE) or the signal after level conversion to high. Namely: when two consecutive data are 0 or OE is 0, EL0H goes high with the first 0, and turns on the transmission gate of the high voltage device controlled by it, and the netp voltage goes to VDDL. If the third data (EIN _ L) does not keep 0 (i.e. DIN _ E, DIN, DIN _ L is 001), EL0H ends with the end of the first data 0, thereby closing its corresponding transmission gate.

The level shifters used in EL1H and EL0H are usually slow, so the capacitor C can be charged earlier than INV 1. When the data sent by INV1 is 110, the right end of the capacitor C starts to charge to VDDQ just in the second half of the first pen 1, and the first half of the second pen 1 finishes charging. Charging to VDDL is performed in the same way at 001. When the transmitted data is 0101, INV1 drives netp through capacitor C to flip rapidly between VDDQ and VDDL. All the circuits are combined to function, and the functions of quickly turning over data and preventing level drift by timely charging can be realized.

The invention adopts the low-voltage device with higher speed as the main driving circuit and the front driving circuit, and simultaneously utilizes the clock signal and the switch capacitor to manufacture a voltage under the condition of not additionally and greatly increasing the power consumption to ensure the safety of the low-voltage device and effectively improve the working speed of the circuit.

Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.