阅读说明：本技术 制造光掩模组的方法和制造半导体器件的方法 (Method of manufacturing photomask set and method of manufacturing semiconductor device ) 是由 安兴培 朴商五 丁成坤 于 2020-07-16 设计创作，主要内容包括：一种制造光掩模组的方法包括：准备掩模布局,所述掩模布局包括在第一区域中彼此间隔开的多个第一布局图案,其中,所述多个第一布局图案中的彼此相邻的三个第一布局图案的中心点之间的距离分别具有不同的值；将成对的第一布局图案进行分组,其中,在所述成对的第一布局图案中彼此相邻的两个第一布局图案的中心点之间的距离不具有所述不同的值中的最小值,并将所述掩模布局划分为至少两个掩模布局图案；以及形成包括至少两个光掩模的光掩模组,每个所述光掩模包括与被划分为所述至少两个掩模布局的所述掩模布局中的对应掩模布局中所包括的所述第一布局图案对应的掩模图案。(A method of manufacturing a photomask set includes: preparing a mask layout including a plurality of first layout patterns spaced apart from each other in a first region, wherein distances between center points of three first layout patterns adjacent to each other among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns in which a distance between center points of two first layout patterns adjacent to each other in the pairs of first layout patterns does not have a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and forming a photomask set including at least two photomasks, each photomask including a mask pattern corresponding to the first layout pattern included in a corresponding one of the mask layouts divided into the at least two mask layouts.)

1. A method of manufacturing a photomask set, the method comprising:

preparing a mask layout including a plurality of first layout patterns spaced apart from each other in a first region, and distances between center points of three first layout patterns adjacent to each other among the plurality of first layout patterns respectively have different values;

grouping pairs of first layout patterns among the plurality of first layout patterns, a distance between center points of two first layout patterns adjacent to each other among the pairs of first layout patterns not having a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and

forming a photomask set including at least two photomasks, each photomask including a mask pattern corresponding to the first layout pattern included in a corresponding mask layout pattern of the at least two mask layout patterns.

2. The method of claim 1, wherein preparing the mask layout comprises: making a triangle connecting the center points of the three first layout patterns adjacent to each other among the plurality of first layout patterns a scalene triangle.

3. The method of claim 2, wherein preparing the mask layout further comprises: the plurality of first layout patterns are arranged in a row in a first horizontal direction to have a bottom side distance between center points of the plurality of first layout patterns, and arranged in a zigzag shape in a second horizontal direction perpendicular to the first horizontal direction.

4. The method of claim 3, wherein:

dividing the mask layout includes: alternately selecting lines arranged in the first horizontal direction from the plurality of first layout patterns, and grouping and dividing the lines into a plurality of first even layout patterns and a plurality of first odd layout patterns, and

forming the photomask set includes: a first photomask including a plurality of first even mask patterns corresponding to the plurality of first even layout patterns and a second photomask including a plurality of first odd mask patterns corresponding to the plurality of first odd layout patterns are formed.

5. The method of claim 3, wherein:

dividing the mask layout includes: alternately selecting lines arranged in a zigzag shape in the second horizontal direction from the plurality of first layout patterns, and grouping and dividing the lines into a plurality of first even layout patterns and a plurality of first odd layout patterns, and

forming the photomask set includes: a first photomask including a plurality of first even mask patterns corresponding to the plurality of first even layout patterns and a second photomask including a plurality of first odd mask patterns corresponding to the plurality of first odd layout patterns are formed.

6. The method of claim 5, wherein dividing the mask layout comprises: rows are alternately selected in which the distance between the centre points has a value greater than the distance of the base.

7. The method of claim 1, wherein the mask layout further comprises a plurality of second layout patterns spaced apart from each other in the second region.

8. The method of claim 7, wherein:

dividing the mask layout includes: alternately selecting the plurality of second layout patterns, grouping and dividing the second layout patterns into a plurality of second even layout patterns and a plurality of second odd layout patterns, and

forming the photomask set includes: forming a first photomask and a second photomask such that the first photomask includes a plurality of second even mask patterns corresponding to the plurality of second even layout patterns and the second photomask includes a plurality of second odd mask patterns corresponding to the plurality of second odd layout patterns.

9. The method of claim 8, wherein dividing the mask layout comprises: grouping and dividing the mask layout patterns into the plurality of second even layout patterns and the plurality of second odd layout patterns such that the minimum pitch of the plurality of second even layout patterns and the minimum pitch of the plurality of second odd layout patterns each have a value twice the minimum pitch of the plurality of second layout patterns.

10. The method of claim 7, wherein forming the photomask set comprises: a first photomask having a plurality of second mask patterns corresponding to the plurality of second layout patterns is formed, and a second photomask having no plurality of second mask patterns is formed.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of bit line structures having bit lines extending parallel to each other in a first horizontal direction on a substrate;

forming a plurality of buried contacts on the substrate filling lower portions of spaces between the plurality of bit line structures; and

forming a plurality of landing pads filling an upper portion of spaces between the plurality of bitline structures and extending onto the plurality of bitline structures by using a photomask set including a first photomask and a second photomask, and including a first landing pad, a second landing pad, and a third landing pad adjacent to each other, wherein a triangle connecting a center point of a top surface of the first landing pad, a center point of a top surface of the second landing pad, and a center point of a top surface of the third landing pad includes a scalene triangle,

wherein forming the plurality of landing pads comprises:

forming a landing pad material layer filling the upper portions of the spaces between the plurality of bitline structures and covering the plurality of bitline structures,

forming a plurality of first hard mask patterns on the landing pad material layer by using the first photomask,

forming a plurality of second hard mask patterns in spaces between the plurality of first hard mask patterns on the landing pad material layer by using the second photomask, an

Patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as an etch mask.

12. The method of claim 11, wherein forming the plurality of landing pads comprises: the plurality of landing pads are arranged in a row in a second horizontal direction perpendicular to the first horizontal direction to have a bottom side distance between center points of top surfaces thereof and arranged in a zigzag pattern in the first horizontal direction.

13. The method of claim 12, wherein the first photomask and the second photomask each include even layout patterns and odd layout patterns that alternately correspond to rows of the plurality of landing pads arranged in the second horizontal direction.

14. The method of claim 12, wherein the first photomask and the second photomask each comprise even layout patterns and odd layout patterns that alternately correspond to rows of the plurality of landing pads arranged in a zigzag pattern in the first horizontal direction.

15. The method of claim 14, wherein the plurality of first hard mask patterns and the plurality of second hard mask patterns alternately correspond to rows of the plurality of landing pads having distances between center points of top surfaces of the landing pads having values greater than the bottom side distance, respectively, the rows being arranged in a zigzag in the first horizontal direction.

16. The method of claim 11, wherein forming the plurality of landing pads comprises: forming an edge of a top surface of each of the plurality of landing pads into a circle.

17. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of word lines extending parallel to each other in a first horizontal direction crossing a plurality of active regions on a substrate in which the plurality of active regions are defined by isolation layers;

forming a plurality of bit line structures having bit lines on the substrate, the bit lines extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction;

forming a plurality of buried contacts on the substrate filling lower portions of spaces between the plurality of bit line structures and connected to the plurality of active regions;

forming a plurality of landing pads connected to the plurality of buried contacts, filling upper portions of spaces between the plurality of bit line structures, extending onto the plurality of bit line structures, and each having a rounded top surface by using a photomask set including a first photomask and a second photomask; and

forming a plurality of storage nodes connected to the plurality of landing pads on the plurality of bitline structures,

wherein forming the plurality of landing pads comprises:

forming a landing pad material layer filling an upper portion of a space between the plurality of bit line structures and covering the plurality of bit line structures;

forming a plurality of first hard mask patterns and a plurality of second hard mask patterns separated from the plurality of first hard mask patterns on the landing pad material layer by sequentially using the first photomask and the second photomask; and

patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as an etch mask,

wherein lengths of three sides of a triangle connecting center points of top surfaces of three landing pads adjacent to each other among the plurality of landing pads respectively have: a base side distance having a value of 3 times the characteristic dimension, a first side distance greater than the base side distance, and a second side distance less than the base side distance, and

in forming the plurality of storage nodes, lengths of three sides of a triangle connecting center points of top surfaces of three storage nodes adjacent to each other among the plurality of storage nodes have a value of 3 times a characteristic dimension.

18. The method of claim 17, wherein the plurality of first hard mask patterns and the plurality of second hard mask patterns alternately correspond to rows of the plurality of landing pads arranged in the first horizontal direction, respectively.

19. The method of claim 17, wherein the plurality of first hard mask patterns and the plurality of second hard mask patterns alternately correspond to rows of the plurality of landing pads arranged in a zigzag in a second horizontal direction in which a distance between center points of top surfaces of the landing pads includes the first side edge distance, respectively.

20. The method of claim 17, wherein the first photomask and the second photomask are both reflective masks used for euv lithography processes.

Technical Field

The present disclosure relates to a method of manufacturing a photomask set for forming a pattern and a method of manufacturing a semiconductor device by using the photomask set.

Background

With the rapid development of the electronics industry and consumer demand, electronic devices are becoming increasingly compact and lightweight. Therefore, semiconductor devices used in electronic apparatuses need to be highly integrated, and design rules for the configuration of the semiconductor devices are being reduced. Therefore, difficulty in a process of forming a pattern of a semiconductor device is increasing.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a method of manufacturing a photomask set, the method including: preparing a mask layout including a plurality of first layout patterns spaced apart from each other in a first region, wherein distances between center points of three first layout patterns adjacent to each other among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns in which a distance between center points of two first layout patterns adjacent to each other does not have a minimum value among the different values, and dividing the mask layout into at least two mask layout patterns; and forming a photomask set including at least two photomasks, each photomask including a mask pattern corresponding to the first layout pattern included in a corresponding one of the mask layouts divided into the at least two mask layout patterns.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device by using a photomask set, the method including: forming a plurality of bit line structures having bit lines extending parallel to each other in a first horizontal direction on a substrate; forming a plurality of buried contacts on the substrate filling lower portions of spaces between the plurality of bit line structures; and forming a plurality of landing pads filling an upper portion of spaces between the plurality of bitline structures and extending onto the plurality of bitline structures, and including a first landing pad, a second landing pad, and a third landing pad adjacent to each other, by using a photomask set including a first photomask and a second photomask, wherein a triangle connecting a center point of a top surface of the first landing pad, a center point of a top surface of the second landing pad, and a center point of a top surface of the third landing pad includes a scalene triangle, and the forming the plurality of landing pads includes: forming a landing pad material layer filling the upper portion of the spaces between the plurality of bit line structures and covering the plurality of bit line structures, forming a plurality of first hard mask patterns on the landing pad material layer by using the first photomask, forming a plurality of second hard mask patterns in the spaces between the plurality of first hard mask patterns on the landing pad material layer by using the second photomask, and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as an etch mask.

According to still another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method including: forming a plurality of word lines extending parallel to each other in a first horizontal direction crossing a plurality of active regions on a substrate, the plurality of active regions being defined by isolation layers in the basic; forming a plurality of bit line structures having bit lines on the substrate, the bit lines extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction; forming a plurality of buried contacts on the substrate filling lower portions of spaces between the plurality of bit line structures and connected to the plurality of active regions; forming a plurality of landing pads connected to the plurality of buried contacts, filling upper portions of spaces between the plurality of bit line structures, extending onto the plurality of bit line structures, and each having a rounded top surface by using a photomask set including a first photomask and a second photomask; and forming a plurality of storage nodes on the plurality of bitline structures connected to the plurality of landing pads, wherein forming the plurality of landing pads comprises: forming a landing pad material layer filling an upper portion of a space between the plurality of bit line structures and covering the plurality of bit line structures; forming a plurality of first hard mask patterns and a plurality of second hard mask patterns separated from the plurality of first hard mask patterns on the landing pad material layer by sequentially using the first photomask and the second photomask; and patterning the landing pad material layer by using the plurality of first hard mask patterns and the plurality of second hard mask patterns as an etching mask, wherein lengths of three sides of a triangle connecting center points of top surfaces of three landing pads adjacent to each other among the plurality of landing pads respectively have: a base distance having a value of 3F (feature size), a first side distance greater than the base distance, and a second side distance smaller than the base distance, and lengths of three sides of a triangle connecting center points of top surfaces of three storage nodes adjacent to each other among the plurality of storage nodes when the plurality of storage nodes are formed have a value of 3F (feature size).

Drawings

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, wherein:

FIG. 1 shows a schematic top view of a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment;

FIGS. 2A and 2B show schematic top views of a process for designing a cell region of a mask layout for fabricating a patterned photomask set according to an example embodiment;

FIG. 3 shows a schematic top view of a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment;

FIGS. 4A, 4B, 5A, and 5B illustrate schematic top views of a photomask set for patterning according to an example embodiment;

FIG. 6 shows a schematic top view of a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment;

FIGS. 7A, 7B, 8A, and 8B illustrate schematic top views of a photomask set for patterning according to example embodiments;

FIGS. 9A-9B illustrate schematic cross-sectional views of a photomask set for patterning according to example embodiments;

10A-10H illustrate cross-sectional views of stages in a method of forming a pattern by using a photomask set according to an example embodiment;

fig. 11A illustrates a schematic top-down layout of a semiconductor device fabricated by using a photomask set according to an example embodiment;

FIG. 11B illustrates a top-down layout that selectively illustrates some of the primary configurations in FIG. 11A;

fig. 12A to 12C illustrate schematic top-down layouts of an arrangement of landing pads included in a semiconductor device manufactured by using a photomask set according to example embodiments;

fig. 13A to 13B illustrate schematic top-down layouts of landing pads included in a semiconductor device formed corresponding to photomasks included in a photomask set according to example embodiments; and

fig. 14A to 21D illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment.

Detailed Description

FIG. 1 is a schematic top view of a mask layout ML for fabricating a photomask set for forming a pattern according to an example embodiment.

Referring to fig. 1, the mask layout ML may include a plurality of first layout patterns MLC, a plurality of second layout patterns MLX, and a plurality of third layout patterns MLY.

The plurality of first layout patterns MLC may be island-shaped layout patterns spaced apart from each other. The plurality of first layout patterns MLC may respectively correspond to a plurality of contact patterns or a plurality of holes in the semiconductor device. The plurality of first layout patterns MLC may be arranged in a honeycomb shape arranged in rows in a first horizontal direction (X direction) on a plane and arranged in zigzag in a second horizontal direction (Y direction), for example, the rows of the first layout patterns MLC in the first horizontal direction (X direction) may be offset with respect to each other in the second horizontal direction (Y direction). The plurality of first layout patterns MLC may be arranged in rows having the first cell pitch PXC in the first horizontal direction (X direction). In the plurality of first layout patterns MLC, the rows arranged in the first horizontal direction (X direction) may be arranged to have the second cell pitch PYC in the second horizontal direction (Y direction). In an embodiment, the value of first cell pitch PXC may be greater than the value of second cell pitch PYC. For example, the first cell pitch PXC may have a value of 3 times the feature size (3F), and the second cell pitch PYC may have a value of 2.6 times the feature size (2.6F). The plurality of first layout patterns MLC may be formed to have a flattened honeycomb shape, which will be described in detail with reference to fig. 2A and 2B.

The plurality of second layout patterns MLX may be a plurality of line-shaped layout patterns extending generally in the first horizontal direction (X direction), and arranged to be spaced apart from each other in the second horizontal direction (Y direction). The plurality of second layout patterns MLX may respectively correspond to a plurality of line patterns included in the semiconductor device. The plurality of third layout patterns MLY may be a plurality of line-shaped layout patterns extending generally in the second horizontal direction (Y direction), and arranged to be spaced apart from each other in the first horizontal direction (X direction). The plurality of second layout patterns MLX may have the first core pitch PYL as a minimum pitch in the second horizontal direction (Y direction), and the plurality of third layout patterns MLY may have the second core pitch PXL as a minimum pitch in the first horizontal direction (X direction). In some embodiments, first core pitch PYL and second core pitch PXL may have a value of 3F (feature size).

The plurality of third layout patterns MLY may respectively correspond to a plurality of line patterns included in the semiconductor device. The plurality of third layout patterns MLY may be a plurality of line-shaped layout patterns for forming a plurality of line-shaped patterns extending in the second horizontal direction (Y direction) as a whole in the semiconductor device. The first horizontal direction (X direction) and the second horizontal direction (Y direction) may be perpendicular to each other.

The second layout pattern MLX and the third layout pattern MLY are line-shaped patterns extending "generally" in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. However, this does not mean that the second and third layout patterns MLX and MLY are straight line-shaped patterns extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), but means that the second and third layout patterns MLX and MLY are generally similar to patterns forming lines extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), even if there are some bent portions or variations in width.

The region where the first layout pattern MLC is arranged may be referred to as a first region CELL, and the region where the second layout pattern MLX and the third layout pattern MLY are arranged may be referred to as a second region CORE. The first region CELL may correspond to a CELL region of the semiconductor device, and the second region CORE may correspond to a CORE region of the semiconductor device, but the embodiment is not limited thereto. The areas where the second and third layout patterns MLX and MLY are arranged may be referred to as first and second line areas CORE-H and CORE-V, respectively. In the present specification, in the photomask and the semiconductor device, the regions corresponding to the first region CELL, the second region CORE, the first line region CORE-H, and the second line region CORE-V of the mask layout ML may also be referred to as the first region CELL, the second region CORE, the first line region CORE-H, and the second line region CORE-V.

Planar shapes of the plurality of first layout patterns MLC, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY are schematically shown to show positions where the first layout patterns MLC to the third layout patterns MLY are arranged. Therefore, the planar shape may be different from that of the actual layout pattern of the mask layout ML. For example, the planar shapes of the plurality of first layout patterns MLC, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY may be the result of performing Optical Proximity Correction (OPC) for forming the plurality of contact patterns, the plurality of holes, or the plurality of line patterns included in the semiconductor device into a desired shape.

Fig. 2A and 2B are schematic top views for describing a process of designing a cell region of a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment. In detail, fig. 2B is a top view illustrating an arrangement of a plurality of first layout patterns MLC in a cell area of a mask layout for manufacturing a photomask set for forming a pattern according to an example embodiment, and fig. 2A is a top view illustrating an arrangement of a plurality of virtual reference layout patterns MLCR referred to for effectively describing the arrangement of the plurality of first layout patterns MLC illustrated in fig. 2B.

Referring to fig. 2A, the plurality of virtual reference layout patterns MLCR may have a honeycomb shape arranged in a row in a first horizontal direction (X direction) and in a zigzag in a second horizontal direction (Y direction) on a plane. The plurality of reference layout patterns MLCR indicate the case where: wherein the triangle connecting the center points of the three reference layout patterns MLCR adjacent to each other is an equilateral triangle, and at least two of the three interior angles of the triangle connecting the center points of the three reference layout patterns MLCR adjacent to each other have the same value.

Among the three reference layout patterns MLCR adjacent to each other, the reference bottom side distance LRB, i.e., the distance between the center points of the two reference layout patterns MLCR adjacent to each other in the first horizontal direction (X direction), and the first and second reference side distances LR1 and LR2, i.e., the distances between the center points of the two reference layout patterns MLCR adjacent to each other in the first horizontal direction (X direction) and the center point of one reference layout pattern MLCT adjacent to the two reference layout patterns MLCR in the second horizontal direction (Y direction), respectively, may have a value of 3F (feature size), i.e., the same value. The value of the reference bottom side distance LRB may be the same as the value of the first cell pitch PXC. A distance having a value of 3F may be referred to as a reference distance.

Referring to fig. 2B, the plurality of first layout patterns MLC may have a honeycomb shape arranged in a row in a first horizontal direction (X direction) on a plane and in a zigzag in a second horizontal direction (Y direction). In the plurality of first layout patterns MLC, a triangle connecting center points of three first layout patterns MLC adjacent to each other may be a scalene triangle.

Among the three first layout patterns MLC adjacent to each other, the bottom side distance LB, i.e., the distance between the center points of two first layout patterns MLC adjacent to each other in the first horizontal direction (X direction), and the first side distance L1 and the second side distance L2, i.e., the distances between the center points of two first layout patterns MLC adjacent to each other in the first horizontal direction (X direction) and the center points of one first layout pattern MLC adjacent to the two first layout patterns MLC in the second horizontal direction (Y direction), respectively, may have different values. In some embodiments, the first side distance L1 may have a value greater than the bottom distance LB, and the second side distance L2 may have a value less than the bottom distance LB. For example, the first side distance L1 may have a value greater than 3F (feature size) and the second side distance L2 may have a value less than 3F (feature size). The bottom side distance LB may have the same value as the first cell pitch PXC.

In comparison with the plurality of reference layout patterns MLCR (fig. 2A), in the plurality of first layout patterns MLC, the center points of the plurality of first layout patterns MLC may be offset from the center points of the plurality of reference layout patterns MLCR by a certain distance in the first horizontal direction (X direction) or a direction opposite to the first horizontal direction (X direction) (-X direction). In comparison with the plurality of reference layout patterns MLCR, in the plurality of first layout patterns MLC, the rows arranged in the first horizontal direction (X direction) may be alternately moved in the second horizontal direction (Y direction) by the first movement distance CM1 in the first horizontal direction (X direction) and by the second movement distance CM2 in a direction opposite to the first horizontal direction (X direction) (-X direction). In some embodiments, the first and second movement distances CM1 and CM2 may have the same value.

Fig. 3 is a schematic top view for describing a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to example embodiments, and fig. 4A, 4B, 5A, and 5B are each schematic top views of a photomask set for forming a pattern according to example embodiments.

Referring to fig. 3, the mask layout ML may include a plurality of first layout patterns MLC, a plurality of second layout patterns MLX, and a plurality of third layout patterns MLY (described with reference to fig. 1). The plurality of first layout patterns MLC are divided into a plurality of first even layout patterns MCL1 and a plurality of first odd layout patterns MLC2, the plurality of second layout patterns MLX are divided into a plurality of second even layout patterns MLX1 and a plurality of second odd layout patterns MLX2, and the plurality of third layout patterns MLY are divided into a plurality of third even layout patterns MLY1 and a plurality of third odd layout patterns MLY 2.

For example, the plurality of first layout patterns MLC may be grouped by selecting a group of first layout patterns MLC whose distance between center points of two first layout patterns MLC adjacent to each other has a value greater than the second side distance L2 (see fig. 2B) and dividing the selected layout patterns into a plurality of first even layout patterns MLC1 and a plurality of first odd layout patterns MLC 2. Each of the plurality of first even layout patterns MLC1 and the plurality of first odd layout patterns MLC2 may be obtained by selecting pairs of layout patterns MLC adjacent to each other, where a distance between center points of two first layout patterns MLC is equal to a bottom side distance LB (see fig. 2B), and grouping the pairs of layout patterns. For example, the plurality of first even layout patterns MLC1 and the plurality of first odd layout patterns MLC2 may be obtained by alternately selecting rows arranged in the first horizontal direction (X direction) from the plurality of first layout patterns MLC.

The plurality of second even layout patterns MLX1 and the plurality of second odd layout patterns MLX2 may be obtained by alternately selecting the plurality of second layout patterns MXL arranged apart from each other in the second horizontal direction (Y direction). The plurality of third even layout patterns MLY1 and the plurality of third odd layout patterns MLY2 may be obtained by alternately selecting the plurality of third layout patterns MLY arranged apart from each other in the first horizontal direction (X direction).

Referring to fig. 4A and 4B, the photomask sets PM1 and PM2 may include a first photomask PM1 and a second photomask PM2, the first photomask PM1 including a first mask pattern MK1, and the second photomask PM2 including a second mask pattern MK 2. The first mask pattern MK1 may include a plurality of first even mask patterns MKC1 arranged in the first region CELL, a plurality of second even mask patterns MKX1 arranged in the first line region CORE-H of the second region CORE, and a plurality of third even mask patterns MKY1 arranged in the second line region CORE-V of the second region CORE. The second mask pattern MK2 may include a plurality of first odd mask patterns MKC2 arranged in the first region CELL, a plurality of second odd mask patterns MKX2 arranged in the first line region CORE-H of the second region CORE, and a plurality of third odd mask patterns MKY2 arranged in the second line region CORE-V of the second region CORE.

The plurality of first even mask patterns MKC1, the plurality of second even mask patterns MKX1, and the plurality of third even mask patterns MKY1 may be formed from the plurality of first even layout patterns MLC1, the plurality of second even layout patterns MLX1, and the plurality of third even layout patterns MLY1, respectively. The plurality of first odd mask patterns MKC2, the plurality of second odd mask patterns MKX2, and the plurality of third odd mask patterns MKY2 may be formed from the plurality of first odd layout patterns MLC2, the plurality of second odd layout patterns MLX2, and the plurality of third odd layout patterns MLY2, respectively.

The plurality of first even mask patterns MKC1 and the plurality of first odd mask patterns MKC2 may be respectively arranged to have a pitch of the first cell pitch PXC in the first horizontal direction (X direction), and to have a pitch (2 × PYC) twice the second cell pitch PYC in the second horizontal direction (Y direction). The plurality of second even-numbered mask patterns MKX1 and the plurality of second odd-numbered mask patterns MKX2 may be respectively arranged to have a pitch (2 × PYL) twice the first core pitch PYL in the second horizontal direction (Y direction) as a minimum pitch. The plurality of third even-numbered mask patterns MKY1 and the plurality of third odd-numbered mask patterns MKY2 may be respectively arranged to have a pitch (2 × PXL) twice the second core pitch PXL in the first horizontal direction (X direction) as a minimum pitch.

Referring to fig. 5A and 5B, the photomask sets PM1a and PM2a may include a first photomask PM1a and a second photomask PM2a, the first photomask PM1a including a first mask pattern MK1a, and the second photomask PM2a including a second mask pattern MK2 a. The first mask pattern MK1a may include a plurality of first even mask patterns MKC1 arranged in the first region CELL, a plurality of second mask patterns MKX arranged in the first line region CORE-H of the second region CORE, and a plurality of third mask patterns MKY arranged in the second line region CORE-V of the second region CORE. The second mask pattern MK2a may include a plurality of second odd mask patterns MKC2 arranged in the first region CELL. The second mask patterns MK2a included in the second photomask PM2a may not be disposed in the second regions CORE.

The plurality of first even mask patterns MKC1, the plurality of first odd mask patterns MKC2, the plurality of second mask patterns MKX, and the plurality of third mask patterns MKY may be formed from the plurality of first even layout patterns MLC1, the plurality of first odd layout patterns MLC2, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY, respectively.

The plurality of first even mask patterns MKC1 and the plurality of first odd mask patterns MKC2 may be respectively arranged to have a pitch of the first cell pitch PXC in the first horizontal direction (X direction) and to have a pitch (2 × PYC) twice the second cell pitch PYC in the second horizontal direction (Y direction). The plurality of second mask patterns MKX may be arranged to have a pitch of the first core pitch PYL as a minimum pitch in the second horizontal direction (Y direction). The plurality of third mask patterns MKY may be arranged to have a pitch of the first core pitch PLY as a minimum pitch in the first horizontal direction (X direction).

Fig. 6 is a schematic top view for describing a process of dividing a mask layout for manufacturing a photomask set for forming a pattern according to example embodiments, and fig. 7A, 7B, 8A and 8B are each schematic top views of a photomask set for forming a pattern according to example embodiments.

Referring to fig. 6, the plurality of first layout patterns MLC are divided into a plurality of first even layout patterns MLC1b and a plurality of first odd layout patterns MLC2b, the plurality of second layout patterns MLX are divided into a plurality of second even layout patterns MLX1 and a plurality of second odd layout patterns MLX2, and the plurality of third layout patterns MLY are divided into a plurality of third even layout patterns MLY1 and a plurality of third odd layout patterns MLY 2.

Among the plurality of first layout patterns MLC, a pair of first layout patterns MLC, in which a distance between center points of two first layout patterns MLC adjacent to each other has a value greater than a second side distance L2 (see fig. 2B) which is a minimum distance value, may be selected, and the selected plurality of first layout patterns MLC may be divided into a plurality of first even layout patterns MLC1B and a plurality of first odd layout patterns MLC 2B. Each of the plurality of first even layout patterns MLC1B and the plurality of first odd layout patterns MLC2B may be obtained by selecting a pair of layout patterns MLC (in the pair of layout patterns MLC, a distance between center points of two first layout patterns MLC adjacent to each other is the first side distance L1 (see fig. 2B) having the maximum value) from the plurality of layout patterns MLC and grouping the pair of layout patterns. For example, the plurality of first even layout patterns MLC1b and the plurality of first odd layout patterns MLC2b may be obtained by alternately selecting rows arranged in a zigzag in the second horizontal direction (Y direction) from the plurality of first layout patterns MLC.

Referring to fig. 7A and 7B, the photomask sets PM1B and PM2B may include a first photomask PM1B and a second photomask PM2B, the first photomask PM1B including a first mask pattern MK1B, and the second photomask PM2B including a second mask pattern MK 2B. The first mask pattern MK1b may include a plurality of first even mask patterns MKC1b arranged in the first region CELL, a plurality of second even mask patterns MKX1 arranged in the first line region CORE-H of the second region CORE, and a plurality of third even mask patterns MKY1 arranged in the second line region CORE-V of the second region CORE. The second mask pattern MK2b may include a plurality of first odd mask patterns MKC2b included in the first region CELL, a plurality of second odd mask patterns MKX2 arranged in the first line region CORE-H of the second region CORE, and a plurality of third odd mask patterns MKY2 arranged in the second line region CORE-V of the second region CORE.

The plurality of first even mask patterns MKC1b, the plurality of second even mask patterns MKX1, and the plurality of third even mask patterns MKY1 may be formed from the plurality of first even layout patterns MLC1b, the plurality of second even layout patterns MLX1, and the plurality of third even layout patterns MLY1, respectively. The plurality of first odd mask patterns MKC2b, the plurality of second odd mask patterns MKX2, and the plurality of third odd mask patterns MKY2 may be formed from the plurality of first odd layout patterns MLC2b, the plurality of second odd layout patterns MLX2, and the plurality of third odd layout patterns MLY2, respectively, illustrated in fig. 6. The plurality of first even mask patterns MKC1b and the plurality of first odd mask patterns MKC2b may be arranged to have a pitch (2 × PXC) twice the first cell pitch PXC in the first horizontal direction (X direction) and to have a pitch of the second cell pitch PYC in the second horizontal direction (Y direction).

Referring to fig. 8A and 8B, the photomask sets PM1c and PM2c may include a first photomask PM1c and a second photomask PM2c, the first photomask PM1c including a first mask pattern MK1c, and the second photomask PM2c including a second mask pattern MK2 c. The first mask pattern MK1c may include a plurality of first even mask patterns MKC1b arranged in the first region CELL, a plurality of second mask patterns MKX arranged in the first line region CORE-H of the second region CORE, and a plurality of third mask patterns MKY arranged in the second line region CORE-V of the second region CORE. The second mask pattern MK2c may include a plurality of first odd mask patterns MKC2b arranged in the first region CELL. The second mask patterns MK2c included in the second photomask PM2c may not be disposed in the second regions CORE.

The plurality of first even mask patterns MKC1b, the plurality of first odd mask patterns MKC2b, the plurality of second mask patterns MKX, and the plurality of third mask patterns MKY may be formed from the plurality of first even layout patterns MLC1b, the plurality of first odd layout patterns MLC2b, the plurality of second layout patterns MLX, and the plurality of third layout patterns MLY, respectively, illustrated in fig. 6. The plurality of first even mask patterns MKC1b and the plurality of first odd mask patterns MKC2b may be respectively arranged to have a pitch (2 × PXC) twice the first cell pitch PXC in the first horizontal direction (X direction), and to have a pitch of the second cell pitch PYC in the second horizontal direction (Y direction).

Fig. 9A and 9B are schematic cross-sectional views of photomask sets 500-1 and 500-2 for patterning according to example embodiments.

Referring to fig. 9A and 9B, the photomask sets 500-1 and 500-2 may include a first photomask 500-1 and a second photomask 500-2, respectively. Although fig. 9A and 9B illustrate that the first and second photomasks 500-1 and 500-2 are reflective masks, the first and second photomasks 500-1 and 500-2 are not limited thereto. For example, the first and second photomasks 500-1 and 500-2 may be used in a photolithography process using Extreme Ultraviolet (EUV) light (e.g., light having a wavelength of 13.5 nm). The first photomask 500-1 may be any one of the first photomasks PM1, PM1a, PM1B, and PM1c shown in fig. 4A, 5A, 7A, and 8A, and the second photomask 500-2 may be any one of the second photomasks PM2, PM2a, PM2B, and PM2c shown in fig. 4B, 5B, 7B, and 8B.

The first and second photomasks 500-1 and 500-2 may each include a mask substrate 510 and a reflective layer 520, and include absorption patterns 530-1 and 530-2, respectively. The mask substrate 510 may include, for example, a glass or quartz substrate. The reflective layer 520 may be positioned on the mask substrate 510 and reflect incident light. The absorption patterns 530-1 and 530-2 may be formed on the reflective layer 520, and the reflective layer 520 may be exposed between the absorption patterns 530-1 and between the absorption patterns 530-2.

The reflective layer 520 may have a multi-layer structure in which thirty to sixty Mo/Si layers are repeatedly stacked, for example. In some embodiments, to protect the reflective layer, a cover layer 522 may be located on the reflective layer 520. The capping layer 522 may include, for example, ruthenium oxide (RuO) or the like. In some embodiments, the cover layer 522 may be omitted.

At the bottom of the mask substrate 510, a base layer 532 for vacuum-attaching the first and second photomasks 500-1 and 500-2 to a stage of an exposure apparatus may be formed. The base layer 532 may include, for example, a chromium nitride (CrN) layer.

The absorption patterns 530-1 and 530-2 may include a first absorption pattern 530-1 in the first photomask 500-1 and a second absorption pattern 530-2 in the second photomask 500-2. The first absorption pattern 530-1 may be any one of the first mask patterns MK1, MK1a, MK1B, and MK1c shown in fig. 4A, 5A, 7A, and 8A, and the second absorption pattern 530-2 may be any one of the second mask patterns MK2, MK2a, MK2B, and MK2c shown in fig. 4B, 5B, 7B, and 8B.

In some embodiments, a portion of the reflective layer 520 located between the first absorption patterns 530-1 may be any one of the first mask patterns MK1, MK1a, MK1B, and MK1c shown in fig. 4A, 5A, 7A, and 8A, and a portion of the reflective layer 520 located between the second absorption patterns 530-2 may be any one of the second mask patterns MK2, MK2a, MK2B, and MK2c shown in fig. 4B, 5B, 7B, and 8B, according to the type of photoresist used in a photolithography process.

Fig. 10A to 10H are sectional views illustrating stages in a method of forming a pattern by using a photomask set according to an example embodiment.

Referring to fig. 10A, on a base substrate 10, after sequentially stacking a target layer 20, a hard mask layer 40, and a first coating layer 50 are formed, a first photoresist layer 90 is formed. In some embodiments, a buffer layer 30 and an auxiliary layer 35, which are sequentially stacked, may also be formed between the target layer 20 and the hard mask layer 40. In some embodiments, a first cover layer 60 stacked on the first coating layer 50 may also be formed.

The base substrate 10 may include, for example, a semiconductor substrate. The base substrate 10 may further include a conductive material and an insulating layer disposed between the semiconductor substrate and the target layer 20. The target layer 20 may include a conductive material. For example, the target layer 20 may include polysilicon, metal, conductive metal nitride, and the like. For example, the buffer layer 30 may include an Amorphous Carbon Layer (ACL). The auxiliary layer 35 may prevent the buffer layer 30 from being exposed during the process of patterning the hard mask layer 40. For example, hard mask layer 40 may comprise tetraethyl orthosilicate (TEOS). For example, the first coating layer 50 may be a spin on hard mask (SOH). The first cover layer 60 may protect the top surface of the first coating layer 50. For example, the first capping layer 60 may include silicon oxynitride (SiON).

Referring to fig. 10A and 10B, a first photoresist pattern 92 is formed from the first photoresist layer 90 by using a first photomask. For example, the first photomask may be any one of the first photomasks PM1a, PM1c, and 500-1 shown in fig. 5A, 8A, and 9A, but is not limited thereto. For example, the first photomask may be any one of the first photomasks PM1 and PM1B shown in fig. 4A and 7A, and in this case, the number of the first photoresist patterns 92 may be less than the number of the first photoresist patterns 92 in the second region CORE shown in fig. 10B.

Referring to fig. 10B and 10C, a preliminary hard mask pattern 52 may be formed by patterning the first overcoat layer using the first photoresist pattern 92 as an etch mask. In some embodiments, overlay pattern 62, which is part of first overlay layer 60, may be left on preliminary hard mask pattern 52.

Referring to fig. 10C and 10D, the hard mask layer 40 is patterned by using the preliminary hard mask pattern 52 as an etch mask to form a first hard mask pattern 42.

Referring to fig. 10E, after forming the second overcoat layer 70 covering the first hard mask pattern 42, a second photoresist layer 95 is formed. In some embodiments, a second cover layer 80 stacked on the second coating layer 70 may also be formed. The second coating layer 70 may include a carbonaceous material. For example, the second coating layer 70 may include SOH. The second cover layer 80 may protect the top surface of the second coating layer 70. For example, the second capping layer 80 may include SiON.

Referring to fig. 10E and 10F, a second photoresist pattern 97 is formed from the second photoresist layer 95 by using a second photomask. For example, the second photomask may be any one of the second photomasks PM2a, PM2c, and 500-2 shown in fig. 5B, 8B, and 9B, but is not limited thereto. For example, the second photomask may be any one of the second photomasks PM2 and PM2B shown in fig. 4B and 7B, in which case the second photoresist pattern 97 may also be patterned in the second region CORE and expose a portion of each of the second coating layer 70 and the second cover layer 80.

Referring to fig. 10F and 10G, the second overcoat layer 70 is patterned by using the second photoresist pattern 97 as an etch mask to form a second hard mask pattern 72. In some embodiments, a portion of the second capping layer 80 may remain on the second hard mask pattern 72, similar to the capping pattern 62 remaining on the preliminary hard mask pattern 52, which is not shown in fig. 10G but is shown in fig. 10C.

Referring to fig. 10G and 10H, the target layer 20 is patterned by using the first and second hard mask patterns 42 and 72 as an etching mask to form the target pattern 22. Although the formation of the target pattern 22 by the PEPE (photo-mask-etch-photo-mask-etch) method is described with reference to fig. 10A to 10H, the present disclosure is not limited thereto, and the present disclosure may include the formation of the target pattern 22 by using a photomask set including two or more photomasks and the formation of the target pattern 22 by the PPE (photo-mask-etch) method.

Fig. 11A is a schematic top-view layout for describing main configurations of the semiconductor device 1 manufactured by using the photomask set according to the example embodiment, and fig. 11B is a top-view layout selectively showing some of the main configurations shown in fig. 11A.

Referring to fig. 11A and 11B, the semiconductor device 1 may include a plurality of active regions ACT. In some embodiments, the plurality of active regions ACT may each have a long axis in a diagonal direction of a first horizontal direction (X direction) and a second horizontal direction (Y direction) perpendicular to each other. The plurality of word lines WL intersecting the plurality of active regions ACT may extend parallel to each other in the first horizontal direction (X direction). Above the plurality of word lines WL, a plurality of bit lines BL may extend parallel to each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The plurality of bit lines BL may be connected to the plurality of active regions ACT via direct contacts DC.

In some embodiments, among the plurality of bit lines BL, a plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other. In some embodiments, the plurality of buried contacts BC may be arranged in a matrix aligned in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

A plurality of landing pads (landing pads) LP may be located on the plurality of buried contacts BC. The plurality of landing pads LP may be arranged to at least partially overlap the plurality of buried contacts BC. In some embodiments, the plurality of landing pads LP may each extend onto any one of two bit lines BL adjacent to each other. In a plane, the plurality of landing pads LP may be arranged to be aligned continuously in the first horizontal direction (X direction) and aligned in a zigzag in the second horizontal direction (Y direction).

The plurality of landing pads LP may be formed by performing a photolithography process twice. For example, the plurality of landing pads LP may be formed by performing the EUV process twice without using a pattern density enhancement technique of performing a photolithography process once. The top surface of each of the plurality of landing pads LP may have a disk shape with sides that are substantially circular rather than elliptical.

The plurality of storage nodes SN may be located on a plurality of landing pads LP. A plurality of storage nodes SN may be located above a plurality of bit lines BL. Each storage node SN may be a lower electrode of each of the plurality of capacitors. The storage node SN may be connected to the active region ACT via the landing pad LP and the buried contact BC. On the plane, the plurality of storage nodes may have a hexagonal arrangement structure. For example, the plurality of storage nodes SN may have a honeycomb shape arranged in a row in a first horizontal direction (X direction) and in a zigzag in a second horizontal direction (Y direction) on a plane.

The cell shape in which the plurality of landing pads LP are arranged and the cell shape in which the plurality of storage nodes SN are arranged may be different from each other. For example, the storage nodes SN may be arranged in a full honeycomb shape HMS in which a triangle connecting center points of three storage nodes SN adjacent to each other is an equilateral triangle, and the plurality of landing pads LP may be arranged in a squashed honeycomb shape HML in which a triangle connecting center points of three landing pads LP adjacent to each other is a scalene triangle. In this specification, the center point of the landing pad LP and the center point of the storage node SN denote the center point of the top surface of the landing pad LP and the center point of the top surface of the storage node SN on the plane (X-Y plane), respectively.

The plurality of landing pads may be aligned in a squashed honeycomb shape HML and respectively arranged between the plurality of buried contacts BC aligned in the matrix RMB and the plurality of storage nodes SN aligned in a full honeycomb shape HMS, and electrically connect the plurality of buried contacts BC to the plurality of storage nodes SN, respectively.

Fig. 12A to 12C are schematic top-view layouts for describing the arrangement of landing pads LP included in a semiconductor device manufactured by using a photomask set according to example embodiments.

Referring to fig. 12A, the plurality of landing pads LP may have a hexagonal alignment structure on a plane. For example, the plurality of landing pads LP may have a honeycomb shape arranged in a row in the first horizontal direction (X direction) and arranged in a zigzag in the second horizontal direction (Y direction). To describe the arrangement of the plurality of landing pads LP, fig. 12A shows the plurality of landing pads LP and the plurality of virtual reference landing pads LPR. The plurality of reference landing pads LPR indicates a case where a triangle connecting center points LPR-C of three reference landing pads LPR adjacent to each other is an equilateral triangle. The diameter of the reference landing pad LPR can have the same value as the diameter DI-L of the landing pad LP.

For example, among three reference landing pads LPR adjacent to each other, the first reference interior angle θ 1-R, the second reference interior angle θ 2-R, and the third reference interior angle may each have the same value, wherein the first reference interior angle θ 1-R and the second reference interior angle θ 2-R are respective interior angles between a base connecting the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X-direction) and two sides connecting the center points LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X-direction) and one adjacent reference landing pad LPR in the second horizontal direction (Y-direction), respectively, and the third reference interior angle is an interior angle between two sides connecting the center points LPR pad LPR of two adjacent reference landing pads LPR in the first horizontal direction (X-direction), respectively C is connected to the center point LPR-C of one adjacent reference landing pad LPR in the second horizontal direction (Y-direction). For example, the first reference interior angle θ 1-R, the second reference interior angle θ 2-R, and the third reference interior angle θ 3-R may each be 60 °.

Among the three reference landing pads LPR adjacent to each other, the reference bottom side distance LB-R, which is a distance between the centerpoints LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction), and the first and second reference side distances LS-R1 and LS-R2, which are respective distances LS-R1 and LS-R2 between the centerpoints LPR-C of two adjacent reference landing pads LPR in the first horizontal direction (X direction) and the centerpoints LPR-C of one adjacent reference landing pad LPR in the second horizontal direction (Y direction), may each have the same 3F (characteristic dimension) value. For example, 3F (feature size) may have a value of about 25.6nm, but is not limited thereto.

A triangle connecting three landing pads LP adjacent to each other among the plurality of landing pads (for example, a center point LP-C of two adjacent landing pads LP in the first horizontal direction (X direction) and a center point LP-C of one landing pad LP adjacent to the two adjacent landing pads LP in the first horizontal direction (X direction) in the second horizontal direction (Y direction)) may be a scalene triangle. Among the plurality of landing pads LP, among three landing pads LP adjacent to each other such that a line connecting the center points LP-C constitutes a triangle, two landing pads LP adjacent to each other in the first horizontal direction (X direction) are referred to as a first landing pad LP1 and a second landing pad LP2, respectively, and a landing pad LP adjacent to the first landing pad LP1 and the second landing pad LP2 in the second horizontal direction (Y direction) between the first landing pad LP1 and the second landing pad LP2 may be referred to as a third landing pad LP 3.

The first interior angle θ 1 and the second interior angle θ 2 may have different values, respectively, where the first interior angle θ 1 is an interior angle between a base of a center point LP-C connecting the first landing pad LP1 and the second landing pad LP2 and a side connecting the first landing pad LP1 to the third landing pad LP3, and the second interior angle θ 2 is an interior angle between a base of a center point LP-C connecting the first landing pad LP1 and the second landing pad LP2 and a side connecting the second landing pad LP2 to the third landing pad LP 3. For example, the first interior angle θ 1 may have a value less than 60 °, and the second interior angle θ 2 may have a value greater than 60 °. The third interior angle θ 3 may have a value obtained by subtracting a value of the first interior angle θ 1 and a value of the second interior angle θ 2 from 180 °, where the third interior angle θ 3 is an interior angle between a side connecting the first landing pad LP1 to the third landing pad LP3 and a side connecting the second landing pad LP2 to the third landing pad LP 3.

The base side distance LB, which is the distance between the center point LP-C of the first landing pad LP1 and the center point LP-C of the second landing pad LP2, the first side distance LS1, which is the distance between the center point LP-C of the first landing pad LP1 and the center point LP-C of the third landing pad LP3, the first side distance LS 355, which is the distance between the center point LP-C of the second landing pad LP2 and the center point LP-C of the third landing pad LP3, the first side distance LS1, and the second side distance LS2 may have different values. The bottom side distance LB may have a value of 3F (characteristic dimension), which is the same value as the reference side distance LB-R. The first side distance LS1 may have a value greater than the bottom distance LB and the second side distance LS2 may have a value less than the bottom distance LB. For example, the first side distance LS1 may have a value greater than 3F (feature size) and the second side distance LS2 may have a value less than 3F (feature size).

The center point LP-C of each of the plurality of landing pads may be offset from the center point LPR-C of each of the plurality of reference landing pads LPR and from the bit line BL adjacent thereto in the first horizontal direction (X direction) or a direction opposite to the first horizontal direction (X direction) (-X direction). For example, the center points LP-C of the landing pads LP constituting a row in the first horizontal direction (X direction) may be offset from the center points LPR-C of the reference landing pads LPR constituting a row in the first horizontal direction (X direction) by a first offset distance CD1 in the first horizontal direction (X direction), and the center points LP-C of the landing pads LP adjacent to each other in the second horizontal direction and constituting another row in the first horizontal direction (X direction) may be offset from the center points LPR-C of the reference landing pads LPR constituting another row in the first horizontal direction (X direction) by a second offset distance CD2 in a direction opposite to the first horizontal direction (X direction). In some embodiments, the first offset distance CD1 and the second offset distance CD2 may have the same value. For example, the first offset distance CD1 and the second offset distance CD2 may each have a value greater than 0 and less than 0.75F (feature size). In some embodiments, first offset distance CD1 and second offset distance CD2 may each have a value of about 1nm to about 6 nm.

The first shift distance CM1 and the second shift distance CM2 shown in fig. 2B, which are logical distances on the mask layout, respectively, and the first offset distance CD1 and the second offset distance CD2, which are physical distances shown in fig. 12A, may have substantially the same values.

The plurality of landing pads LP according to example embodiments may be formed by performing the EUV photolithography process twice without using a pattern density enhancement technique in which the photolithography process is performed once. Thus, the top surface of each of the plurality of landing pads LP may have a disk shape with sides that are substantially circular rather than elliptical or quadrilateral.

Referring to FIG. 12B, a plurality of storage nodes SN may be located on a plurality of landing pads LP. As described above with reference to fig. 11A and 11B, the landing pads LP may be arranged in a squashed honeycomb shape. The plurality of storage nodes SN may be arranged in a complete honeycomb shape. The diameter DI-S of storage node SN may have a value substantially equal to the diameter DI-L of landing pad LP. For example, the diameter DI-S of storage node SN and the diameter DI-L of landing pad LP may have a value of approximately 1.5F (feature size).

A triangle connecting the center point LP-C of the first landing pad LP1, the center point LP-C of the second landing pad LP2, and the center point LP-C of the third landing pad LP3 may be a scalene triangle, and a triangle connecting the center points SN-C of the three storage nodes SN corresponding to the first landing pad LP1, the second landing pad LP2, and the third landing pad LP3, respectively, may be an equilateral triangle. For example, distances between center points SN-C of the three storage nodes SN corresponding to the first, second, and third landing pads LP1, LP2, and LP3, respectively, may have the same value, i.e., a value of 3F (feature size). Accordingly, the first, second, and third intra-node angles θ 1-S, θ 2-S, and θ 3-S of the triangle connecting the center points SN-C of the three storage nodes SN corresponding to the first, second, and third landing pads LP1, LP2, and LP3, respectively, may have the same value of 60.

Referring to fig. 12C, the center point LP-C of the third landing pad LP3 is spaced apart by a center transfer distance TCD in the first horizontal direction (X direction) from a center of a bottom line connecting the center point LP-C of the first landing pad LP1 and the center point LP-C of the second landing pad LP2 and a virtual center extension line HVL extending in the second horizontal direction (Y direction) which is a vertical direction connecting the center point LP-C of the first landing pad LP1 and a side of the center point LP-C of the second landing pad LP 2. The center point LP-C of the third landing pad LP3 may be offset from the center extension line HVL by a center transfer distance TCD in the first horizontal direction (X-direction). The value of the center transfer distance TCD may be the sum of the first offset distance CD1 and the second offset distance CD2 shown in fig. 12A. The center transfer distance TCD may have a value greater than 0 and less than half of the bottom edge distance LB. For example, the value of the center transfer distance TCD may be greater than 0 and less than 1.5F (feature size). In some embodiments, the center transfer distance TCD may have a value of about 2nm to about 12 nm.

Fig. 13A through 13B are schematic top-view layouts for sorting and describing landing pads included in a semiconductor device formed corresponding to photomasks included in a photomask set according to example embodiments.

Referring to fig. 13A, the plurality of landing pads LP may include a first landing pad LP1 and a second landing pad LP 2. The first landing pad LP1 may be formed from a plurality of first even mask patterns MKC1 included in the first photomask PM1 shown in fig. 4A or the first photomask PM1a shown in fig. 5A, and the second landing pad LP2 may be formed from a plurality of first odd mask patterns MKC2 included in the second photomask PM2 shown in fig. 4B or the second photomask PM2a shown in fig. 5B. The distance between the center points of the two first landing pads LP1 adjacent to each other may be the base distance LB having a value greater than that of the second side distance L2.

Referring to fig. 13B, the plurality of landing pads LP may include a first landing pad LP1a and a second landing pad LP2 a. The first landing pad LP1 may be formed from a plurality of first even mask patterns MKC1B included in the first photomask PM1B shown in fig. 7A or the first photomask shown in fig. 8A, and the second landing pad LP2 may be formed from a plurality of first odd mask patterns MKC2B included in the second photomask PM2B shown in fig. 7B or the second photomask PM2c shown in fig. 8B. A distance between center points of two first landing pads LP1 adjacent to each other may be the first side distance L1 having a value greater than the value of the second side distance L2 and the value of the bottom distance LB.

Referring to fig. 13A and 13B, the plurality of landing pads LP may be formed by grouping the landing pads LP adjacent to each other, wherein a bottom side distance LB or a first side distance L1 of the landing pads LP adjacent to each other has a value greater than a second side distance L2 having a minimum value of a distance between center points LP-C of the two landing pads LP adjacent to each other, and each performing a photolithography process two or more times using two or more photomasks. Therefore, as described above in fig. 12A, even if the center point LP-C of each of the plurality of landing pads LP is offset from the center point LPR-C of each of the plurality of reference landing pads LP and the distance between two landing pads LP adjacent to each other is reduced, the plurality of landing pads LP can be formed without being affected.

Fig. 14A to 21D are sectional views illustrating stages in a method of manufacturing a semiconductor device according to an example embodiment. Fig. 14A, 15A, 16A, 17A, 18A, 19A, 20A, and 21A correspond to a cross section along the line a-a' of fig. 11A. Fig. 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 21B correspond to a cross section along the line B-B' of fig. 11A. Fig. 14C, 15C, 16C, 17C, 18C, 19C, 20C, and 21C correspond to a section along the line C-C' of fig. 11A. Fig. 14D, 15D, 16D, 17D, 18D, 19D, 20D, and 21D correspond to a cross section along the line D-D' of fig. 11A.

Referring to fig. 14A through 14D, a device isolation trench 116T may be formed on the substrate 110, and an isolation layer 116 filling the device isolation trench 116T may be formed. The substrate 110 may include a semiconductor material, such as silicon (Si). The isolation layer 116 may include a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, for example. A plurality of active regions 118 may be defined on the substrate 110 by the isolation layer 116. As with the active region ACT shown in fig. 11A, the active regions 118 may each be a relatively long island shape having a short axis and a long axis.

A plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may each have a line shape extending in parallel in the first horizontal direction (X direction), intersecting the active region 118, and arranged at substantially equal intervals in the second horizontal direction (Y direction). In some embodiments, a step may be formed at the bottom surface of the plurality of word line trenches 120T. After cleaning the product of forming the plurality of word line trenches 120T, a plurality of gate dielectric films 122, a plurality of word lines 120, and a plurality of buried insulators 124 may be sequentially formed in the plurality of word line trenches 120T. The plurality of word lines 120 may constitute a plurality of word lines WL illustrated in fig. 11A. The plurality of word lines may have line shapes extending parallel to each other in the first horizontal direction (X direction), respectively crossing the active regions 118, and arranged substantially at equal intervals in the second horizontal direction (Y direction). A top surface of each wordline of the plurality of wordlines 120 may be located at a lower level than a top surface of the substrate 110. For example, the plurality of word lines 120 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof.

The gate dielectric film 122 may include at least one of: such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide/nitride/oxide (ONO) or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film.

The top surfaces of the plurality of buried insulators 124 may be located at substantially the same level as the level of the top surface of the substrate 110. Buried insulator 124 may include at least one of: such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

Referring to fig. 15A through 15D, insulator patterns 112 and 114 are formed covering the isolation layer 116, the plurality of active regions 118, and the plurality of buried insulators 124. For example, the insulator patterns 112 and 114 may include at least one of: a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal based dielectric film, or a combination thereof. In some embodiments, the insulator patterns 112 and 114 may be formed by stacking a plurality of insulators including the first insulator pattern 112 and the second insulator pattern 114. In some embodiments, the first insulator pattern 112 may include a silicon oxide film, and the second insulator pattern 114 may include a silicon oxynitride film. Thereafter, direct contact holes 134H are formed through the insulator patterns 112 and 114. The direct contact hole 134H may be formed to expose the source region in the active region 118. In some embodiments, the direct contact hole 134H may extend into the active region 118, i.e., into the source region.

Referring to fig. 16A to 16D, a direct contact conductive layer filling the direct contact hole 134H and covering the insulator patterns 112 and 114 is formed. In some embodiments, the conductive layer for direct contact may comprise doped polysilicon. Next, after sequentially forming a metal-based conductive layer and an insulating capping layer for capping the insulator patterns 112 and 114 and directly contacting the conductive layers and forming the bit line structure 140, the first metal-based conductive layer, the second metal-based conductive layer, and the insulating capping layer are etched to form a plurality of bit lines 147 and a plurality of insulating capping lines 148, the plurality of bit lines 147 including first metal-based conductive patterns 145 and second metal-based conductive patterns 146 in a line shape. In some embodiments, the first metal-based conductive pattern 145 may include titanium nitride (TiN) or Ti-Si-n (tsn), and the second metal-based conductive pattern 146 may include tungsten (W) or W and tungsten silicide (WSi)_x). One bit line 147 and one insulating cover line 148 covering the one bit line 147 may together constitute one bit line structure 140. The plurality of bit line structures 140 including the plurality of bit lines 147 and the plurality of insulating cover lines 148 may each extend in parallel in a second horizontal direction (Y direction) parallel to the main surface of the substrate 110. The plurality of bit lines 147 may constitute the plurality of bit lines BL shown in fig. 11A. In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 disposed between the insulator patterns 112 and 114 and the first metal-based conductive pattern 145. The conductive semiconductor pattern 132 may include doped polysilicon.

In the etching process for forming the plurality of bit lines 147, a portion of the direct contact conductive layer that does not vertically overlap the bit lines may be removed by the etching process to form the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 may constitute the direct contact DC shown in fig. 11A. The plurality of bit lines 147 may be electrically connected to the plurality of active regions 118 through the plurality of direct contact conductive patterns 134.

Both sidewalls of each of the plurality of bitline structures 140 may be covered by insulating spacer structures 150. The plurality of insulating spacer structures 150 may each include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a dielectric constant lower than that of the first and third insulating spacers 152 and 156. In some embodiments, the second insulating spacer 154 including an oxide film may be removed in a subsequent process, and may be an air spacer.

A plurality of buried contact holes 170H may be formed between the plurality of bit lines 147. Between two bit lines 147 of the plurality of bit lines 170, an inner surface of the plurality of buried contact holes 170H may be defined by the insulating spacer structure 150 and the active region 118 covering sidewalls of each of the two bit lines. The plurality of buried contact holes 170H may be formed by using a portion of each of the insulator patterns 112 and 114 and the active region 118 and by using the insulating spacer structure 150 covering both sidewalls of each of the plurality of bit line structures 140.

Referring to fig. 17A to 17D, a plurality of buried contacts 170 and a plurality of insulating fences (ferces) 180 are formed between the plurality of insulating spacer structures 150, wherein the plurality of insulating spacer structures 150 each cover both sidewalls of each of the plurality of bit line structures 140. The plurality of buried contacts 170 and the plurality of insulating fences 180 may be alternately arranged between pairs of insulating spacer structures 150 of the plurality of insulating spacer structures 150, wherein the plurality of insulating spacer structures 150 each cover (i.e., in the second horizontal direction (Y-direction)) both sidewalls of each of the plurality of bit line structures 140. For example, the plurality of buried contacts 170 may include polysilicon. For example, the plurality of insulation barriers 180 may include a nitride film. In some embodiments, the plurality of buried contacts 170 may be arranged along a line in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). Each buried contact 170 may extend from the active region 118 in a vertical direction (Z-direction) perpendicular to the substrate 110. The buried contact 170 may constitute a plurality of buried contacts BC shown in fig. 11A. The plurality of buried contacts 170 may be arranged in a space defined by the plurality of insulating fences and the plurality of insulating spacer structures 150, wherein the plurality of insulating spacer structures 150 each cover both sidewalls of each of the plurality of bit line structures 140. The plurality of buried contacts 170 may each fill a lower portion of a space between the plurality of insulating spacer structures 150, wherein the plurality of insulating spacer structures 150 each cover both sidewalls of each of the plurality of bit line structures 140.

The level of the top surface of the plurality of buried contacts 170 may be lower than the level of the top surface of the plurality of insulating cover lines 148. The top surfaces of the plurality of insulation fences 180 and the top surfaces of the plurality of insulation cover lines 148 may be located at the same level with respect to the vertical direction (Z direction).

A plurality of landing pad holes 190H may be defined by the plurality of insulating spacer structures 150 and the plurality of insulating fences 180. The plurality of buried contacts 170 may be exposed at the bottom of the plurality of landing pad holes 190H.

Referring to fig. 18A through 18D, after filling the plurality of landing via holes 190H and forming a landing pad material layer 190P covering the plurality of bit line structures, a plurality of first hard mask patterns HMK1 are formed on the landing pad material layer 190P. The plurality of first hard mask patterns HMK1 may be formed by, for example, an EUV lithography process. The plurality of first hard mask patterns HMK1 on the landing pad material layer 190P may be formed by a method similar to the method of manufacturing the first hard mask pattern 42 on the target layer 20 described with reference to fig. 10A to 10D. In some embodiments, the buffer layer 30 and the auxiliary layer 35 shown in fig. 10A may also be disposed between the landing pad material layer 190P and the first hard mask pattern HMK 1. In some embodiments, the landing pad material layer 190P may include a conductive barrier film and a conductive pad material layer over the conductive barrier film. In some embodiments, the conductive barrier film may have a Ti/TiN stack structure. In some embodiments, the conductive pad material layer may include tungsten (W).

Referring to fig. 19A to 19D, a plurality of second hard mask patterns HMK2 are formed on the landing pad material layer 190P. The plurality of second hard mask patterns HMK2 may be formed by, for example, an EUV lithography process. The plurality of second hard mask patterns HMK2 may be spaced apart from the plurality of first hard mask patterns HMK1 and disposed between the plurality of first hard mask patterns HMK 1. The plurality of second hard mask patterns HMK2 may be formed in a method similar to the method of manufacturing the second hard mask patterns 72 described with reference to fig. 10E to 10G.

Referring to fig. 20A through 20D, a plurality of landing pads 190 filling at least a portion of the plurality of landing pad holes 190H and extending onto the plurality of bit line structures 140 are formed. A plurality of landing pads 190 may be disposed on the plurality of buried contacts 170 and extend onto the plurality of bit line structures 140. In some embodiments, a plurality of landing pads 190 may extend onto a plurality of bit lines 147. Since the plurality of landing pads 190 are disposed on the plurality of buried contacts 170, the plurality of buried contacts 170 and the plurality of landing pads 190 corresponding to each other may be electrically connected to each other. A plurality of landing pads 190 may be connected to the active region 118 by a plurality of buried contacts 170. The plurality of landing pads 190 may constitute the plurality of landing pads LP shown in fig. 11A.

The buried contact 170 may be disposed between two bitline structures 140 adjacent to each other, and the landing pad 190 may extend from between two bitline structures 140 adjacent to each other with the buried contact 170 therebetween onto one bitline structure 140. The plurality of landing pads 190 may be a portion of the landing pad material layer 190P obtained by removing a portion of the landing pad material layer 190P using the hard mask pattern HMK including the plurality of first and second hard mask patterns HMK1 and HMK2 shown in fig. 18A to 19D as an etch mask, and then may be separated into a plurality by using the recess cells 190R. The plurality of landing pads 190 may be spaced apart from each other with the recess unit 190R therebetween.

Referring to fig. 21A to 21D, a plurality of lower electrodes 210, a capacitor dielectric film 220, and an upper electrode 230 may be sequentially formed on the plurality of landing pads 190 to form the semiconductor memory device 1 including a plurality of capacitor structures 200. The plurality of lower electrodes 210 may be electrically connected to the plurality of landing pads 190, respectively, and correspond to the plurality of landing pads 190, respectively. The capacitor dielectric film 220 may conformally cover the plurality of lower electrodes 210. The upper electrode 230 may cover the capacitor dielectric film 220. The upper electrode 230 may face the lower electrode 210, and the capacitor dielectric film 220 is positioned between the upper electrode 230 and the lower electrode 210. In a certain region, the capacitor dielectric film 220 and the upper electrode 230 may be integrally formed to cover the plurality of lower electrodes 210. The plurality of lower electrodes 210 may constitute the plurality of storage nodes SN illustrated in fig. 11A.

The plurality of lower electrodes 210 may have a cylindrical shape filled with a circular horizontal cross-section, i.e., a pillar shape, but is not limited thereto. In some embodiments, the plurality of lower electrodes 210 may each have a cylindrical shape with a sealed bottom. In some embodiments, the plurality of lower electrodes 210 may be arranged in a honeycomb shape aligned in a zigzag with respect to the first horizontal direction (X direction) or the second horizontal direction (Y direction). The plurality of lower electrodes 210 may include, for example, silicon doped with impurities, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not shown, the semiconductor memory device 1 may further include at least one support pattern contacting sidewalls of the plurality of lower electrodes 210.

Prior to forming the plurality of capacitor structures 200, an insulator structure 195 filling the recessed cell 190R may be formed. Although fig. 21A and 21C show that the top surface of the insulator structure 195 and the bottom surface of the lower electrode 210 are at the same level, it is not limited thereto. For example, the level of the top surface of the insulator structure 195 may be higher than the level of the bottom surface of the lower electrode 210, and the lower electrode 210 may extend into the insulator structure 195 toward the substrate 110.

In the semiconductor memory device 1 according to the present disclosure, the center points of the plurality of landing pads 190 are offset from the adjacent bit line structures 140, and therefore, the width in the first horizontal direction (X direction) of the plurality of landing pads 190 extending in the vertical direction (Z direction) along the sidewalls of the adjacent bit line structures 140 can be lengthened. Accordingly, an overlap margin (margin) between the landing pad 190 and the buried contact 170 corresponding to each other increases, and reliability of the electrical connection between the landing pad 190 and the buried contact 170 corresponding to each other may increase. In addition, since the distance in the first horizontal direction (X direction) between one landing pad 190 and the buried contact 170 connected to another landing pad 190 adjacent to the one landing pad 190 is increased, it is possible to prevent the occurrence of bridging between the landing pad and the buried contact 170 adjacent to the landing pad 190.

Additionally, the top surface of each of the plurality of landing pads 190 may have a disk shape with sides that are substantially circular rather than elliptical. Accordingly, since the separation distance between the plurality of landing pads 190 is increased, the occurrence of bridging between adjacent landing pads 190 can be prevented, and the blanket fill property of the insulator structure 195 filled between the plurality of landing pads can be improved. Accordingly, the reliability of electrical insulation between the plurality of landing pads 190 may be improved.

The methods, processes, and/or operations described herein (e.g., preparation, grouping, dividing, etc. of a pattern layout) may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device (e.g., via simulations to be performed when processing a physical layer on a substrate). The computer, processor, controller or other signal processing device may be those described herein or may be one in addition to the elements described herein. Because algorithms forming the basis of the methods (or the operation of a computer, processor, controller or other signal processing device) are described in detail, the code or instructions for carrying out the operations of the method embodiments may transform the computer, processor, controller or other signal processing device into a special purpose processor for performing the methods described herein.

Additionally, another embodiment may include a computer-readable medium, e.g., a non-transitory computer-readable medium, for storing the code or instructions described above. The computer-readable medium may be volatile or non-volatile memory or other storage device, which may be removably or fixedly coupled to a computer, processor, controller, or other signal processing device that is to execute code or instructions for performing the method embodiments described herein.

By way of summary and review, example embodiments provide a method of manufacturing a photomask set that may be used to reduce the difficulty of a process of forming a pattern in a process of manufacturing a semiconductor device and a method of manufacturing a semiconductor device by using the photomask set.

Example embodiments have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to one of ordinary skill in the art at the time of filing the present application, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless explicitly stated otherwise. It will, therefore, be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.