阅读说明：本技术 一种移位寄存器、显示面板、驱动方法及显示装置 (Shift register, display panel, driving method and display device ) 是由 刘炳麟 吴桐 于 2020-12-31 设计创作，主要内容包括：本发明公开移位寄存器、显示面板、驱动方法及显示装置。包括：多个级联的移位寄存单元；每一移位寄存单元包括锁存模块、至少一个扫描开关模块和至少一个发光控制开关模块；锁存模块用于响应所述时钟信号输入端输入的时钟信号,锁存上级移位信号输入端输入的上级移位信号,并通过下级移位信号输出端输出；扫描开关模块用于响应下级移位信号输出端输出的下级移位信号,将扫描信号输入端输入的扫描信号通过扫描信号输出端输出；发光控制开关模块用于响应下级移位信号输出端输出的下级移位信号,将发光控制信号输入端输入的发光控制信号通过发光控制信号输出端输出。可以减小移位寄存器所在非显示区的面积,满足显示设备窄边框的需求。(The invention discloses a shift register, a display panel, a driving method and a display device. The method comprises the following steps: a plurality of cascaded shift register units; each shift register unit comprises a latch module, at least one scanning switch module and at least one light-emitting control switch module; the latch module is used for responding to a clock signal input by the clock signal input end, latching a superior shift signal input by the superior shift signal input end and outputting the superior shift signal through the inferior shift signal output end; the scanning switch module is used for responding to the lower-level shifting signal output by the lower-level shifting signal output end and outputting the scanning signal input by the scanning signal input end through the scanning signal output end; the light-emitting control switch module is used for responding to the lower-level shift signal output by the lower-level shift signal output end and outputting the light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end. The area of the non-display area where the shift register is located can be reduced, and the requirement of a narrow frame of the display device is met.)

1. A shift register, comprising: a plurality of cascaded shift register units; each shift register unit comprises a latch module, at least one scanning switch module and at least one light-emitting control switch module;

each shift register unit further comprises a clock signal input end, a superior shift signal input end, a subordinate shift signal output end, a scanning signal input end, a light-emitting control signal input end, a scanning signal output end and a light-emitting control signal output end;

the latch module is respectively and electrically connected with the clock signal input end, the upper shift signal input end and the lower shift signal output end; the latch module is used for responding to a clock signal input by the clock signal input end, latching a superior shift signal input by the superior shift signal input end and outputting the superior shift signal through the inferior shift signal output end;

the scanning switch module is electrically connected with the scanning signal input end, the scanning signal output end and the lower-level shifting signal output end respectively; the scanning switch module is used for responding to the lower-level shifting signal output by the lower-level shifting signal output end and outputting the scanning signal input by the scanning signal input end through the scanning signal output end;

the light-emitting control switch module is electrically connected with the light-emitting control signal input end, the light-emitting control signal output end and the lower-level shift signal output end respectively; the light-emitting control switch module is used for responding to a lower-level shift signal output by the lower-level shift signal output end and outputting a light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end;

the clock signal input end comprises a first clock signal input end and a second clock signal input end; the latch modules in the odd-numbered shift register units are electrically connected with the first clock signal input end, and the latch modules in the even-numbered shift register units are electrically connected with the second clock signal input end.

2. The shift register of claim 1, wherein the scan switch module comprises a first nand gate; the first input end of the first NAND gate is electrically connected with the shift signal output end of the next stage, the second input end of the first NAND gate is electrically connected with the scan signal input end, and the output end of the first NAND gate is electrically connected with the scan signal output end.

3. The shift register according to claim 2, wherein the scan switch module further comprises a first voltage range adjusting unit; a first input end of the first voltage range adjusting unit is electrically connected with the lower-level shift signal output end, a second input end of the first voltage range adjusting unit is electrically connected with the scan signal input end, and an output end of the first nand gate is electrically connected with a third input end of the first voltage range adjusting unit;

the first voltage range adjusting unit is used for responding to a lower shift signal output by the lower shift signal output end and a scanning signal input by the scanning signal input end, and adjusting the potential output by the first NAND gate to be switched between a first potential V1 and a second potential V2 and between a third potential V3 and a fourth potential V4; wherein | V2-V1| < | V4-V3 |.

4. The shift register according to claim 3, wherein the first voltage range adjusting unit includes a first level shifter, a second NAND gate, and a first inverter;

the input end of the first level conversion unit is electrically connected with the lower-level shift signal output end, and the output end of the first level conversion unit is electrically connected with the first input end of the second NAND gate;

the input end of the second level conversion unit is electrically connected with the scanning signal input end, and the output end of the second level conversion unit is electrically connected with the second input end of the second NAND gate;

the output end of the first NAND gate is electrically connected with the first power input end of the first inverter;

the output end of the second NAND gate is electrically connected with the second power input end of the first inverter; the input end of the first phase inverter is grounded, and the output end of the first phase inverter is electrically connected with the scanning signal output end.

5. The shift register of claim 4, further comprising a third NAND gate;

the first input end of the third NAND gate is electrically connected with the lower-level shift signal output end, and the second input end of the third NAND gate and the second input end of the first NAND gate are both electrically connected with the same scanning signal input end;

the output end of the third NAND gate and the output end of the first inverter are electrically connected with different scanning signal output ends.

6. The shift register of claim 4, further comprising a first cutoff signal input;

the first cut-off signal input end is electrically connected with the third input end of the first NAND gate.

7. The shift register according to claim 1, wherein the light emission control switch module includes a fourth nand gate; the first input end of the fourth NAND gate is electrically connected with the lower-level shift signal output end, the second input end of the fourth NAND gate is electrically connected with the light-emitting control signal input end, and the output end of the fourth NAND gate is electrically connected with the light-emitting control signal output end.

8. The shift register according to claim 7, wherein the light emission control switch module further comprises a second voltage range adjusting unit; a first input end of the second voltage range adjusting unit is electrically connected with the lower-level shift signal output end, a second input end of the second voltage range adjusting unit is electrically connected with the light-emitting control signal input end, and an output end of the fourth nand gate is electrically connected with a third input end of the second voltage range adjusting unit;

the second voltage range adjusting unit is configured to switch the potential output by the fourth nand gate from a fifth potential V5 to a sixth potential V6 and adjust the potential to switch between a seventh potential V7 and an eighth potential V8 in response to the lower shift signal output by the lower shift signal output terminal and the light emission control signal input by the light emission control signal input terminal; wherein | V6-V5| < | V8-V7 |.

9. The shift register according to claim 8, wherein the second voltage range adjusting unit includes a third level shifter, a fourth level shifter, a fifth nand gate, and a second inverter;

the input end of the third level conversion unit is electrically connected with the lower-level shift signal output end, and the output end of the third level conversion unit is electrically connected with the first input end of the fifth nand gate;

the input end of the fourth level conversion unit is electrically connected with the input end of the light-emitting control signal, and the output end of the fourth level conversion unit is electrically connected with the second input end of the fifth nand gate;

the output end of the fourth NAND gate is electrically connected with the first power supply input end of the second inverter;

the output end of the fifth NAND gate is electrically connected with the second power supply input end of the second inverter; the control end of the second phase inverter is grounded, and the output end of the second phase inverter is electrically connected with the light-emitting control signal output end.

10. The shift register of claim 9, further comprising a second off signal input;

and the second cut-off signal input end is electrically connected with the third input end of the fourth NAND gate.

11. The shift register of claim 1, wherein each of the shift register units further comprises at least one first buffer and at least one second buffer; the first buffers correspond to the scanning switch modules one to one; the second buffers correspond to the light-emitting control switch modules one to one;

the first buffer is positioned between the scanning switch module and the scanning signal output end;

the second buffer is located between the light emission control switch module and the light emission control signal output terminal.

12. The shift register of claim 1, wherein the latch module comprises a third inverter, a first tri-state gate, a second tri-state gate, and a nor gate;

the shift register unit further comprises a reset end, and the reset end is used for transmitting a reset signal;

the input end of the third inverter, the first power supply input end of the second tri-state gate and the second power supply input end of the first tri-state gate are respectively and electrically connected with the clock signal input end, and the output end of the third inverter is respectively and electrically connected with the first power supply input end of the first tri-state gate and the second power supply input end of the second tri-state gate;

the input end of the first tri-state gate is electrically connected with the upper-level shift signal input end, and the output end of the first tri-state gate is respectively electrically connected with the output end of the second tri-state gate and the first input end of the NOR gate;

and the second input end of the NOR gate is electrically connected with the reset end, and the output end of the NOR gate is respectively electrically connected with the input end of the second tri-state gate and the lower-stage shift signal output end.

13. A display panel, comprising: a trigger signal line, a first clock signal line, a second clock signal line, at least one scan signal input line, at least one light emission control signal input line, at least one scan line, at least one light emission control signal line, and the shift register according to any one of claims 1 to 12;

the upper shift signal input end of the first shift register unit is electrically connected with the trigger signal wire, and the upper shift signal input end of the next shift register unit is electrically connected with the lower shift signal output end of the previous shift register unit;

the first clock signal line is electrically connected with a first clock signal input end of the odd-numbered stage of the shift register units, and the second clock signal line is electrically connected with a second clock signal input end of the even-numbered stage of the shift register units;

the scanning signal output end of the shift register unit is electrically connected with the scanning line;

and the light-emitting control signal end of the shift register unit is electrically connected with the light-emitting control signal wire.

14. A driving method of a display panel, characterized by being applied to the display panel according to claim 13; the driving method of the display panel includes:

providing a trigger signal to the trigger signal line, a first clock signal to the first clock signal line, and a second clock signal to the second clock signal line, so that the latch module in the first stage to the nth stage of the shift register unit outputs a lower shift signal to an upper shift signal input end of a lower shift register unit and outputs a lower shift signal to the scan switch module and the light emitting control switch module;

and outputting a scan signal transmitted by the scan signal input line through a scan signal output terminal and outputting a light emission control signal transmitted by the light emission control signal input line through a light emission control signal output terminal according to the lower shift signal.

15. A display device characterized by comprising the display panel according to claim 13.

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a shift register, a display panel, a driving method and a display device.

Background

An Organic Light Emitting Diode (OLED) display has the advantages of self-luminescence, low driving voltage, high Light Emitting efficiency, short response time, and flexible display, and is the most promising display currently.

The OLED element of the OLED display panel belongs to a current-driven type element, and a corresponding pixel circuit and a driving circuit are required to be provided, and the driving circuit provides a driving signal for the pixel circuit, so that the pixel circuit provides a driving current for the OLED element to drive the OLED element to emit light. A pixel circuit of an OLED display generally includes a driving transistor, a light emission control transistor, a reset transistor, and the like. The drive circuit includes a light emission control drive circuit and a scan drive circuit. The light-emitting control drive circuit outputs a light-emitting control signal to control the light-emitting control transistor to be turned on or off, and the scanning drive circuit outputs a scanning signal to control the reset transistor to be turned on or off. That is, each signal (light-emitting control signal and scanning signal) needs a set of independent driving circuits, which results in a large area of the non-display region occupied by the driving circuits, and is not favorable for the narrow-frame design of the display.

Disclosure of Invention

The embodiment of the invention provides a shift register, a display panel, a driving method and a display device, which can reduce the area of a non-display area where the shift register is located and meet the requirement of a narrow frame of display equipment.

In a first aspect, an embodiment of the present invention provides a shift register, including:

a plurality of cascaded shift register units; each shift register unit comprises a latch module, at least one scanning switch module and at least one light-emitting control switch module;

each shift register unit further comprises a clock signal input end, a superior shift signal input end, a subordinate shift signal output end, a scanning signal input end, a light-emitting control signal input end, a scanning signal output end and a light-emitting control signal output end;

the latch module is respectively and electrically connected with the clock signal input end, the upper shift signal input end and the lower shift signal output end; the latch module is used for responding to a clock signal input by the clock signal input end, latching a superior shift signal input by the superior shift signal input end and outputting the superior shift signal through the inferior shift signal output end;

the scanning switch module is electrically connected with the scanning signal input end, the scanning signal output end and the lower-level shifting signal output end respectively; the scanning switch module is used for responding to the lower-level shifting signal output by the lower-level shifting signal output end and outputting the scanning signal input by the scanning signal input end through the scanning signal output end;

the light-emitting control switch module is electrically connected with the light-emitting control signal input end, the light-emitting control signal output end and the lower-level shift signal output end respectively; the light-emitting control switch module is used for responding to a lower-level shift signal output by the lower-level shift signal output end and outputting a light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end;

the clock signal input end comprises a first clock signal input end and a second clock signal input end; the latch modules in the odd-numbered shift register units are electrically connected with the first clock signal input end, and the latch modules in the even-numbered shift register units are electrically connected with the second clock signal input end.

In a second aspect, an embodiment of the present invention further provides a display panel, including:

a trigger signal line, a first clock signal line, a second clock signal line, at least one scanning signal input line, at least one light emission control signal input line, at least one scanning line, at least one light emission control signal line, and the shift register according to the first aspect;

the upper shift signal input end of the first shift register unit is electrically connected with the trigger signal wire, and the upper shift signal input end of the next shift register unit is electrically connected with the lower shift signal output end of the previous shift register unit;

the first clock signal line is electrically connected with a first clock signal input end of the odd-numbered stage of the shift register units, and the second clock signal line is electrically connected with a second clock signal input end of the even-numbered stage of the shift register units;

the scanning signal output end of the shift register unit is electrically connected with the scanning line;

and the light-emitting control signal input end of the shift register unit is electrically connected with the light-emitting control signal line.

In a third aspect, an embodiment of the present invention further provides a driving method of a display panel, applied to the display panel of the second aspect:

the driving method of the display panel includes:

providing a trigger signal to the trigger signal line, a first clock signal to the first clock signal line, and a second clock signal to the second clock signal line, so that the latch module in the first stage to the nth stage of the shift register unit outputs a lower shift signal to an upper shift signal input end of a lower shift register unit and outputs a lower shift signal to the scan switch module and the light emitting control switch module;

and outputting a scan signal transmitted by the scan signal input line through a scan signal output terminal and outputting a light emission control signal transmitted by the light emission control signal input line through a light emission control signal output terminal according to the lower shift signal.

In a fourth aspect, an embodiment of the present invention further provides a display device, which includes the display panel according to the second aspect.

The embodiment of the invention completes the transmission of the shift signal by arranging the latch module, and the shift signal can be used as the control signal of the scanning switch module and the light-emitting control switch module. The scanning switch module outputs the scanning signal input by the scanning signal input end through the scanning signal output end according to the control signal; and the light-emitting control switch module outputs the light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end according to the control signal, namely, the switch module (the scanning switch module and the light-emitting control switch module) is used for controlling whether the signal required by the pixel circuit is transmitted to the pixel circuit. Compared with the prior art, the output of the scanning signal and the light-emitting control signal can be completed by arranging one shift register in the embodiment, the structure is simple, and the occupied area is small. Even if the display mode of the display device is different, for example, the display mode is a typical display mode (normal mode), a scrolling mode (Rolling mode), a global display mode (global mode), or the like, the simple structure can be ensured. In addition, the scanning signal output by the scanning signal output end has the same waveform as the scanning signal input by the scanning signal input end, and the light-emitting control signal output by the light-emitting control signal output end has the same waveform as the light-emitting control signal input by the light-emitting control signal input end, so that the input and output signals can be randomly converted and are not controlled by a clock signal any more, namely, the operation is flexible and is not influenced by any additional signal.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of a pixel circuit in the prior art;

FIG. 2 is a schematic diagram of a driving circuit in the prior art;

fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a shift register unit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

FIG. 6 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

fig. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

FIG. 9 is a diagram illustrating a shift register unit according to another embodiment of the present invention;

FIG. 10 is a timing diagram of a shift register unit according to an embodiment of the present invention;

FIG. 11 is a timing diagram of another shift register unit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 13 is a timing diagram of a display panel according to an embodiment of the present invention;

fig. 14 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a pixel circuit in the prior art, and as shown in fig. 1, the pixel circuit includes a data writing transistor M1 ', a light emission control transistor M2 ', a reset transistor M3 ', a driving transistor MD ', and a storage capacitor Cst '. The gate of the data write transistor M1 'is electrically connected to the first SCAN signal terminal SCAN 1', the gate of the emission control transistor M2 'is electrically connected to the emission control signal terminal EMIT', and the gate of the reset transistor M3 'is electrically connected to the second SCAN signal terminal SCAN 2'. The data writing transistor M1 'is turned on or off according to a first SCAN signal inputted from the first SCAN signal terminal SCAN 1', the emission control transistor M2 'is turned on or off according to an emission control signal inputted from the emission control signal terminal EMIT', and the reset transistor M3 'is turned on or off according to a second SCAN signal inputted from the second SCAN signal terminal SCAN 2'. As shown in fig. 2, the first scan signal needs to be configured with a first scan driving circuit 10 ', the second scan signal needs to be configured with a second scan driving circuit 20', and the light-emitting control signal needs to be configured with a light-emitting control driving circuit 30 ', wherein each driving circuit is composed of a plurality of cascaded shift register units, so that the whole driving circuit 100' is heavy and inflexible, occupies a large area of a non-display region, and is not favorable for the narrow frame design of a display.

In order to solve the above problem, an embodiment of the present invention provides a shift register, including: a plurality of cascaded shift register units; each shift register unit comprises a latch module, at least one scanning switch module and at least one light-emitting control switch module; each shift register unit further comprises a clock signal input end, a superior shift signal input end, a subordinate shift signal output end, a scanning signal input end, a light-emitting control signal input end, a scanning signal output end and a light-emitting control signal output end; the latch module is respectively and electrically connected with the clock signal input end, the upper-level shift signal input end and the lower-level shift signal output end; the latch module is used for responding to a clock signal input by the clock signal input end, latching a superior shift signal input by the superior shift signal input end and outputting the superior shift signal through the inferior shift signal output end; the scanning switch module is respectively and electrically connected with the scanning signal input end, the scanning signal output end and the lower-level shifting signal output end; the scanning switch module is used for responding to the lower-level shifting signal output by the lower-level shifting signal output end and outputting the scanning signal input by the scanning signal input end through the scanning signal output end; the light-emitting control switch module is respectively and electrically connected with the light-emitting control signal input end, the light-emitting control signal input end and the lower-level shift signal output end; the light-emitting control switch module is used for responding to the lower-level shift signal output by the lower-level shift signal output end and outputting the light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end; the clock signal input end comprises a first clock signal input end and a second clock signal input end; the latch modules in the odd-level shift register units are electrically connected with the first clock signal input end, and the latch modules in the even-level shift register units are electrically connected with the second clock signal input end.

By adopting the technical scheme, the output of the scanning signal and the light-emitting control signal can be completed through a group of shift registers, the structure is simple, and the occupied area is small. Even if the display mode of the display device is different, for example, the display mode is a typical display mode (normal mode), a scrolling mode (Rolling mode), a global display mode (global mode), or the like, the simple structure can be ensured. In addition, the scanning signal output by the scanning signal output end has the same waveform as the scanning signal input by the scanning signal input end, and the light-emitting control signal output by the light-emitting control signal output end has the same waveform as the light-emitting control signal input by the light-emitting control signal input end, so that the input and output signals can be randomly converted and are not controlled by a clock signal any more, namely, the operation is flexible and is not influenced by any additional signal.

The above is the core idea of the present invention, and based on the embodiments of the present invention, a person skilled in the art can obtain all other embodiments without creative efforts, which belong to the protection scope of the present invention. The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and as shown in fig. 3, the shift register 100 according to the embodiment of the present invention includes: the plurality of cascaded shift register units 10 may include, for example, n shift register units 10, where n is a positive integer, and the n shift register units 10 are arranged in a cascade. Each shift register unit 10 includes a latch module 11, at least one scan switch module 12, and at least one light-emitting control switch module 13, and fig. 3 illustrates an example in which each shift register unit 10 includes two scan switch modules 12 and one light-emitting control switch module 13. The two scan switch modules 12 include a first scan switch module 121 and a second scan switch module 122.

Each shift register cell 10 further includes a clock signal input terminal CLK, an upper shift signal input terminal IN, a lower shift signal output terminal Next, a scan signal input terminal SCANin, a light emission control signal input terminal EMITin, a scan signal output terminal SCANout, and a light emission control signal output terminal EMITout. The clock signal inputs CLK include a first clock signal input CLK1 and a second clock signal input CLK 2. Accordingly, when the two SCAN switch modules 12 include the first SCAN switch module 121 and the second SCAN switch module 122, the SCAN signal output terminal SCANout includes a first SCAN signal output terminal SCAN1out and a second SCAN signal output terminal SCAN2 out. The SCAN signal input terminal SCANin includes a first SCAN signal input terminal SCAN1in and a second SCAN signal input terminal SCAN2 in.

The latch module 11 is electrically connected to the clock signal input terminal CLK, the upper shift signal input terminal IN, and the lower shift signal output terminal Next, respectively. The latch modules 11 in the odd-numbered shift register units 10 are electrically connected to the first clock signal input terminal CLK1, and the latch modules 11 in the even-numbered shift register units 10 are electrically connected to the second clock signal input terminal CLK 2. The latch module 11 is configured to latch an upper shift signal input by an upper shift signal input terminal IN response to a clock signal input by a clock signal input terminal CLK, and output the upper shift signal through a lower shift signal output terminal Next.

For example, when the shift register unit 10 is a first-stage shift register unit, the latch module 11 of the shift register unit 10 latches the start signal STV in response to the clock signal input from the clock signal input terminal CLK1, and outputs the start signal STV through the Next shift signal output terminal Next; correspondingly, when the shift register unit is the second stage shift register unit 10, the latch module 11 latches the Next shift signal output from the latch module 11 of the first stage shift register unit in response to the clock signal input from the clock signal input terminal CLK2, and outputs the Next shift signal through the Next shift signal output terminal Next of the latch module 11; when the shift register unit 10 is a third-stage shift register unit 10, the latch module 11 latches a Next-stage shift signal output by the latch module 11 of the second-stage shift register unit 10 in response to the clock signal input by the clock signal input terminal CLK1, and outputs the Next-stage shift signal through the Next-stage shift signal output terminal Next of the latch module 11; and so on.

The first SCAN switch module 121 is electrically connected to the first SCAN signal input terminal SCAN1in, the first SCAN signal output terminal SCAN1out, and the Next shift signal output terminal Next, respectively; the first SCAN switch module 121 is configured to output the SCAN signal input from the first SCAN signal input terminal SCAN1in through the first SCAN signal output terminal SCAN1out in response to the Next shift signal output from the Next shift signal output terminal Next. That is, the latch module 11 inputs the shift signal into the latch and outputs the shift signal through the Next shift signal output terminal Next. Meanwhile, the shift signal is also used as a control signal of the first SCAN switch module 121 to control the first SCAN switch module 121 to be turned on, so as to output the first SCAN signal required by the pixel circuit input by the first SCAN signal input terminal SCAN1in to the pixel circuit through the first SCAN signal output terminal SCAN1 out. For example, when the pixel circuit is the pixel circuit in fig. 1, the data writing transistor M1' may be controlled to be turned on or off to complete writing of the data signal.

The second SCAN switch module 122 is electrically connected to the second SCAN signal input terminal SCAN2in, the second SCAN signal output terminal SCAN2out, and the Next shift signal output terminal Next, respectively; the second SCAN switch module 122 is configured to output the SCAN signal input from the second SCAN signal input terminal SCAN2in through the second SCAN signal output terminal SCAN1out in response to the Next shift signal output from the Next shift signal output terminal Next. That is, the latch module 11 inputs the shift signal into the latch and outputs the shift signal through the Next shift signal output terminal Next. Meanwhile, the shift signal also serves as a control signal of the second SCAN switch module 122, which controls the second SCAN switch module 122 to be turned on, so as to output the second SCAN signal required by the pixel circuit input by the second SCAN signal input terminal SCAN2in to the pixel circuit through the second SCAN signal output terminal SCAN2 out. For example, when the pixel circuit is the pixel circuit in fig. 1, the reset transistor M3' may be controlled to be turned on or off to complete the resetting of the anode of the light emitting element.

The light emitting control switch module 13 is electrically connected to a light emitting control signal input terminal EMITin, a light emitting control signal output terminal EMITout and a Next shift signal output terminal Next, respectively; the light-emitting control switch module 13 is configured to respond to the Next shift signal output from the Next shift signal output terminal Next, and output the light-emitting control signal input by the light-emitting control signal input terminal EMITin through the light-emitting control signal output terminal EMITout. That is, the shift signal also serves as a control signal for the light-emitting control switch module 13, and controls the light-emitting control switch module 13 to be turned on, so as to output a required light-emitting control signal inputted from the light-emitting control signal input terminal EMITin to the pixel circuit through the light-emitting control signal output terminal EMITout. For example, when the pixel circuit is the pixel circuit in fig. 1, the light emission controlling transistor M2' may be controlled to be turned on or off to flow a driving current into the anode of the light emitting element so that the light emitting element emits light in response to the driving current.

In the embodiment of the present invention, the latch module 11 is arranged to complete the transmission of the shift signal, and the shift signal can be used as the control signal of the scan switch module 12 and the light-emitting control switch module 13. The scan switch module 12 outputs the scan signal inputted from the scan signal input terminal SCANin through the scan signal output terminal SCANout according to the control signal; and the light-emitting control switch module 13 outputs the light-emitting control signal input by the light-emitting control signal input end EMITin through the light-emitting control signal output end EMITout according to the control signal, that is, the switch module is used for controlling whether the signal required by the pixel circuit is transmitted to the pixel circuit. Compared with the prior art, the output of the scanning signal and the light-emitting control signal can be completed by arranging one shift register in the embodiment, the structure is simple, and the occupied area is small. Even if the display mode of the display device is different, for example, the display mode is a typical display mode (normal mode), a scrolling mode (Rolling mode), a global display mode (global mode), or the like, the simple structure can be ensured. In addition, the scan signal output from the scan signal output terminal SCANout has the same waveform as the scan signal input from the scan signal input terminal SCANin, and the emission control signal output from the emission control signal output terminal EMITout has the same waveform as the emission control signal input from the emission control signal input terminal EMITin, so that the input and output signals can be arbitrarily changed without being controlled by a clock signal, that is, the operation is flexible without being affected by any additional signal.

It should be noted that the shift register provided in the present embodiment is a configuration for the pixel circuit in fig. 1, that is, two scanning signals and one light emission control signal are output. However, when the pixel circuit is changed, the number of the scan switch modules and the number of the light emission control switch modules may be set according to the setting of the pixel circuit, and the output of the scan signal and the light emission control signal may be completed.

Optionally, fig. 4 is a schematic structural diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 4, the scan switch module 12 includes a first nand gate 123; the first input end of the first nand gate 123 is electrically connected to the Next shift signal output end Next, the second input end of the first nand gate 123 is electrically connected to the scan signal input end SCANin, and the output end of the first nand gate 123 is electrically connected to the scan signal output end SCANout.

Illustratively, the signal output from the Next shift signal output terminal Next is at a high level, that is, the signal input from the first input terminal of the first nand gate 123 is at a high level, at this time, the first nand gate 123 can realize that when the Next shift signal output terminal Next is at a high level, the signal output from the output terminal of the first nand gate 123 is controlled by the scan signal input from the scan signal input terminal SCANin, that is, when the scan signal input from the second input terminal of the first nand gate 123 is at a high level, the signal output from the output terminal of the first nand gate 123 is a signal (low level) opposite to the scan signal; when the scan signal input to the second input terminal of the first nand gate 123 is at a low level, the signal output from the output terminal of the first nand gate 123 is a signal (at a high level) opposite to the scan signal. Based on this, the signal output from the scan signal output terminal SCANout is opposite in level to the scan signal input from the scan signal input terminal SCANin.

Optionally, with continued reference to fig. 4, each shift register cell 10 further includes a first buffer 14, and the first buffer 14 includes an even number of inverters or an odd number of inverters (not shown in fig. 4). The number of inverters is set in relation to the output of the scanning signal. If the signal output by the scan switch module 12 is low, for example, when the scan switch module 12 includes the first nand gate 123, the signal output by the output terminal of the first nand gate 123 is low. For example, the first buffer 14 including an odd number of inverters may be provided such that the level of the scan signal output from the scan signal output terminal SCANout coincides with the level of the scan signal input from the scan signal input terminal SCANin; and simultaneously, the driving capability of the scanning signal can be increased.

Optionally, with continued reference to fig. 4, the lighting control switch module 13 includes a fourth nand gate 131; a first input terminal of the fourth nand gate 131 is electrically connected to the Next shift signal output terminal Next, a second input terminal of the fourth nand gate 131 is electrically connected to the emission control signal input terminal EMITin, and an output terminal of the fourth nand gate 131 is electrically connected to the emission control signal output terminal EMITout.

Illustratively, the signal output from the Next shift signal output terminal Next is at a high level, that is, the signal input from the first input terminal of the fourth nand gate 131 is at a high level, at this time, the fourth nand gate 131 can realize that when the Next shift signal output terminal Next is at a high level, the signal output from the output terminal of the fourth nand gate 131 is controlled by the emission control signal input from the emission control signal input terminal EMITin, that is, when the scan signal input from the second input terminal of the fourth nand gate 131 is at a high level, the signal output from the output terminal of the fourth nand gate 131 is a signal (low level) with a level opposite to that of the emission control signal. When the scan signal inputted to the second input terminal of the fourth nand gate 131 is at a low level, the signal outputted from the output terminal of the fourth nand gate 131 is a signal (at a high level) opposite to the level of the emission control signal. Accordingly, the signal output from the emission control signal output terminal EMITout is opposite in level to the emission control signal input from the emission control signal input terminal EMITin.

Optionally, with continued reference to fig. 4, each shift register unit 10 further includes a second buffer 15, and the second buffer 15 includes an even number of inverters or an odd number of inverters (not shown in fig. 4). Wherein the number of inverters is set in relation to the output of the light emission control signal. If the signal output from the light-emitting control switch module 13 is at a low level, for example, when the light-emitting control switch module 13 includes the third nand gate 131, the signal output from the output terminal of the third nand gate 131 is at a low level. For example, the second buffer 15 including an odd number of inverters may be provided such that the light emission control signal output from the light emission control signal output terminal EMITout is the same as the light emission control signal input from the light emission control signal input terminal EMITin; and meanwhile, the driving capability of the light-emitting control signal can be increased.

It should be noted that the scan switch module 12 and the light-emitting control switch module 13 include, but are not limited to, nand gates, and those skilled in the art can set the nand gates according to actual situations as long as the scan signals input by the scan signal input terminal can be output after corresponding logic operations are completed. In other alternative embodiments, a nor gate and/or a nor gate, etc. combination may be used.

Optionally, fig. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and as shown in fig. 5, the scan switch module 12 further includes a first voltage range adjusting unit 124; a first input terminal of the first voltage range adjusting unit 124 is electrically connected to the Next shift signal output terminal Next, a second input terminal of the first voltage range adjusting unit 124 is electrically connected to the scan signal input terminal SCANin, and an output terminal of the first nand gate 123 is electrically connected to a third input terminal of the first voltage range adjusting unit 124; the first voltage range adjusting unit 124 is configured to switch the potential output from the first nand gate 123 between the first potential V1 and the second potential V2, and adjust to switch between the third potential V3 and the fourth potential V4, in response to the lower shift signal output from the lower shift signal output terminal Next and the scan signal input from the scan signal input terminal SCANin; wherein | V2-V1| < | V4-V3 |.

Illustratively, 8V devices are used as devices in the scan switch module 12, i.e., the devices have a withstand voltage range of 8V. The voltage range of the signal input from the scan signal input terminal SCANin is, for example, 0-5V. The first potential inputted by the scan signal input terminal SCANin is 0V, and the second potential is 5V. When the signal input by the SCANin input end of the scanning signal is low level, the potential is 0V; when the signal inputted from the scan signal input terminal SCANin is at a high level, the potential thereof is 5V. After passing through the first voltage range adjusting unit 124, the third potential outputted from the first voltage range adjusting unit 124 is-5V, and the fourth potential is 5V. When the signal output by the first voltage range adjusting unit 124 is at a low level, the potential thereof is-5V; when the signal output from the first voltage range adjusting unit 124 is at a high level, the potential thereof is 5V. The first voltage range adjusting unit 124 adjusts the voltage range of the scan signal output from the scan signal output terminal SCANout from 0-5V to-5-5V. Namely, under the condition that the potential range of the input signal is not changed, the voltage range of the scanning signal output by the scanning signal output end SCANout is expanded. Therefore, the pixel circuit can be reset at a lower potential, and the display effect can be improved; and the voltage range of the input signal is unchanged, which is beneficial to maintaining lower circuit power consumption.

Optionally, with continued reference to fig. 5, the first voltage range adjustment unit 124 includes a first level shifter 1241, a second level shifter 1242, a second nand gate 1243 and a first inverter 1244; the input end of the first level shift unit 1241 is electrically connected to the Next shift signal output end Next, and the output end of the first level shift unit 1241 is electrically connected to the first input end of the second nand gate 1243; the input end of the second level shifter 1242 is electrically connected to the scan signal input end SCANin, and the output end of the second level shifter 1242 is electrically connected to the second input end of the second nand gate 1243; the output end of the first nand gate 123 is electrically connected to the first power input end of the first inverter 1244; the output end of the second nand gate 1243 is electrically connected to the second power input end of the first inverter 1243; an input terminal of the first inverter 1244 is grounded, and an output terminal of the first inverter 1244 is electrically connected to the scan signal output terminal SCANout.

Illustratively, the voltage range of the signal output from the Next-stage shifted signal output terminal Next is 0-5V, and the voltage range output from the first level shift unit 1241 is-5-0V. The voltage range of the signal input by the scan signal input terminal SCANin is 0-5V, and the voltage range output by the second level shifter 1242 is-5-0V. When the voltage of the signal output from the output terminal of the first nand gate 123 is 5V, the voltage of the signal output from the first level shifter 1241 is-5V, the voltage of the signal output from the second level shifter 1242 is 0V, and the voltage output from the second nand gate 1243 is 0V. That is, the voltage input to the first power input terminal of the first inverter 1244 is 5V, the voltage input to the second power input terminal of the first inverter 1243 is 0V, and at this time, the signal output from the output terminal of the first inverter 1243 is 5V. When the voltage input to the first power input terminal of the first inverter 1244 is 0V and the voltage input to the second power input terminal of the first inverter 1243 is-5V, the signal output from the output terminal of the first inverter 1243 is-5V. Therefore, the voltage range output by the SCANout of the scanning signal output end is-5-5V.

Optionally, fig. 6 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and as shown in fig. 6, the shift register unit 10 further includes a third nand gate 125; the first input end of the third nand gate 125 and the first input end of the first nand gate 123 are both electrically connected with the Next shift signal output end Next, and the second input end of the third nand gate 125 and the second input end of the first nand gate 123 are both electrically connected with the same scan signal input end SCANin; the output terminal of the third nand gate 125 and the output terminal of the first inverter 1244 are electrically connected to different scan signal output terminals SCANout. The different SCAN signal output terminals SCANout may include, for example, a first SCAN signal output terminal SCAN1out and a second SCAN signal output terminal SCAN2 out; the output terminal of the third nand gate 125 is electrically connected to the second SCAN signal output terminal SCAN2out, and the output terminal of the first inverter 1244 is electrically connected to the first SCAN signal output terminal SCAN1 out. That is, although the first nand gate 123 and the third nand gate 125 are connected to the same SCAN signal input terminal SCANin, different SCAN signals may be output through the first SCAN signal output terminal SCAN1out and the second SCAN signal output terminal SCAN2out, respectively.

Fig. 7 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present invention, and as shown in fig. 6 and 7, the pixel circuit includes a driving transistor MD, a data writing transistor M1, a light emission control transistor M2, an initialization transistor M3, and a storage capacitor C. The gate of the data write transistor M1 is electrically connected to the second SCAN signal terminal SCAN2, the second SCAN signal terminal SCAN2 receives the SCAN signal output from the second SCAN signal output terminal SCAN2out, the gate of the initialization transistor M3 is electrically connected to the first SCAN signal terminal SCAN1, and the first SCAN signal terminal SCAN1 receives the SCAN signal output from the first SCAN signal output terminal SCAN1 out. The gate of the light emitting control transistor M2 is electrically connected to the light emitting control terminal EMIT, which receives the light emitting control signal output from the light emitting control signal output terminal EMIT. In the data writing phase, for example, the data writing transistor M1 may be controlled to be turned on by the SCAN signal output from the second SCAN signal output terminal SCAN2out, and at the same time, the initialization transistor M3 may be controlled to be turned on by the SCAN signal output from the first SCAN signal output terminal SCAN1out (the same waveform as the SCAN signal output from the second SCAN signal output terminal SCAN2out, but wider than the voltage range of the SCAN signal output from the second SCAN signal output terminal SCAN2 out) to write a very low potential to the anode of the light emitting element 22 through the initialization transistor M3, thereby resetting the anode of the light emitting element 22. In the light emitting period, the light emitting control transistor M2 is controlled to be turned on by the light emitting control signal inputted from the light emitting control terminal EMIT, the driving current generated by the driving transistor MD flows into the light emitting element 22, and the light emitting element 22 EMITs light in response to the driving current.

According to the technical scheme of the embodiment, the input scanning signals can be the same scanning signal, but two scanning signals with the same waveform and different voltage ranges can be output to meet different requirements. The scan signal input end SCANin is shared to finish the output of two scan signals, the number of signal lines is reduced, the number of control ends on a chip for driving the shift register is reduced, and the chip cost is saved.

Optionally, with continued reference to fig. 6, the shift register unit 10 further includes a first off signal input SBAR 1; the first off signal input terminal SBAR1 is electrically connected to the third input terminal of the first nand gate 123. Illustratively, the signal input at the first off signal input SBAR1 is 0. The SCAN signal output from the first SCAN signal output terminal SCAN1out is always at a high level. If the pixel circuit is the one shown in fig. 7, the initialization transistor M3 is always turned off, and when the emission control signal output from the emission control signal output terminal EMITout is always high, the transition of the display device from the 4T1C mode to the 2T1C mode can be realized.

In the above embodiment, the scan switch module 12 includes the first voltage range adjusting unit 124 to expand the voltage range of the scan signal output from the scan signal output terminal SCANout, and the light-emitting control switch module 13 can be configured in the same manner to meet the requirement of lower circuit power consumption.

Optionally, fig. 8 is a schematic structural diagram of another shift register unit according to an embodiment of the present invention, and as shown in fig. 8, the light-emitting control switch module 13 further includes a second voltage range adjusting unit 132; a first input end of the second voltage range adjusting unit 132 is electrically connected with the Next shift signal output end Next, a second input end of the second voltage range adjusting unit 132 is electrically connected with the emission control signal input end EMITin, and an output end of the third nand gate 131 is electrically connected with a third input end of the second voltage range adjusting unit 132; the second voltage range adjusting unit 132 is configured to switch the potential output from the third nand gate 131 between a fifth potential V5 and a sixth potential V6, and adjust to switch between a seventh potential V7 and an eighth potential V8, in response to the lower shift signal output from the lower shift signal output terminal Next and the light emission control signal input from the light emission control signal input terminal EMITin; wherein | V6-V5| < | V8-V7 |.

Illustratively, 8V devices are used as the devices in the light emission control switch module 13, that is, the devices have a withstand voltage range of 8V. The voltage range of the signal inputted from the emission control signal input terminal EMITin is, for example, 0 to 5V. The first potential inputted from the emission control signal input terminal EMITin is 0V, and the second potential is 5V. When the signal input by the light-emitting control signal input end EMITIN is at low level, the potential is 0V; when the signal input from the emission control signal input terminal EMITin is at a high level, the potential thereof is 5V. After passing through the second voltage range adjustment unit 132, the third potential outputted from the second voltage range adjustment unit 132 is-5V, and the fourth potential is 5V. When the signal output by the second voltage range adjusting unit 132 is at a low level, the potential thereof is-5V; when the signal output from the second voltage range adjusting unit 132 is high, the potential thereof is 5V. The second voltage range adjusting unit 132 adjusts the voltage range of the light emission control signal output from the light emission control signal output terminal EMITout from 0-5V to-5-5V. That is, the voltage range of the emission control signal output from the emission control signal output terminal EMITout is expanded without changing the potential range of the input signal. Thus, the voltage range of the input signal is unchanged, which is beneficial to maintaining lower circuit power consumption.

Optionally, with continued reference to fig. 8, the second voltage range adjusting unit 132 includes a third level shifter 1321, a fourth level shifter 1322, a fifth nand gate 1323, and a second inverter 1324; the input end of the third level conversion unit 1321 is electrically connected to the Next shift signal output end Next, and the output end of the third level conversion unit 1321 is electrically connected to the first input end of the fifth nand gate 1323; an input end of the fourth level shifter 1322 is electrically connected to the emission control signal input end EMITin, and an output end of the fourth level shifter 1322 is electrically connected to a second input end of the fifth nand gate 1323; the output end of the fourth nand gate 131 is electrically connected to the first power input end of the second inverter 1324; the output end of the fourth nand gate 131 is electrically connected to the second power input end of the second inverter 1324; the control terminal of the second inverter 1324 is grounded, and the output terminal of the second inverter 1324 is electrically connected to the light emission control signal output terminal EMITout.

Illustratively, the voltage range of the signal output from the Next-stage shifted signal output terminal Next is 0-5V, and the voltage range output from the third level shifter 1321 is-5-0V. The voltage range of the signal input from the emission control signal input terminal EMITin is 0-5V, and the voltage range output from the fourth level shifter 1322 is-5-0V. When the voltage of the signal output by the output terminal of the fourth nand gate 131 is 5V, the voltage of the signal output by the third level shifter 1321 is-5V, the voltage of the signal output by the fourth level shifter 1322 is 0V, and the voltage of the signal output by the fifth nand gate 1323 is 0V. That is, the voltage input to the first power input terminal of the second inverter 1324 is 5V, the voltage input to the second power input terminal of the second inverter 1324 is 0V, and at this time, the signal output from the output terminal of the second inverter 1324 is 5V. When the voltage input to the first power input terminal of the second inverter 1324 is 0V and the voltage input to the second power input terminal of the second inverter 1324 is-5V, the signal output from the output terminal of the second inverter 1324 is-5V. Therefore, the voltage range output by the light-emitting control signal output end EMITout is-5-5V.

Optionally, with continued reference to fig. 8, the shift register unit 10 further includes a second off signal input terminal SBAR 2; the second off signal input terminal SBAR2 is electrically connected to the third input terminal of the fourth nand gate 131. Illustratively, the signal input at the first off signal input SBAR2 is 0. The light emission control signal output by the light emission control signal output terminal EMITout is always at a high level; and when the scan signal output from the optical control signal output terminal EMITout is always at a high level. If the pixel circuit is the one shown in fig. 7, the initialization transistor M3 and the emission control transistor M2 are always turned off, and the conversion of the display device from the 4T1C mode to the 2T1C mode can be realized.

On the basis of the foregoing embodiments, optionally, fig. 9 is a schematic structural diagram of another shift register provided in the embodiments of the present invention, and as shown in fig. 9, the latch module 11 includes a third inverter 111, a first tri-state gate 112, a second tri-state gate 113, and a nor gate 114; the shift register unit 10 further includes a reset terminal RST for transmitting a reset signal; the input terminal of the third inverter 111, the first power input terminal of the second tri-state gate 112 and the second power input terminal of the first tri-state gate 112 are electrically connected to the clock signal input terminal CLK, respectively, and the output terminal of the third inverter 111 is electrically connected to the first power input terminal of the first tri-state gate 112 and the second power input terminal of the second tri-state gate 113, respectively; the input end of the first tri-state gate 112 is electrically connected to the upper shift signal input end IN, and the output end of the first tri-state gate 112 is electrically connected to the output end of the second tri-state gate 113 and the first input end of the nor gate 114, respectively; a second input terminal of the nor gate 114 is electrically connected to the reset terminal RST, and output terminals of the nor gate 114 are electrically connected to an input terminal of the second tri-state gate 113 and the Next shift signal output terminal Next, respectively.

It should be noted that fig. 9 only shows an exemplary arrangement of the latch module 11, and the arrangement is not a limitation to the present invention, and those skilled in the art can perform the arrangement according to actual needs.

The working principle of all the structures of the present application will be explained in detail below:

it should be noted that fig. 9 illustrates that the shift register unit 10 includes two scan switch modules 12 and two light-emitting control switch modules 13, where the two scan switch modules 12 include a first scan switch module 121 and a second scan switch module 122, and the first scan switch module 121 and the second scan switch module 122 are connected to a same scan signal input terminal SCANin; the first SCAN switch module 121 is electrically connected to the first SCAN signal output terminal SCAN1out, and the second SCAN switch module 122 is electrically connected to the second SCAN signal output terminal SCAN2out, wherein the first SCAN signal output terminal SCAN1out and the second SCAN signal output terminal SCAN2out output SCAN signals having the same waveform but different voltage ranges. The two light emission control switch modules 13 include a first light emission control switch module 131 and a second light emission control switch module 132. A first input end of the first lighting control switch module 131 is electrically connected to the Next shift signal output end Next, a second input end of the first lighting control switch module 131 is electrically connected to the first lighting control signal input end EMIT1in, and an output end of the first lighting control switch module 131 is electrically connected to the first lighting control signal input end EMIT1 out; a first input terminal of the second light-emission control switch module 132 is electrically connected to the Next shift signal output terminal Next, a second input terminal of the second light-emission control switch module 132 is electrically connected to the second light-emission control signal input terminal EMIT2in, and an output terminal of the second light-emission control switch module 132 is electrically connected to the second light-emission control signal input terminal EMIT2 out.

Fig. 10 is a timing diagram of a shift register according to an embodiment of the present invention, and referring to fig. 9 and 10, between time T1 and time T2, when the upper shift signal is at a high level and the first clock signal is at a low level, the latch module 11 latches the upper shift signal of the previous stage, and continues to output a low level at the Next shift signal output terminal Next.

Between the time T2 and the time T3, when the upper shift signal is at a high level and the first clock signal is at a high level, the third inverter 111 inverts the upper shift signal input at its input terminal and outputs the inverted signal, that is, the signal output at the output terminal of the third inverter 11 is at a low level, passes through the nor gate 114 and outputs a high level, and the Next shift signal output terminal of the lower shift signal outputs a high level and latches the high level.

Between the time T3 and the time T4, when the upper shift signal is at a high level and the first clock signal is at a high level, the second SCAN switch module 122 responds to the high level of the lower shift signal, and transmits the SCAN signal input by the SCAN signal input terminal SCANin to the first buffer 14 (the number of inverters in the first buffer 14 is an odd number) and outputs the SCAN signal through the second SCAN signal output terminal SCAN2 out; meanwhile, the first SCAN switch module 121 adjusts the voltage range of the SCAN signal input from the SCAN signal input terminal SCANin to switch between the third potential V3 and the fourth potential V4, for example, from 0-5V to-5-5V, in response to the high level of the lower shift signal, and outputs through the first SCAN signal output terminal SCAN1 out. Therefore, the pixel circuit can be reset at a lower potential, and the display effect can be improved.

Between the time T4 and the time T5, the first lighting control switch module 131 transmits the first lighting control signal input from the first lighting control signal input terminal EMIT1in to the second buffer 15 in response to the high level of the lower shift signal and outputs the first lighting control signal through the first lighting control signal input terminal EMIT1 out.

Between the time T5 and the time T6, when the upper shift signal is at a low level and the first clock signal is at a low level, the Next shift signal output terminal Next continues to output a high level. The second emission control switch module 132 transmits the second emission control signal inputted from the second emission control signal input terminal EMIT2in to the second buffer 15 in response to the high level of the lower shift signal, and outputs the second emission control signal through the second emission control signal input terminal EMIT2 out.

Therefore, when the upper stage shift signal is at a high level, the clock signal is transmitted to the input circuit to generate a high level signal to control the scan switch module 12 and the emission control switch module 13 to be turned on, and at this time, the scan signal inputted from the scan signal input terminal SCANin is outputted through the scan signal output terminal SCANout and the emission control signal inputted from the emission control signal input terminal EMIT1in is outputted through the emission control signal input terminal EMITout. Compared with the prior art, the output of the scanning signal and the light-emitting control signal can be completed by arranging one shift register in the embodiment, the structure is simple, and the occupied area is small. In addition, the SCAN signal output from the SCAN signal output terminal SCAN1out has the same waveform as the SCAN signal input from the SCAN signal input terminal SCAN1in, and the emission control signal output from the emission control signal output terminal EMITout has the same waveform as the emission control signal input from the emission control signal input terminal EMITin, so that the input and output signals can be arbitrarily changed without being controlled by a clock signal, that is, the operation flexibility is not affected by any additional signal.

Fig. 11 is a timing diagram of another shift register according to the embodiment of the invention, which is different from the timing diagram of fig. 10 in that the first off signal input SBAR1 outputs a 0, and accordingly, the signal output by the second SCAN signal output SCAN2out is high, and other signals are not changed. At this time, the switching of different modes, for example, the switching of the display device from the 4T1C mode to the 2T1C mode, may be realized.

Based on the same inventive concept, the embodiment of the invention also provides a display panel. For the content that is not described in detail in the embodiment of the display panel, reference may be made to the content in each embodiment of the shift register, which is not described herein again. Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and as shown in fig. 12, the display panel according to the embodiment of the present invention includes: a trigger signal line 101, a first clock signal line 102, a second clock signal line 103, at least one scanning signal input line 104, at least one light emission control signal input line 105, at least one scanning line 106, at least one light emission control signal line 107, and the shift register 100 described in the above embodiments; a superior shift signal input terminal IN of the first shift register unit 10 is electrically connected to the trigger signal line 101, and a superior shift signal input terminal IN of the Next shift register unit 10 is electrically connected to a subordinate shift signal output terminal Next of the previous shift register unit 10; the first clock signal line 102 is electrically connected to the first clock signal input terminal CLK1 of the odd shift register unit 10, and the second clock signal line 103 is electrically connected to the second clock signal input terminal CLK2 of the even shift register unit 10; the scan signal output terminal SCANout of the shift register unit 10 is electrically connected to the scan line 106; the emission control signal input terminal EMITin of the shift register unit 10 is electrically connected to the emission control signal line 107.

The latch module is arranged to complete the transmission of the shift signal, and the shift signal can be used as the control signal of the scanning switch module and the light-emitting control switch module. The scanning switch module outputs the scanning signal input by the scanning signal input end through the scanning signal output end according to the control signal; and the light-emitting control switch module outputs the light-emitting control signal input by the light-emitting control signal input end through the light-emitting control signal output end according to the control signal, namely the switch module is used for controlling whether the signal required by the pixel circuit is transmitted to the pixel circuit. Compared with the prior art, the display panel has the advantages that the output of the scanning signals and the light-emitting control signals can be completed by arranging the shift register, the structure is simple, the occupied area is small, and the narrow frame design of the display panel is facilitated. Even if the display mode of the display panel is different, for example, the display mode is a typical display mode (normal mode), a scrolling mode (Rolling mode), a global display mode (global mode), or the like, the configuration can be ensured to be simple. In addition, the scanning signal output by the scanning signal output end has the same waveform as the scanning signal input by the scanning signal input end, and the light-emitting control signal output by the light-emitting control signal output end has the same waveform as the light-emitting control signal input by the light-emitting control signal input end, so that the input and output signals can be randomly changed and are not controlled by a clock signal any more, namely, the operation is flexible and is not influenced by any additional signal, and the display effect of the display panel is favorably improved.

Fig. 13 is a timing diagram of a display panel according to an embodiment of the invention, as shown in fig. 13, each scanning signal is transmitted step by step, and each light-emitting control signal is transmitted step by step.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a display panel, which is applied to the display panel in the above embodiments. Fig. 14 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, and as shown in fig. 14, the driving method of the display panel includes:

s110, providing a trigger signal to the trigger signal line, providing a first clock signal to the first clock signal line, and providing a second clock signal to the second clock signal line, so that the latch module in the first to nth shift register units outputs a lower shift signal to the upper shift signal input terminal of the lower shift register unit and outputs the lower shift signal to the scan switch module and the light emitting control switch module;

and S120, outputting the scanning signal transmitted by the scanning signal input line through the scanning signal output end and outputting the light emitting control signal transmitted by the light emitting control signal input line through the light emitting control signal output end according to the lower-stage shift signal.

In the embodiment, the output of the scanning signal and the light-emitting control signal can be completed by arranging one shift register, so that the structure is simple, the occupied area is small, and the narrow frame design of the display panel is facilitated. Even if the display mode of the display panel is different, for example, the display mode is a typical display mode (normal mode), a scrolling mode (Rolling mode), a global display mode (global mode), or the like, the configuration can be ensured to be simple. In addition, the scanning signal output by the scanning signal output end has the same waveform as the scanning signal input by the scanning signal input end, and the light-emitting control signal output by the light-emitting control signal output end has the same waveform as the light-emitting control signal input by the light-emitting control signal input end, so that the input and output signals can be randomly changed and are not controlled by a clock signal any more, namely, the operation is flexible and is not influenced by any additional signal, and the display effect of the display panel is favorably improved.

Based on the same inventive concept, the embodiment of the invention also provides a display device, and the display device comprises any one of the display panels provided by the above embodiments. Illustratively, as shown in fig. 15, the display device 1000 includes a display panel 1001. Therefore, the display device also has the advantages of the display panel in the above embodiments, and the same points can be understood by referring to the above explanation of the display panel, which is not repeated herein.

The display device 1000 provided in the embodiment of the present invention may be a mobile phone shown in fig. 15, or may be any electronic product with a display function, and for example, the display device 1000 may be an AR (Augmented Reality) display device, a VR (Virtual Reality) display device, a vehicle-mounted display, an intelligent bracelet, an industrial control device, a computer, a television, or other electronic display devices.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.