阅读说明：本技术 一种高速输出的hcsl电平驱动电路 (High-speed output HCSL level driving circuit ) 是由 吕俊盛 田泽 刘颖 邵刚 蔡叶芳 李嘉 于 2020-12-05 设计创作，主要内容包括：本发明涉及一种高速输出的HCSL电平驱动电路。本发明包括PMOS开关管M1和PMOS开关管M2,PMOS开关管M1的源极连接电流源I1,PMOS开关管M2的源极连接电流源I2,PMOS开关管M1的漏极通过负载电阻RL1接地,PMOS开关管M2的漏极通过负载电阻RL2接地,PMOS开关管M1的源极和PMOS开关管M2的源极之间串联有电阻Rs和电容Cs,电阻Rs与电容Cs并联。本发明具有增大电路工作频率,同时提高信号的阻抗匹配效果。(The invention relates to an HCSL level driving circuit with high-speed output. The power supply circuit comprises a PMOS (P-channel metal oxide semiconductor) switching tube M1 and a PMOS switching tube M2, wherein the source electrode of the PMOS switching tube M1 is connected with a current source I1, the source electrode of the PMOS switching tube M2 is connected with a current source I2, the drain electrode of the PMOS switching tube M1 is grounded through a load resistor RL1, the drain electrode of the PMOS switching tube M2 is grounded through a load resistor RL2, a resistor Rs and a capacitor Cs are connected in series between the source electrode of the PMOS switching tube M1 and the source electrode of the PMOS switching tube M2, and the resistor Rs is connected with the capacitor Cs in. The invention has the advantages of increasing the working frequency of the circuit and simultaneously improving the impedance matching effect of signals.)

1. A high-speed output HCSL level driving circuit comprises a PMOS switch tube M1 and a PMOS switch tube M2, wherein the source electrode of the PMOS switch tube M1 is connected with a current source I1, the source electrode of the PMOS switch tube M2 is connected with a current source I2, the drain electrode of the PMOS switch tube M1 is grounded through a load resistor RL1, and the drain electrode of the PMOS switch tube M2 is grounded through a load resistor RL2, and the high-speed output HCSL level driving circuit is characterized in that: a resistor Rs and a capacitor Cs are connected in series between the source electrode of the PMOS switch tube M1 and the source electrode of the PMOS switch tube M2, and the resistor Rs is connected with the capacitor Cs in parallel.

2. A high speed output HCSL level driver circuit according to claim 1, wherein: a PMOS tube M3 is connected in series between the PMOS switch tube M1 and the load resistor RL1, and a PMOS tube M4 is connected in series between the PMOS switch tube M2 and the load resistor RL 2.

3. A high speed output HCSL level driver circuit according to claim 2, wherein: the grid electrodes of the PMOS tube M3 and the PMOS tube M4 are respectively controlled by the on-chip voltage Vctrl.

Technical Field

The invention relates to the field of integrated circuits, in particular to a high-speed output HCSL level driving circuit.

Background

The current HCSL circuit is in a typical drain-end open-circuit mode, a source electrode of a PMOS (P-channel metal oxide semiconductor) tube of a switching tube is connected with a current source, a drain electrode of the switching tube is open-circuit, a signal ground circuit is formed by the PMOS tube and an off-chip ground resistor, and a differential voltage signal is formed on the external ground resistor by inputting a differential signal Inp/n through controlling the PMOS switching current.

The HCSL level is fixed in external 50 omega resistance value and is large in level amplitude, so that the tail current value is large, and the size of a corresponding switch tube is large. The parasitic weight of the switching tube has a large influence on the speed of the level signal; in addition, because the output stage is cascaded with an external circuit through the PAD, the switching tube has a large influence on impedance matching when switching at a high speed, and large reflection can be introduced when high-speed signals are transmitted. Thus, the rate of conventional HCSL output driver circuits does not exceed 250 MHz.

Disclosure of Invention

The present invention provides a high-speed HCSL level driver with a spread spectrum function to solve the above-mentioned technical problems in the background art, and the HCSL level driver has the functions of increasing the operating frequency of the circuit and improving the impedance matching effect of the signal.

The technical solution of the invention is as follows: the invention relates to a high-speed output HCSL level driving circuit, which comprises a PMOS switching tube M1 and a PMOS switching tube M2, wherein the source electrode of the PMOS switching tube M1 is connected with a current source I1, the source electrode of the PMOS switching tube M2 is connected with a current source I2, the drain electrode of the PMOS switching tube M1 is grounded through a load resistor RL1, and the drain electrode of the PMOS switching tube M2 is grounded through a load resistor RL2, and is characterized in that: and a resistor Rs and a capacitor Cs are connected in series between the source electrode of the PMOS switch tube M1 and the source electrode of the PMOS switch tube M2, and the resistor Rs is connected in parallel with the capacitor Cs.

Preferably, a PMOS transistor M3 is connected in series between the PMOS switching transistor M1 and the load resistor RL1, and a PMOS transistor M4 is connected in series between the PMOS switching transistor M2 and the load resistor RL 2.

Preferably, the gates of the PMOS transistor M3 and the PMOS transistor M4 are controlled by the on-chip voltage Vctrl, respectively.

According to the invention, zero is added on the basis of a drain open circuit structure of a traditional HCSL level driving circuit, frequency attenuation caused by channels and parasitics is compensated, namely, a zero mode is introduced through series resistors Rs and series capacitors Cs at sources of a PMOS (P-channel metal oxide semiconductor) transistor M1 and a PMOS transistor M2; meanwhile, the impedance of the output stage is controlled by adding an isolation PMOS transistor M3 and a PMOS transistor M4. The gates of the PMOS transistor M3 and the PMOS transistor M4 are controlled by the voltage Vctrl, and the impedances of the transistor M3 and the transistor M4 are controlled by the voltage, so that the impedance of the whole HCSL output stage is adjusted. By adjusting the impedance, the impedance matching with a channel and a terminal load can be realized, the signal reflection is reduced, and the signal quality is improved. Therefore, the invention has the following advantages:

1) the bandwidth of the drive circuit is increased. The invention is realized by introducing a source electrode series resistor Rs and a capacitor Cs on the basis of the existing HCSL level driving circuit through two differential source electrodes, a zero point is introduced into a circuit transmission function by the resistor Rs and the capacitor Cs, the circuit frequency corresponding to the corresponding frequency can be raised, and the zero point can be placed at a reasonable frequency point by reasonably setting the values of the Rs and the Cs, so that the attenuation effect brought by the spurious response to the frequency response of the whole circuit is counteracted, and the effect of increasing the working frequency of the circuit is achieved.

2) The impedance matching effect is improved. According to the invention, the PMOS tube M3 and the PMOS tube M4 of which the two gates are controlled by the on-chip voltage Vctrl are respectively inserted in series between the PMOS switch tube M1 and the load resistor RL1 and between the PMOS switch tube M2 and the load resistor RL2, and the PMOS tube M3 and the PMOS tube M4 work in a specific working area under the control of the Vctrl, so that the impedance of the PMOS tube M3 or the PMOS tube M4 and the PMOS switch tube M1 or the PMOS switch tube M2 which are connected in series is kept unchanged and is not influenced by the high-speed switching of the switch tubes, and the signal reflection is reduced.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, the structure of the embodiment of the present invention includes a PMOS switch tube M1, a PMOS switch tube M2, a PMOS tube M3, and a PMOS tube M4, wherein a source of the PMOS switch tube M1 is connected to a current source I1, a source of the PMOS switch tube M2 is connected to a current source I2, a drain of the PMOS switch tube M1 is connected to a source of a PMOS tube M3, a drain of the PMOS switch tube M3 is grounded through a load resistor RL1, a drain of the PMOS switch tube M2 is connected to a source of a PMOS tube M4, a drain of the PMOS tube M4 is grounded through a load resistor RL2, a resistor Rs and a capacitor Cs are connected in series between the source of the PMOS switch tube M1 and the source of the PMOS switch tube M2, the resistor Rs is connected in parallel to the capacitor Cs, and gates of the PMOS tube M3 and the PMOS tube M4 are respectively controlled.

When the circuit is applied specifically, a differential signal Inp/n is input to control the on and off of a PMOS tube M1/M2, the sources of the PMOS tube M1 and M2 are connected with a current source I1 and a current source I2, meanwhile, a source series resistor Rs and a capacitor Cs are introduced into the two differential sources, a zero point is introduced into a circuit transmission function by the resistor Rs and the capacitor Cs, the circuit frequency under the corresponding frequency can be raised, the zero point can be placed at a reasonable frequency point by reasonably setting the values of the Rs and the Cs, the attenuation effect of the parasitic effect on the frequency response of the whole circuit is counteracted, and the effect of increasing the working frequency of the circuit is achieved.

The PMOS tube M3 and the PMOS tube M4, of which the grid electrodes are controlled by the on-chip voltage Vctrl, are respectively inserted between the PMOS switch tube M1 and the load resistor RL1 and between the PMOS switch tube M2 and the load resistor RL2 in series, so that the PMOS tube M3 and the PMOS tube M4 work in a specific working area, the impedance of the PMOS tube M3 or the PMOS tube M4 and the PMOS switch tube M1 or the PMOS switch tube M2 which are connected in series is kept unchanged and is not influenced by high-speed switching of the switch tubes, and signal reflection is reduced.

By implementing the technical scheme, the working frequency of the HCSL level driver can be further improved, and through simulation tests, the highest working frequency of the HCSL level driver circuit realized by the invention can reach 400 MHz.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.