阅读说明：本技术 一种用于安全芯片测试模式的保护装置及方法 (Protection device and method for security chip test mode ) 是由 张奇惠 董文强 刘曼 于 2020-12-31 设计创作，主要内容包括：本发明公开了一种用于安全芯片测试模式的保护装置及方法,涉及芯片安全防护技术领域；该装置包括简单保护模块、对称保护模块、软保护模块和分布保护模块,其中简单保护模块用于生成测试模式进入的使能信号EN0,对称保护模块用于生成测试模式进入的使能信号EN1,软保护模块用于生成测试模式进入的使能信号EN2,分布保护模块用于使用EN0、EN1和EN2根据分布保护策略对测试模式的进入过程进行分布式保护。本发明中提供的装置提供了三重保护以实现在芯片已经完成CP测试后有效防御攻击者重新进入测试模式,同时在不破坏芯片的情况下,不能逆向追踪三个使能信号的分布布线结构,从而进一步提高芯片的安全性。(The invention discloses a protection device and a method for a security chip test mode, relating to the technical field of chip security protection; the device comprises a simple protection module, a symmetrical protection module, a soft protection module and a distributed protection module, wherein the simple protection module is used for generating an enable signal EN0 for entering a test mode, the symmetrical protection module is used for generating an enable signal EN1 for entering the test mode, the soft protection module is used for generating an enable signal EN2 for entering the test mode, and the distributed protection module is used for carrying out distributed protection on the entering process of the test mode by using EN0, EN1 and EN2 according to a distributed protection strategy. The device provided by the invention provides triple protection to effectively defend an attacker from reentering a test mode after the chip has finished CP test, and meanwhile, the distributed wiring structure of three enabling signals cannot be traced reversely under the condition of not damaging the chip, so that the safety of the chip is further improved.)

1. A protection device for a test mode of a security chip is characterized by comprising a simple protection module, a symmetrical protection module, a soft protection module and a distributed protection module, wherein the simple protection module, the symmetrical protection module and the soft protection module are respectively connected with the distributed protection module, and the simple protection module is used for generating an enable signal EN0 for entering a test mode; the symmetric protection module is used for receiving a random number RN and generating an enable signal EN1 for test mode entry based on the RN; the soft protection module is used for receiving an output MO of the memory and generating an enable signal EN2 for entering the test mode based on the MO; the distributed protection module is used for receiving enable signals EN0, EN1 and EN2, and simultaneously generating enable signals TMENn entering various test modes based on the enable signals EN0, EN1 and EN2 according to a specific distributed protection strategy, so that the test modes of the security chip are protected in a distributed mode.

2. The protection device for the test mode of the security chip according to claim 1, wherein the simple protection module comprises an up-pull module, a scribe line module 0, a down-pull module 0 and a buffer module, the up-pull module, the down-pull module 0 and the scribe line module 0 are respectively connected to the buffer module, the up-pull module is used for up-pulling to a high voltage of a kernel, the scribe line module 0 is used for routing in the scribe line, the down-pull module 0 is used for down-pulling to a low voltage of the kernel, and the buffer module is used for enhancing the driving capability of the output of the down-pull module 0 and the output of the scribe line module 0, and outputting an enable signal EN 0.

3. The protection device for the test mode of the security chip as claimed in claim 1, wherein the symmetric protection module comprises a sampling module, a main chip module, a scribe line module 1, a pull-down module 1, an exclusive nor module and a detection module, the sampling module is respectively connected to the main chip module and the scribe line module 1, an input end of the exclusive nor module is respectively connected to output ends of the main chip module and the scribe line module 1, and the exclusive nor module is respectively connected to an output end of the pull-down module and an input end of the detection module.

4. The protection device for the test mode of the secure chip according to claim 3, wherein the sampling module receives a random number RN as an input, while generating control/data signals common to the main chip module and the scribe lane module 1, the main chip module is used for the symmetrical copy of the scribing slot module 1 in the main chip, the scribing slot module 1 is used for the symmetrical copy of the main chip module in the scribing slot, the pull-down module 1 is used for pulling down to the kernel weak low voltage, the exclusive nor module is used for performing exclusive nor logic on the output signal of the main chip module and the output signal of the scribing slot module 1 and outputting the result to the detection module, the detection module is used for detecting the output state of the exclusive OR module, judging and outputting an enable signal EN1 according to the judgment result.

5. The apparatus according to claim 1, wherein the soft protection module includes a decryption module for decrypting the input specific stored data MO, and a comparison module for comparing an output of the decryption module with a specific constant and outputting an enable signal EN2 according to a comparison result.

6. The protection device for the test mode of the secure chip according to claim 1, wherein the distributed protection module comprises a plurality of and gates for performing and logic of the distributed protection strategy on the received enable signals EN0, EN1 and EN2, and generating the enable signal TMENn, n-0, 1,2 … entering each test sub-mode according to the and logic result.

7. A protection method for a secure chip test mode, which is implemented by using the protection device for a secure chip test mode of any one of claims 1 to 6, comprising the following steps:

s1, the simple protection module, the symmetrical protection module and the soft protection module respectively generate enable signals EN0, EN1 and EN2 and send the generated enable signals to the distributed protection module;

s2, the distribution protection module generates an entry enable signal TMENn, n is 0,1,2 … for each sub-module test according to a specific distribution protection strategy;

s3, it is judged whether or not the test sub-modes can be entered based on the generated enable signal TMENn.

8. The method for protecting the test mode of the secure chip according to claim 7, wherein the step S1 specifically includes:

s11, determining whether the scribe line module 0 and the scribe line module 1 in the simple protection module and the symmetrical protection module are broken, if so, outputting an enable signal EN 0-1 and EN 1-1, otherwise, outputting an enable signal EN 0-0 and EN 1-0;

s12, determining whether the value stored in the chip memory is equal to a preset value, if so, outputting an enable signal EN2 is 1, otherwise, outputting an enable signal EN2 is 0;

and S13, transmitting all the generated enabling signals to the distribution protection module.

9. The method for protecting test mode of security chip according to claim 7, wherein the distributed protection policy in step S2 specifically includes:

A. the 3-input AND gate in the distributed protection module takes EN0, EN1 and EN2 as inputs, and outputs TMEN 0-EN 0& EN1& EN2 to judge whether a Flash test mode can be entered;

B. a 2-input AND gate in the distributed protection module takes EN0 and EN1 as inputs, and outputs TMEN 1-EN 0& EN1 to judge whether a DFT test mode can be entered;

C. a 2-input and gate in the distributed protection module takes EN0 and EN2 as inputs, and outputs TMEN 2-EN 0& EN2 to determine whether a functional test mode can be entered.

10. The method for protecting the test mode of the security chip of claim 9, wherein when any one of the enable signals EN0, EN1 and EN2 outputs a logic "0", the logic of the input and gate output inputted by the enable signal is 0.

Technical Field

The invention relates to the technical field of chip safety protection, in particular to a protection device and a protection method for a safety chip test mode.

Background

Since defects introduced during the manufacturing process may cause the functions or performances of the analog I P or the memory or the digital logic to fail to meet the specification requirements defined by the chip, CP test and FT test are required before the production of the chip. After the chip CP is tested and the package is debugged, the chip cannot re-enter the test mode because the values of the chip memory and registers, which may contain critical information such as factory code, programs and keys of the chip, are obtained through the test mode.

The non-secure chip may enter the test mode of the chip only by inputting a certain test sequence from the external port, and if the chip CP test is performed without taking a certain measure to perform the scratch-reduction packaging directly, an attacker may enter the test mode of the chip by applying the same test sequence, thereby easily obtaining the key information of the chip.

It is therefore necessary to provide a protection module for the test mode in the security chip.

Disclosure of Invention

The present invention is directed to a protection device and method for a test mode of a security chip, so as to solve the foregoing problems in the prior art.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a protection apparatus for a test mode of a security chip, the protection apparatus comprising a simple protection module, a symmetric protection module, a soft protection module, and a distributed protection module, the simple protection module, the symmetric protection module, and the soft protection module being respectively connected to the distributed protection module, wherein the simple protection module is configured to generate an enable signal EN0 for test mode entry, the symmetric protection module is configured to receive a random number RN and generate an enable signal EN1 for test mode entry based on the RN, the soft protection module is configured to receive an output MO of a memory and generate an enable signal EN2 for test mode entry based on the MO, the distributed protection module is configured to receive enable signals EN0, EN1, and EN2, while generating an enable signal TMENn for entry into each test mode based on the enable signals EN0, EN1, and EN2 according to a specific distributed protection strategy, thereby performing distributed protection on the security chip.

Preferably, simple protection module includes pull-up module, scribing slot module 0, pull-down module 0 and buffer module, pull-up module pull-down module 0 with scribing slot module 0 respectively with buffer module links to each other, simultaneously pull-up module is used for pulling up to the kernel high pressure, scribing slot module 0 is arranged in the scribing slot to walk the line, pull-down module 0 is arranged in the interior weak low pressure of pull-down to the kernel, buffer module is used for the reinforcing pull-down module 0 output with the driving force of scribing slot module 0 output, output enable signal EN 0.

Preferably, the symmetrical protection module comprises a sampling module, a main chip module, a scribing slot module 1, a pull-down module 1, an exclusive nor module and a detection module, wherein the sampling module is respectively connected with the main chip module and the scribing slot module 1, the input end of the exclusive nor module is respectively connected with the main chip module and the output end of the scribing slot module 1, and the exclusive nor module is connected with the output end of the pull-down module and the input end of the detection module.

Preferably, the sampling module receives a random number RN as an input, and is configured to generate a control/data signal shared by the master chip module and the scribe lane module 1, where the master chip module is configured to symmetrically copy the scribe lane module 1 in the master chip, the scribe lane module 1 is configured to symmetrically copy the master chip module in the scribe lane, the pull-down module 1 is configured to pull down to a weak low voltage in the core, the exclusive nor module is configured to perform exclusive nor logic on an output signal of the master chip module and an output signal of the scribe lane module 1 and output a result to the detection module, and the detection module is configured to detect an output state of the exclusive nor module and determine the output state, and output an enable signal EN1 according to a determination result.

Preferably, the soft protection module includes a decryption module and a comparison module, the decryption module is configured to decrypt the input specific storage data MO, and the comparison module is configured to compare the output of the decryption module with a specific constant, and output an enable signal EN2 according to a comparison result.

Preferably, the distributed protection module includes a plurality of and gates for performing and logic of the distributed protection strategy on the received enable signals EN0, EN1 and EN2, and generating an enable signal TMENn, n ═ 0,1,2 … into each test sub-mode according to a result of the and logic.

Preferably, the plurality of and gates comprise a 3-input and gate and a plurality of 2-input and gates, the 3-input and gate is used for receiving three input enable signals of EN0, EN1 and EN2, and the 2-input and gate is used for receiving any two input enable signals of EN0, EN1 and EN 2.

Another object of the present invention is to provide a test mode protection method for a security chip, comprising the steps of:

s1, the simple protection module, the symmetrical protection module and the soft protection module respectively generate enable signals EN0, EN1 and EN2 and send the generated enable signals to the distributed protection module;

s2, the distribution protection module generating an entry enable signal TMENn, n is 0,1,2 … for testing each sub-module according to a specific distribution protection strategy;

and S3, judging whether the test sub-mode can be entered according to the generated enabling signal.

Preferably, step S1 specifically includes:

s11, determining whether the scribe line module 0 and the scribe line module 1 in the simple protection module and the symmetrical protection module are broken, if so, outputting an enable signal EN 0-1 and EN 1-1, otherwise, outputting an enable signal EN 0-0 and EN 1-0;

s12, determining whether the value stored in the chip memory is equal to a preset value, if so, outputting an enable signal EN2 is 1, otherwise, outputting an enable signal EN2 is 0;

and S13, transmitting all the generated enabling signals to the distribution protection module.

Preferably, the distributed protection policy in step S2 specifically includes:

A. the 3-input AND gate in the distributed protection module takes EN0, EN1 and EN2 as inputs, and outputs TMEN 0-EN 0& EN1& EN2 to judge whether a Flash test mode can be entered;

B. a 2-input AND gate in the distributed protection module takes EN0 and EN1 as inputs, and outputs TMEN 1-EN 0& EN1 to judge whether a DFT test mode can be entered;

C. a 2-input and gate in the distributed protection module takes EN0 and EN2 as inputs, and outputs TMEN 2-EN 0& EN2 to determine whether a functional test mode can be entered.

Preferably, when any one of the enable signals EN0, EN1 and EN2 outputs a logic "0", the input and gate that is inputted by the enable signal outputs a logic 0.

The invention has the beneficial effects that:

the invention discloses a protection device and a method for a test mode of a security chip, and the device comprises a simple protection module, a symmetrical protection module, a soft protection module and a distributed protection module, wherein the simple protection module is used for generating an enable signal EN0 for entering the test mode, the symmetrical protection module is used for generating an enable signal EN1 for entering the test mode, the soft protection module is used for generating an enable signal EN2 for entering the test mode, and the distributed protection module is used for carrying out distributed protection on the entering process of the test mode according to a distributed protection strategy by using EN0, EN1 and EN 2. The device provided by the invention can effectively defend an attacker from reentering a test mode after the chip has finished CP test, and meanwhile, the distributed wiring structure of the three enabling signals cannot be traced reversely under the condition of not damaging the chip, so that the safety of the chip is further improved.

Drawings

Fig. 1 is a schematic diagram of the overall structure of a protection device for a secure chip test mode provided in embodiment 1;

fig. 2 is a schematic structural view of a simple protection module provided in embodiment 1;

fig. 3 is a schematic structural view of a symmetric protection module provided in embodiment 1;

fig. 4 is a schematic structural diagram of a soft protection module provided in embodiment 1;

fig. 5 is a schematic structural view of the distributed protection module provided in embodiment 1;

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Example 1

The present embodiment provides a protection apparatus for a test mode of a security chip, as shown in fig. 1, which includes a test mode protection apparatus of a security chip, and is characterized in that the protection apparatus includes a simple protection module, a symmetric protection module, a soft protection module and a distributed protection module, the simple protection module, the symmetric protection module and the soft protection module are respectively connected to the distributed protection module, wherein the simple protection module is configured to generate an enable signal EN0 for test mode entry, the symmetric protection module is configured to receive a random number RN and generate an enable signal EN1 for test mode entry, the soft protection module is configured to receive an output MO of a memory and generate an enable signal EN2 for test mode entry based on the MO, the distributed protection module is configured to receive enable signals EN0, EN1 and EN2, and simultaneously generate an enable signal EN0, EN2 based on a specific distributed protection strategy, EN1 and EN2 generate enable signals TMENn to enter respective test modes, thereby performing distributed protection on the security chip.

In this embodiment, the simple protection module includes an upward-pulling module, a scribing slot module 0, a downward-pulling module 0, and a buffer module, as shown in fig. 2, the upward-pulling module, the downward-pulling module 0, and the scribing slot module 0 are respectively connected to the buffer module, and the upward-pulling module is configured to pull up an input end of the buffer module to a high voltage of the kernel, the scribing slot module 0 is configured to route wires in the scribing slot, the downward-pulling module 0 is configured to pull down an input end of the buffer module to a weak low voltage of the kernel (e.g., 0.2V) (logic "weak 0"), and the buffer module is configured to enhance a driving capability of the downward-pulling module 0 and an output of the scribing slot module 0, and output an enable signal EN 0.

During specific work, the working principle of the simple protection module is as follows: the input in the module is self-generated by the pull-up module, namely the output end of the pull-up module is pulled up to the high voltage of the kernel so as to output fixed high voltage, the logic is '1', the output fixed high voltage is buffered by the buffer module and then is connected to the outside scribing slot module 0, the scribing slot module 0 is only a connecting line made of POLY materials, namely the scribing slot module 0 only directly connects the high voltage (logic '1') output by the buffer module, and the pull-down module 0 generates weak low voltage (logic 'weak 0'). Before the CP test is completed, POLY in the scribe line module 0 is not scribed, the buffer module input represents a high voltage (logic "1"), and the enable signal EN0 output after being buffered by the buffer module is equal to 1; after the CP test is completed, POLY in the scribe line module 0 is already scribed, the buffer module input is represented by a weak low voltage (logic "weak 0") of the pull-down module input, and the enable signal EN0 buffered by the buffer module is equal to 0.

The symmetrical protection module in this embodiment is shown in fig. 3, and includes a sampling module, a main chip module, a scribe line module 1, a pull-down module 1, an exclusive nor module, and a detection module, where the sampling module is connected to the main chip module and the scribe line module 1, an input end of the exclusive nor module is connected to an output end of the main chip module and an output end of the scribe line module 1, and the exclusive nor module is connected to an output end of the pull-down module and an input end of the detection module.

The sampling module receives a random number RN as an input and is used for generating a control/data signal shared by the main chip module and the scribing slot module 1, the main chip module is used for symmetrically copying the scribing slot module 1 in a main chip, the scribing slot module 1 is used for symmetrically copying the main chip module in a scribing slot, the pull-down module 1 is used for pulling down to an inner core weak low voltage, the exclusive OR module is used for carrying out exclusive OR logic on an output signal of the main chip module and an output signal of the scribing slot module 1 and outputting a result to the detection module, and the detection module is used for detecting an output state of the exclusive OR module and judging and outputting an enable signal EN1 according to a judgment result.

In operation, the input of the symmetric protection module is a random number RN, which may be a random number generated by a true random number generator to increase the security of the chip. The RN generates a control/data signal after passing through the sampling module and outputs the control/data signal to a main chip module and a scribing slot module 1 which have the same logic and wiring respectively, the exclusive OR module adopts a 2-input exclusive OR gate, one end of the exclusive OR gate is connected to the output of the main chip module, the other end of the exclusive OR gate is connected to the output of the scribing slot module 1, and the exclusive OR module is simultaneously connected to the output end of the pull-down module 1. Before the CP test is completed, the scribe lane module 1 is not scribed, at this time, the output of the main chip module is completely the same as the output of the scribe lane module 1, the exclusive nor module outputs a constant high voltage (logic "1"), and the detection module makes EN1 equal to 1; after the CP test is completed, the scribe lane module 1 is scribed, the output of the main chip module is the random number RN sampled by the sampling module and then output, the output of the scribe lane module 1 is the weak low voltage (logic "weak 0") generated by the pull-down module 1, at this time, the output of the exclusive or gate is sometimes logic "1", sometimes logic "0", rather than the constant logic "1", and this condition is detected by the detection module, so that the output enable signal EN1 is 0. The speed of changing to logic "1" and "0" is combined with the design, and particularly, according to the frequency of the input random number RN, if the frequency of RN is high, the change of "1" is fast when "0" is needed, otherwise, the change is slow.

In this embodiment, the structure of the soft protection module is as shown in fig. 4, and mainly includes a decryption module and a comparison module, where the decryption module is configured to decrypt input specific stored data MO, and the comparison module is configured to compare an output of the decryption module with a specific constant, and output an enable signal EN2 according to a comparison result.

It should be noted that the specific constant in the present embodiment may be a fixed value of 8 bits or 32 bits, such as 8 'b 00111001 and 32' b 01010101101010100101010101010101010101010101010, or may be other fixed values of other bits.

In operation, the input to the soft protection module is the output MO of the memory, which is encrypted by the algorithm and written to the memory before the CP test. During testing, the MO performs a decryption process through a decryption module corresponding to the encryption algorithm, and then compares the MO with the comparison module. Before the CP test is completed, since the value stored in the MO is a fixed preset value, comparing the MO value and the preset value to be equal, the output enable signal EN2 is 1; after the CP test is completed, the value stored in the MO has been changed to a non-preset value, and the MO value is not equal to the preset value after being compared with the preset value, the output enable signal EN2 is 0.

For the distributed protection module, as shown in fig. 5, a plurality of and gates are included, and the and gates are used for performing and logic of the distributed protection strategy on the received enable signals EN0, EN1 and EN2, and generating enable signals TMENn, n-0, 1,2 … for entering of each test sub-mode according to the and logic result.

As a preferable mode, the distributed protection module in this embodiment employs a 3-input and gate and a plurality of 2-input and gates, inputs of the 3-input and gate are EN0, EN1, and EN2, and inputs of the 2-input and gate may be any two of EN0, EN1, and EN2, specifically including but not limited to the following enable signals for test mode entry:

the 3-input AND gate in the distributed protection module takes EN0, EN1 and EN2 as inputs, and outputs TMEN 0-EN 0& EN1& EN2 to judge whether a Flash test mode can be entered;

a 2-input AND gate in the distributed protection module takes EN0 and EN1 as inputs, and outputs TMEN 1-EN 0& EN1 to judge whether a DFT test mode can be entered;

a 2-input AND gate in the distributed protection module takes EN0 and EN2 as inputs, and outputs TMEN 2-EN 0& EN2 to judge whether a function test mode can be entered;

the input and gate output logic can also be adopted according to actual needs to judge whether the enable signals entering functional test sub-modules such as an RAMBIST test mode, a BGR test mode, a VR test mode, a POR test mode, an OSC test mode and the like are generated.

When any one of the enable signals EN0, EN1, and EN2 outputs logic "0", the input and gate that is inputted by the enable signal outputs logic 0. In order to make the security chip more secure, the protection device provided in this embodiment includes three modules, which is equivalent to triple insurance, even if an attacker reconnects the "scribe lane module 0" in the broken simple protection module, another symmetrical protection module and a soft protection module can continuously protect the chip; an attacker can reenter the test mode only by cracking/reconnecting/restoring the scribing slot module 0, the scribing slot module 1 and the soft protection preset storage value at the same time, obviously the difficulty is far greater than that of the protection of a specific test mode, the difficulty of entering the test mode by the attacker is greatly improved, and the safety performance of the chip is improved.

Example 2

The embodiment provides a protection method for a test mode of a secure chip, which adopts the protection device for the test mode of the secure chip described in embodiment 1, and comprises the following steps:

s1, the simple protection module, the symmetrical protection module and the soft protection module respectively generate enable signals EN0, EN1 and EN2 and send the generated enable signals to the distributed protection module;

s11, determining whether the scribe line module 0 and the scribe line module 1 in the simple protection module and the symmetrical protection module are broken, if so, outputting an enable signal EN 0-1 and EN 1-1, otherwise, outputting an enable signal EN 0-0 and EN 1-0;

s12, determining whether the value stored in the chip memory is equal to a preset value, if so, outputting an enable signal EN2 is 1, otherwise, outputting an enable signal EN2 is 0;

and S13, transmitting all the generated enabling signals to the distribution protection module.

S2, the distribution protection module generating an entry enable signal TMENn, n is 0,1,2 … for testing each sub-module according to a specific distribution protection strategy;

A. the 3-input AND gate in the distributed protection module takes EN0, EN1 and EN2 as inputs, and outputs TMEN 0-EN 0& EN1& EN2 to judge whether a Flash test mode can be entered;

B. a 2-input AND gate in the distributed protection module takes EN0 and EN1 as inputs, and outputs TMEN 1-EN 0& EN1 to judge whether a DFT test mode can be entered;

C. a 2-input and gate in the distributed protection module takes EN0 and EN2 as inputs, and outputs TMEN 2-EN 0& EN2 to determine whether a functional test mode can be entered.

When any one of the enable signals EN0, EN1, and EN2 outputs logic "0", the input and gate that is inputted by the enable signal outputs logic 0.

S3, judging whether a test sub-mode can be entered or not according to the generated enabling signal, and forbidding to enter the test sub-mode when TMENn output logic is '0'; when TMENn output logic is "1", then entry into the test sub-mode is allowed.

In fact, after the CP test is completed, all three enable signals EN0, EN1 and EN2 should be logic "0", so that TMENn is 0, that is, it is impossible to enter any test sub-mode, and it is not easy to trace back the distribution wiring of the three enable signals without destroying the chip, so the distributed protection module further improves the security of the chip.

By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:

the invention discloses a protection device and a method for a test mode of a security chip, and the device comprises a simple protection module, a symmetrical protection module, a soft protection module and a distributed protection module, wherein the simple protection module is used for generating an enable signal EN0 for entering the test mode, the symmetrical protection module is used for generating an enable signal EN1 for entering the test mode, the soft protection module is used for generating an enable signal EN2 for entering the test mode, and the distributed protection module is used for carrying out distributed protection on the entering process of the test mode according to a distributed protection strategy by using EN0, EN1 and EN 2. The device provided by the invention can effectively defend an attacker from reentering a test mode after the chip has finished CP test, and meanwhile, the distributed wiring structure of the three enabling signals cannot be traced reversely under the condition of not damaging the chip, so that the safety of the chip is further improved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.