阅读说明：本技术 一种隔离驱动电路的接收电路 (Receiving circuit of isolation driving circuit ) 是由 郝炳贤 王云 郑鲲鲲 王飞 薛静 杨娜 任广辉 严文瑞 马玫娟 于 2020-12-10 设计创作，主要内容包括：本申请提供一种隔离驱动电路的接收电路,包括：差分对输入模块,用于接收共模输入电压信号,并抑制共模输入电压信号的噪声；电流产生和镜像电路,用于接收第一使能信号,并在第一使能信号开启时,产生四路电流偏置；共模反馈电路的输入端和输出端连接电流产生和镜像电路的两路电流偏置,用于提高环路共模增益,稳定差分对输入模块输出的共模信号；预放大电路的两个输入端连接两路电流偏置,用于对差分对输入模块输出的共模信号进行放大,提高电路的带宽；比较电路的两个输入端分别连接预放大电路的两个输出端,用于接收预放大电路输出的差模信号,并比较后输出比较结果；低通滤波电路,用于接收比较结果,并进行低通滤波后输出,作为接收信号。(The application provides a receiving circuit of isolation drive circuit, includes: the differential pair input module is used for receiving the common mode input voltage signal and inhibiting the noise of the common mode input voltage signal; the current generation and mirror image circuit is used for receiving a first enable signal and generating four paths of current bias when the first enable signal is started; the input end and the output end of the common mode feedback circuit are connected with the current generation circuit and the two paths of current bias of the mirror image circuit and are used for improving the common mode gain of the loop and stabilizing the common mode signal output by the differential pair input module; two input ends of the pre-amplifying circuit are connected with two paths of current biases and used for amplifying common-mode signals output by the differential pair input module, and the bandwidth of the circuit is improved; two input ends of the comparison circuit are respectively connected with two output ends of the pre-amplification circuit and used for receiving the differential mode signals output by the pre-amplification circuit and outputting comparison results after comparison; and the low-pass filter circuit is used for receiving the comparison result, performing low-pass filtering and outputting the comparison result as a received signal.)

1. A receive circuit for isolating a driver circuit, comprising:

a differential pair input module (6) for receiving a common mode input voltage signal and suppressing noise of the common mode input voltage signal;

the current generation and mirror circuit (1) is used for receiving a first enable signal (CMD _ P) and generating four-way current bias when the first enable signal (CMD _ P) is turned on;

the input end and the output end of the common mode feedback circuit (2) are connected with the current generation and two-way current bias of the mirror circuit (1) and are used for improving the loop common mode gain and stabilizing the common mode signal output by the differential pair input module;

two input ends of the pre-amplification circuit (3) are connected with the two paths of current biases and used for amplifying the common-mode signal output by the differential pair input module (6) and improving the bandwidth of the circuit;

two input ends of the comparison circuit (4) are respectively connected with two output ends of the pre-amplification circuit (3), and the comparison circuit (4) is used for receiving the differential mode signal output by the pre-amplification circuit (3) and outputting a comparison result after comparison;

and the low-pass filter circuit (5) is used for receiving the comparison result of the comparison circuit, performing low-pass filtering and outputting the result as a received signal (OUT).

2. The receiving circuit of an isolated driver circuit according to claim 1, wherein the differential pair input module (6) comprises:

the circuit comprises a first transistor (MN1), a second transistor (MN2), a third transistor (MN3), a fourth transistor (MN4), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a first resistor (R1) and a second resistor (R2);

wherein a control terminal of the first transistor (MN1) is connected to a control terminal of the third transistor (MN 3);

a first terminal of the first transistor (MN1) is connected to a first of the four current biases (S1);

a second terminal of the first transistor (MN1) is connected to a second terminal of the third transistor (MN3), a terminal of the third capacitor (C3), and a terminal of the first resistor (R1);

the other end of the third capacitor (C3) receives a positive voltage signal (Vin +) of the common mode input voltage signal;

the other end of the first resistor (R1) is grounded;

a first terminal of the third transistor (MN3) is coupled to a control terminal of the third transistor (MN3), to one terminal of the first capacitor (C1), and to a second of the four current biases (S2);

the other end of the first capacitor (C1) is connected with one end of the second capacitor (R2), one end of the fourth capacitor (C4), and a second end of the fourth transistor (MN4), a second end of the second transistor (MN 2);

the other end of the fourth capacitor (C4) receives a negative voltage signal (Vin-) of the common-mode input voltage signal;

the other ends of the second resistors (R2) are all grounded;

the control end of the second transistor (MN2) is connected with the control end of the fourth transistor (MN 4);

a first terminal of the second transistor (MN2) is connected to a fourth one of the four current biases (S4);

a first terminal of the fourth transistor (MN4) is connected to a control terminal of the fourth transistor (MN4), to a terminal of the second capacitor (C2), and to a third one of the four current biases (S3);

the other end of the second capacitor (C2) is used for receiving a positive voltage signal (Vin +) of the common-mode input voltage signal.

3. The receiving circuit of the isolated driving circuit according to claim 2, wherein the current generating and mirroring circuit (1) comprises:

a fifth transistor (MP1), a sixth transistor (MP2), a seventh transistor (MP3), a first current source (I1), and a second current source (I2);

wherein a control terminal of the fifth transistor (MP1) is configured to receive a control of a first enable signal (CMD _ P), a second terminal of the fifth transistor (MP1) is connected to a control terminal of the sixth transistor (MP2), and a first terminal and a control terminal of the fifth transistor (MP1) are connected to a power supply (VCC);

a control terminal of the sixth transistor (MP2) is connected to a control terminal of the seventh transistor (MP3), a second terminal of the sixth transistor (MP2) is the first current bias (S1), and a first terminal of the sixth transistor (MP2) is connected to a power supply (VCC);

a second terminal of the seventh transistor (MP3) is the fourth current bias (S4), and a first terminal of the seventh transistor (MP3) is connected to a power supply (VCC);

one end of the first current source (I1) is connected to the power supply (VCC), and the other end is used as the second current bias (S2);

one end of the second current source (I2) is connected to the power supply (VCC), and the other end serves as the third current bias (S3).

4. The receive circuit of the isolation drive circuit according to claim 3, wherein the common mode feedback circuit (2) comprises: an eighth transistor (MP4), a ninth transistor (MP5), a tenth transistor (MP6), an eleventh transistor (MN5), and a twelfth transistor (MN 6);

wherein a first terminal of the eighth transistor (MP4), a first terminal of the ninth transistor (MP5), and a first terminal of the tenth transistor (MP6) are all connected to the power supply (VCC);

a control terminal of the eighth transistor (MP4) is connected to the fourth current bias (S4);

a control terminal of the ninth transistor (MP5) is connected to the first path current bias (S1);

a control terminal of the tenth transistor (MP6) is connected to a control terminal of the seventh transistor (MP 3);

a second terminal of the eighth transistor (MP4) is connected to the second terminal of the ninth transistor (MP5) and to the first terminal of the eleventh transistor (MN5), the control terminal of the eleventh transistor (MN5), and the control terminal of the twelfth transistor (MN 6);

a second terminal of the tenth transistor (MP6) is connected to the control terminal of the tenth transistor (MP6) and the first terminal of the twelfth transistor (MN 6);

a second terminal of the eleventh transistor (MN5) and a second terminal of the twelfth transistor (MN6) are both grounded.

5. The receive circuit of the isolated driver circuit according to claim 4, wherein the pre-amplifying circuit (3) comprises: a third resistor (R3), a fourth resistor (R4), a first triode (Q1), a second triode (Q2), a thirteenth transistor (MN7), a fourteenth transistor (MN8), a fifteenth transistor (MN9) and a third current source (I3);

wherein one end of each of the third resistor (R3) and the fourth resistor (R4) is connected to the power supply (VCC);

the other end of the third resistor (R3) is connected with the first end of the first triode (Q1) to be used as a negative output end (OUT-);

the control terminal of the first triode (Q1) is used for receiving a positive voltage signal (Vin +) of the common-mode input voltage signal;

the other end of the fourth resistor (R4) is connected with the first end of the second triode (Q2) to serve as a positive output end (OUT +);

the control end of the second triode (Q2) is used for receiving a negative voltage signal (Vin-) of the common-mode input voltage signal;

a second terminal of the first transistor (Q1) is connected to a second terminal of the second transistor (Q2) and to a first terminal of the thirteenth transistor (MN 7);

one end of the third current source (I3) is connected to the power supply (VCC), and the other end is connected to the control terminal of the thirteenth transistor (MN7), the first terminal of the fourteenth transistor (MN8), the control terminal of the fourteenth transistor (MN8), and the first terminal of the fifteenth transistor (MN 9);

a second terminal of the fourteenth transistor (MN8) and a second terminal of the fifteenth transistor (MN9) are both grounded;

the control terminal of the fifteenth transistor (MN9) is used for receiving the control of the second enable signal (CMD _ N).

6. The receiving circuit of an isolated driving circuit according to claim 5, wherein the comparison circuit (4) comprises: a sixteenth transistor (MP7), a seventeenth transistor (MP8), an eighteenth transistor (MP9), a nineteenth transistor (MP10), a twentieth transistor (MP11), a twenty-first transistor (MP12), a twentieth transistor (MP13), a twenty-third transistor (MP14), a twenty-fourth transistor (MN10), a twenty-fifth transistor (MN11), a twenty-sixth transistor (MN12), a twenty-seventh transistor (MN13), a twenty-eighth transistor (MN14), a twenty-ninth transistor (MN15), a thirty-third transistor (MN16), a thirty-eleventh transistor (MN17), a thirty-second transistor (MN18), a fourth current source (I4), and a fifth resistor (R5);

wherein a first terminal of the sixteenth transistor (MP7), a first terminal of the seventeenth transistor (MP8), a first terminal of the eighteenth transistor (MP9), a first terminal of the nineteenth transistor (MP10), a first terminal of the twentieth transistor (MP11), a first terminal of the twenty-first transistor (MP12), a first terminal of the twenty-second transistor (MP13), a first terminal of the twenty-third transistor (MP14), and a terminal of the fourth current source (I4) are all connected to the power supply (VCC);

the other end of the fourth current source (I4) is connected to the first end of the twenty-fourth transistor (MN10), the first end of the twenty-fifth transistor (MN11), the control end of the twenty-fifth transistor (MN11) and the control end of the twenty-seventh transistor (MN 13);

a second terminal of the twenty-fourth transistor (MN10), a second terminal of the twenty-fifth transistor (MN11), a second terminal of the twenty-sixth transistor (MN12), a second terminal of the twenty-seventh transistor (MN13), a second terminal of the twenty-eighth transistor (MN14), a second terminal of the twenty-ninth transistor (MN15), and a second terminal of the thirty-second transistor (MN18) are all grounded;

a control terminal of the twenty-fourth transistor (MN10) is configured to receive control of the second enable signal (CMD _ N);

a second terminal of the sixteenth transistor (MP7) is connected to the first terminal of the twenty-sixth transistor (MN12), the control terminal of the twenty-sixth transistor (MN12), the control terminal of the twenty-ninth transistor (MN15), and the first terminal of the twenty-eighth transistor (MN 14);

a control terminal of the twenty-eighth transistor (MN14) is configured to receive control of the second enable signal (CMD _ N);

a control terminal of the sixteenth transistor (MP7) is connected to the second terminal of the seventeenth transistor (MP8) and the control terminal of the eighteenth transistor (MP 9);

a control terminal of the seventeenth transistor (MP8) is configured to receive control of the first enable signal (CMD _ P);

a second terminal of the eighteenth transistor (MP9) is connected to a first terminal of the thirty-first transistor (MN 17);

the control end of the thirty-first transistor (MN17) is connected with the negative input end (V-) of the power supply;

a second terminal of the thirty-first transistor (MN17) is connected to one terminal of the fifth resistor (R5);

the other end of the fifth resistor (R5) is connected to the first end of the twenty-seventh transistor (MN13) and the second end of the thirtieth transistor (MN 16);

a control terminal of the twenty-fourth transistor (MN10) is connected to the second terminal of the twentieth transistor (MP11) and the control terminal of the twenty-first transistor (MP 12);

a control terminal of the twentieth transistor (MP11) is configured to receive control of the first enable signal (CMD _ P);

a second terminal of the nineteenth transistor (MP10) is connected to a first terminal of the thirtieth transistor (MN 16);

the control end of the thirtieth transistor (MN16) is connected with the positive power supply input end (V +);

a second terminal of the twenty-first transistor (MP12) is connected to a second terminal of the twenty-second transistor (MP13), a control terminal of the twenty-third transistor (MP14), a first terminal of the twenty-ninth transistor (MN15), and a control terminal of the thirty-second transistor (MN 18);

a control terminal of the twentieth transistor (MP13) is configured to receive control of the first enable signal (CMD _ P);

the second end of the twenty-third transistor (MP14) is connected to the first end of the thirty-second transistor (MN18) and serves as the output terminal (Vout) of the comparator.

7. The receiving circuit of the isolated driving circuit of claim 6, wherein the first transistor (MN1), the second transistor (MN2), the third transistor (MN3), the fourth transistor (MN4), the eleventh transistor (MN5), the twelfth transistor (MN6), the thirteenth transistor (MN7), the fourteenth transistor (MN8), the fifteenth transistor (MN9), the twenty-fourth transistor (MN10), the twenty-fifth transistor (MN11), the twenty-sixth transistor (MN12), the twenty-seventh transistor (MN13), the twenty-eighth transistor (MN14), the twenty-ninth transistor (MN15), the thirty transistor (MN16), the thirty transistor (MN17), the thirty transistor (MN18) are all NMOS transistors;

the fifth transistor (MP1), the sixth transistor (MP2), the seventh transistor (MP3), the eighth transistor (MP4), the ninth transistor (MP5), the tenth transistor (MP6), the sixteenth transistor (MP7), the seventeenth transistor (MP8), the eighteenth transistor (MP9), the nineteenth transistor (MP10), the twentieth transistor (MP11), the twenty-first transistor (MP12), the twenty-second transistor (MP13), and the twenty-third transistor (MP14) are all PMOS transistors.

Technical Field

The invention relates to the field of design of a SiC high-voltage isolation driving integrated circuit of a new energy automobile, in particular to a receiving circuit of an isolation driving circuit.

Background

The SiC is a core power device of a third-generation semiconductor of the new energy automobile, and a driving and protecting circuit is indispensable for reasonably controlling the on-off of the SiC device, detecting and protecting the SiC device.

With the development of the third generation semiconductor SiC on the aspect of high-voltage and high-speed device characteristics, the high-voltage and low-on impedance characteristics of SiC have more and more obvious advantages compared with the traditional silicon-based power device in the aspect of processing high voltage and high power, but each high-voltage SiC device needs a corresponding driving circuit to realize the control from an MCU (microprogrammed control Unit) to a high-voltage switch SiC, and the voltage at the MCU end is only 1.8V-5V and even lower; and the voltage domain of the SiC end is as high as 1700V-3300V and even higher, so a high-voltage isolation driving transceiving circuit is needed to realize the signal transmission.

In an isolation driving transceiving circuit suitable for a SiC high-voltage application environment, a receiving end is very easily influenced by serious high-speed common mode interference in a traditional transceiving mode, the amplitude of an interference receiving signal is different from 50V/ns to 200V/ns or even higher according to different starting speeds and working voltages of SiC. The larger the common mode interference, the worse the signal quality and the lower the reliability of the transmission.

Disclosure of Invention

In view of this, the present invention provides a receiving circuit suitable for an isolation driving circuit, so as to solve the problems of poor signal quality and low transmission reliability caused by serious high-speed common-mode interference on a receiving end in an isolation driving receiving and transmitting circuit in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

a receive circuit for an isolated driver circuit, comprising:

the differential pair input module is used for receiving a common mode input voltage signal and inhibiting the noise of the common mode input voltage signal;

the current generation and mirror image circuit is used for receiving a first enable signal and generating four paths of current bias when the first enable signal is started;

the input end and the output end of the common mode feedback circuit are connected with the current generation circuit and the two paths of current bias of the mirror image circuit, and the common mode feedback circuit is used for improving the loop common mode gain and stabilizing the common mode signal output by the differential pair input module;

the two input ends of the pre-amplifying circuit are connected with the two paths of current biases and used for amplifying the common-mode signal output by the differential pair input module and improving the bandwidth of the circuit;

two input ends of the comparison circuit are respectively connected with two output ends of the pre-amplification circuit, and the comparison circuit is used for receiving the differential mode signal output by the pre-amplification circuit and outputting a comparison result after comparison;

and the low-pass filter circuit is used for receiving the comparison result of the comparison circuit, performing low-pass filtering and outputting the result as a received signal.

Through the technical scheme, the receiving circuit of the isolation driving circuit comprises the current generating circuit and the mirror image circuit, wherein the current generating circuit and the mirror image circuit are controlled by the enable signal CMD _ P, and the output of the current generating circuit and the output of the mirror image circuit are connected with the differential pair, the common mode feedback circuit and the pre-amplifying circuit. The differential pair is used for suppressing input signal noise, the common mode feedback circuit is used for improving loop common mode gain and stabilizing common mode signals, and the pre-amplification circuit is used for improving the bandwidth of the circuit and increasing the stability of the circuit. The output of the pre-amplifying circuit is connected with a comparator for judging signals, the output of the comparator is connected with a low-pass filter circuit, and the output of the low-pass filter circuit is a receiving signal OUT. When the circuit does not detect the temperature, all the circuits are in a turn-off state, and no power consumption is generated; when the receiving circuit starts to isolate the driving circuit, the current source generation and the mirror circuit output current respectively flow through the two differential pairs to respectively generate a voltage signal positively correlated with the input signal and an output voltage signal. The output signals of the differential pair are input into the pre-amplifying circuit and the comparator in sequence and finally input into the low-pass filter circuit.

The receiving circuit adopting the isolation driving circuit has the advantages of simple circuit structure, area saving, cost reduction, high reliability and improvement of the stability of the isolation circuit, effectively inhibits serious high-speed common mode interference and ensures the integrity of signals. That is, when a high-speed common-mode transient occurs, the amplitude of an input signal is seriously reduced, and the input/output common-mode voltage is also remarkably changed.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a block diagram of a receiving circuit of an isolation driving circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a receiving circuit of an isolation driving circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a pre-amplifying circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a comparison circuit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a block diagram of a receiving circuit of an isolation driving circuit according to an embodiment of the present invention; the receiving circuit of the isolation driving circuit comprises a current generation and mirror image circuit 1, a common mode feedback circuit 2, a pre-amplification circuit 3, a comparator circuit 4, a low-pass filter circuit 5 and a differential pair input module 6.

In this embodiment, the differential pair input module 6 is configured to receive a common mode input voltage signal and suppress noise of the common mode input voltage signal; the current generation and mirror circuit 1 is used for receiving a first enable signal CMD _ P and generating four current biases when the first enable signal CMD _ P is started; the input end and the output end of the common mode feedback circuit 2 are connected with the current generation and two-way current bias of the mirror circuit 1 and are used for improving the common mode gain of the loop and stabilizing the common mode signal output by the differential pair input module; two input ends of the pre-amplifying circuit 3 are connected with two paths of current biases and used for amplifying the common-mode signal output by the differential pair input module 6 and improving the bandwidth of the circuit; two input ends of the comparison circuit 4 are respectively connected with two output ends of the pre-amplification circuit 3, and the comparison circuit 4 is used for receiving the differential mode signal output by the pre-amplification circuit 3 and outputting a comparison result after comparison; and the low-pass filter circuit 5 is used for receiving the comparison result of the comparison circuit, performing low-pass filtering and outputting the result as a receiving signal OUT.

The connection relationship between the circuit modules provided in this embodiment can suppress a high-speed common mode transient, and the principle is as follows: when a high-speed common-mode transient occurs, the amplitude of an input chip is seriously reduced, and the input/output common-mode voltage is also obviously changed.

Referring to fig. 2, fig. 2 is a schematic diagram of a specific structure of a receiving circuit of an isolation driving circuit according to an embodiment of the present invention, in which the differential pair input module 6 includes: the circuit comprises a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MN4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1 and a second resistor R2.

Wherein, the control terminal of the first transistor MN1 is connected with the control terminal of the third transistor MN 3; a first terminal of the first transistor MN1 is connected to a first current bias S1 of the four current biases; a second terminal of the first transistor MN1 is connected to a second terminal of the third transistor MN3, one terminal of the third capacitor C3, and one terminal of the first resistor R1, and the other terminal of the third capacitor C3 receives a positive voltage signal Vin + of the common mode input voltage signal; one end of the first resistor R1 is grounded; a first end of the third transistor MN3 is connected to a control end of the third transistor MN3, one end of the first capacitor C1, and a second of the four current biases S2; the other end of the first capacitor C1 is connected to one end of the second capacitor R2, one end of the fourth capacitor C4, the second end of the fourth transistor MN4 and the second end of the second transistor MN2, and the other end of the fourth capacitor C4 receives a negative voltage signal Vin-of the common-mode input voltage signal; the other end of the second resistor R2 is grounded; the control terminal of the second transistor MN2 is connected with the control terminal of the fourth transistor MN 4; a first terminal of the second transistor MN2 is connected to a fourth current bias S4 of the four current biases; a first terminal of the fourth transistor MN4 is connected to the control terminal of the fourth transistor MN4, to one terminal of the second capacitor C2, and to a third one of the four current biases S3; the other end of the second capacitor C2 is used for receiving the positive voltage signal Vin + of the common mode input voltage signal.

In this embodiment, specific types of the transistors are not limited, and optionally, in this embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS transistors. Correspondingly, the first end is the drain electrode of the NMOS tube, the second end is the source electrode of the NMOS tube, and the control end is the grid electrode of the NMOS tube.

The current mirror generation and mirror circuit 1 includes a fifth transistor MP1, a sixth transistor MP2, a seventh transistor MP3 with an enable function, a first current source I1, a second current source I2, an input control signal CMD _ P, and an output as a four-channel current source, which is a first current bias S1, a second current bias S2, a third current bias S3, and a fourth current bias S4.

A control terminal of the fifth transistor MP1 is configured to receive control of the first enable signal CMD _ P, a second terminal of the fifth transistor MP1 is connected to a control terminal of the sixth transistor MP2, and a first terminal and a control terminal of the fifth transistor MP1 are connected to the power source VCC;

a control terminal of the sixth transistor MP2 is connected to a control terminal of the seventh transistor MP3, a second terminal of the sixth transistor MP2 is a first current bias S1, and a first terminal of the sixth transistor MP2 is connected to the power source VCC; the second terminal of the seventh transistor MP3 is a fourth current bias S4, and the first terminal of the seventh transistor MP3 is connected to the power source VCC; one end of the first current source I1 is connected with a power supply VCC, and the other end is used as a second current bias S2; one end of the second current source I2 is connected to the power source VCC, and the other end is used as the third current bias S3.

In this embodiment, specific types of the transistors are not limited, and optionally, in this embodiment, the fifth transistor, the sixth transistor, and the seventh transistor are all PMOS transistors. Correspondingly, the first end is the source electrode of the PMOS tube, the second end is the drain electrode of the PMOS tube, and the control end is the grid electrode of the PMOS tube.

That is, in the current mirror generating and mirroring circuit in the present embodiment, the gate of the fifth transistor MP1 is connected to the input control signal CMD _ P, the drain of the fifth transistor MP1 is connected to the gate of the sixth transistor MP2, and the source of the fifth transistor MP1 and the source not shown in the well potential diagram are connected to the power supply VCC. Wherein the gate of the sixth transistor MP2 is connected to the gate of the seventh transistor MP3, the drain of the sixth transistor MP2 is the current output terminal S1, i.e. the first current bias S1, the source and well potential of the sixth transistor MP2 are connected to the power supply VCC, wherein the drain of the seventh transistor MP3 is the current output terminal S4, i.e. the fourth current bias S4, the source and well potential of the seventh transistor MP3 are connected to the power supply VCC. Wherein the first current source I1 and the second current source I2 are provided by reference currents.

With continued reference to fig. 2, the common mode feedback circuit 2 includes: an eighth transistor MP4, a ninth transistor MP5, a tenth transistor MP6, an eleventh transistor MN5, and a twelfth transistor MN 6.

A first terminal of the eighth transistor MP4, a first terminal of the ninth transistor MP5, and a first terminal of the tenth transistor MP6 are all connected to the power supply VCC; the control terminal of the eighth transistor MP4 is connected to the fourth current bias S4; the control terminal of the ninth transistor MP5 is connected to the first path current bias S1; a control terminal of the tenth transistor MP6 is connected to a control terminal of the seventh transistor MP 3; a second terminal of the eighth transistor MP4 is connected to the second terminal of the ninth transistor MP5, and to the first terminal of the eleventh transistor MN5, the control terminal of the eleventh transistor MN5, and the control terminal of the twelfth transistor MN 6; a second terminal of the tenth transistor MP6 is connected to the control terminal of the tenth transistor MP6 and the first terminal of the twelfth transistor MN 6; a second terminal of the eleventh transistor MN5 and a second terminal of the twelfth transistor MN6 are both grounded.

Similarly, the specific type of each transistor is not limited in this embodiment, and optionally, in this embodiment, the eighth transistor, the ninth transistor, and the tenth transistor are all PMOS transistors. Correspondingly, the first end is the source electrode of the PMOS tube, the second end is the drain electrode of the PMOS tube, and the control end is the grid electrode of the PMOS tube. The eleventh transistor and the twelfth transistor are both NMOS transistors. Correspondingly, the first end is the drain electrode of the NMOS tube, the second end is the source electrode of the NMOS tube, and the control end is the grid electrode of the NMOS tube.

Specifically, the gate of the eighth transistor MP4 is connected to the current output terminal S4, the drain of the eighth transistor MP4 is connected to the drain of the ninth transistor MP5, and the source and the well potential of the eighth transistor MP4 are connected to the power supply VCC. Wherein the gate of the ninth transistor MP5 is connected to the current output terminal S1, the drain of the ninth transistor MP5 is connected to the drain of the eleventh transistor MN5, and the source and well potential of the ninth transistor MP5 are connected to the power supply VCC. Wherein a gate of the eleventh transistor MN5 is connected to a gate of the twelfth transistor MN6, a drain of the transistor MP5 is connected to a gate of the eleventh transistor MN5, and a source and a substrate of the eleventh transistor MN5 are connected to the ground power source GND. Wherein the drain of the twelfth transistor MN6 is connected to the drain of the tenth transistor MP6, and the source and substrate of the twelfth transistor MN6 are connected to the ground power supply GND. Wherein a gate of the tenth transistor MP6 is connected to a gate of the seventh transistor MP3, a drain of the tenth transistor MP6 is connected to a gate of the tenth transistor MP6, and a source and a well potential of the tenth transistor MP6 are connected to the power source VCC.

Referring to fig. 3, fig. 3 is a schematic diagram of a pre-amplifying circuit according to an embodiment of the present invention; the pre-amplifying circuit 3 includes a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2, a thirteenth transistor MN7, a fourteenth transistor MN8, a fifteenth transistor MN9, and a third current source I3.

One ends of the third resistor R3 and the fourth resistor R4 are both connected with a power supply VCC; the other end of the third resistor R3 is connected with the first end of the first triode Q1 to be used as a negative output end OUT-; the control end of the first triode Q1 is used for receiving a positive voltage signal Vin + of the common-mode input voltage signal; the other end of the fourth resistor R4 is connected with the first end of the second triode Q2 to serve as a positive output end OUT +; the control end of the second triode Q2 is used for receiving a negative voltage signal Vin-of the common-mode input voltage signal; a second terminal of the first transistor Q1 is connected to a second terminal of the second transistor Q2, and to a first terminal of a thirteenth transistor MN 7; one end of the third current source I3 is connected to the power VCC, and the other end is connected to the control terminal of the thirteenth transistor MN7, the first terminal of the fourteenth transistor MN8, the control terminal of the fourteenth transistor MN8, and the first terminal of the fifteenth transistor MN 9; a second terminal of the fourteenth transistor MN8 and a second terminal of the fifteenth transistor MN9 are both grounded; a control terminal of the fifteenth transistor MN9 is configured to receive control of the second enable signal CMD _ N.

Similarly, the specific type of each transistor is not limited in this embodiment, and optionally, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor in this embodiment are all NMOS transistors. Correspondingly, the first end is the drain electrode of the NMOS tube, the second end is the source electrode of the NMOS tube, and the control end is the grid electrode of the NMOS tube.

Specifically, the base of the first transistor Q1 is connected to the positive input terminal Vin +, the collector of the first transistor Q1 is connected to the negative output terminal OUT-, and the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2. Wherein the base of the second transistor Q2 is connected to the negative input terminal Vin-, the collector of the second transistor Q2 is connected to the positive output terminal OUT +, and the emitter of the second transistor Q2 is connected to the drain of the thirteenth transistor MN 7. Wherein the gate of the transistor MN7 is connected to the gate of the fourteenth transistor MN8, and the source and the substrate of the thirteenth transistor MN7 are connected to the ground power source GND. Wherein the gate of the fourteenth transistor MN8 is connected to the drain of the fourteenth transistor MN8, the drain of the fourteenth transistor MN8 is connected to the drain of the fifteenth transistor MN9, and the source and the substrate of the fourteenth transistor MN8 are connected to the ground power source GND. Wherein the gate of the fifteenth transistor MN9 is connected to the input control signal CMD _ N, and the source and the substrate of the fifteenth transistor MN9 are connected to the ground power source GND. One end of the third resistor R3 is connected to the collector of the first transistor Q1, and the other end of the third resistor R3 is connected to the power supply VCC. One end of the fourth resistor R4 is connected to the collector of the second transistor Q2, and the other end of the third resistor R3 is connected to the power supply VCC. Wherein the third current source I3 is provided by a reference current, and the third current source I3 is connected to the drain of the fourteenth transistor MN 8.

Referring to fig. 4, fig. 4 is a schematic diagram of a comparison circuit according to an embodiment of the present invention; the comparator 4 circuit includes a sixteenth transistor MP7, a seventeenth transistor MP8, an eighteenth transistor MP9, a nineteenth transistor MP10, a twentieth transistor MP11, a twenty-first transistor MP12, a twenty-second transistor MP13, a twenty-third transistor MP14, a twenty-fourth transistor MN10, a twenty-fifth transistor MN11, a twenty-sixth transistor MN12, a twenty-seventh transistor MN13, a twenty-eighth transistor MN14, a twenty-ninth transistor MN15, a thirty-third transistor MN16, a thirty-first transistor MN17, a thirty-second transistor MN18, and a fourth current source I4 and a fifth resistor R5 with an enable function.

The first end of the sixteenth transistor MP7, the first end of the seventeenth transistor MP8, the first end of the eighteenth transistor MP9, the first end of the nineteenth transistor MP10, the first end of the twentieth transistor MP11, the first end of the twenty-first transistor MP12, the first end of the twenty-second transistor MP13, the first end of the twenty-third transistor MP14, and one end of the fourth current source I4 are all connected to the power source VCC; the other end of the fourth current source I4 is connected to the first end of a twenty-fourth transistor MN10, the first end of a twenty-fifth transistor MN11, the control end of a twenty-fifth transistor MN11 and the control end of a twenty-seventh transistor MN 13; the second end of the twenty-fourth transistor MN10, the second end of the twenty-fifth transistor MN11, the second end of the twenty-sixth transistor MN12, the second end of the twenty-seventh transistor MN13, the second end of the twenty-eighth transistor MN14, the second end of the twenty-ninth transistor MN15, and the second end of the thirty-second transistor MN18 are all grounded.

A control terminal of the twenty-fourth transistor MN10 is for receiving control of the second enable signal CMD _ N; a second end of the sixteenth transistor MP7 is connected to the first end of the twenty-sixth transistor MN12, the control end of the twenty-sixth transistor MN12, the control end of the twenty-ninth transistor MN15, and the first end of the twenty-eighth transistor MN 14; a control terminal of the twenty-eighth transistor MN14 is for receiving control of the second enable signal CMD _ N; a control terminal of the sixteenth transistor MP7 is connected to the second terminal of the seventeenth transistor MP8 and the control terminal of the eighteenth transistor MP 9; a control terminal of the seventeenth transistor MP8 is used for receiving control of the first enable signal CMD _ P; a second terminal of the eighteenth transistor MP9 is connected to a first terminal of the thirty-first transistor MN 17; the control end of the thirty-first transistor MN17 is connected with the negative input end V-of the power supply; a second terminal of the thirty-first transistor MN17 is connected to one terminal of a fifth resistor R5; the other end of the fifth resistor R5 is connected with the first end of the twenty-seventh transistor MN13 and the second end of the thirty-third transistor MN 16; a control terminal of the twenty-fourth transistor MN10 is connected to the second terminal of the twentieth transistor MP11 and the control terminal of the twenty-first transistor MP 12; the control terminal of the twentieth transistor MP11 is for receiving control of the first enable signal CMD _ P; a second terminal of the nineteenth transistor MP10 is connected to a first terminal of the thirtieth transistor MN 16; the control end of the thirtieth transistor MN16 is connected with the positive power supply input end V +; the second end of the twenty-first transistor MP12 is connected to the second end of the twenty-second transistor MP13, the control end of the twenty-third transistor MP14, the first end of the twenty-ninth transistor MN15, and the control end of the thirty-second transistor MN 18; the control terminal of the twentieth transistor MP13 is used for receiving control of the first enable signal CMD _ P; the second terminal of the twenty-third transistor MP14 is connected to the first terminal of the thirty-second transistor MN18 and serves as the output terminal Vout of the comparator.

Similarly, the specific type of each transistor is not limited in this embodiment, and alternatively, the sixteenth transistor to the twenty-third transistor in this embodiment are all PMOS transistors. Correspondingly, the first end is the source electrode of the PMOS tube, the second end is the drain electrode of the PMOS tube, and the control end is the grid electrode of the PMOS tube. And the twenty-seventh transistor to the thirty-second transistor are all NMOS transistors. Correspondingly, the first end is the drain electrode of the NMOS tube, the second end is the source electrode of the NMOS tube, and the control end is the grid electrode of the NMOS tube.

Specifically, the gate of the twenty-fourth transistor MN10 is connected to the input control signal CMD _ N, the drain of the twenty-fourth transistor MN10 is connected to the drain of the twenty-fifth transistor MN11, and the source and substrate of the twenty-fourth transistor MN10 are connected to the ground power supply GND. Wherein a gate of the twenty-fifth transistor MN11 is connected to a gate of the twenty-seventh transistor MN13, a drain of the twenty-fifth transistor MN11 is connected to a gate of the twenty-fifth transistor MN11, and a source and a substrate of the twenty-fifth transistor MN11 are connected to the ground power supply GND. Wherein the drain of the twenty-seventh transistor MN13 is connected to the source of the thirtieth transistor MN16, and the source and the substrate of the twenty-seventh transistor MN13 are connected to the ground power supply GND. Wherein the gate of the thirtieth transistor MN16 is connected to the positive input terminal V +, the substrate of the thirtieth transistor MN16 is connected to the source thereof, the drain of the thirtieth transistor MN16 is connected to the drain of the nineteenth transistor MP10, and the source of the thirtieth transistor MN16 is connected to one end of the resistor R5. Wherein the other end of the resistor R5 is connected to the source of the transistor MN 17. Wherein the gate of the thirty-first transistor MN17 is connected to the negative input terminal V-, the substrate of the thirty-first transistor MN17 is connected to the source thereof, and the drain of the thirty-first transistor MN17 is connected to the drain of the eighteenth transistor MP 9. Wherein the gate of the eighteenth transistor MP9 is connected to the drain of the seventeenth transistor MP8, and the source and well potential of the eighteenth transistor MP9 are connected to the power supply VCC. Wherein a gate of the seventeenth transistor MP8 is connected to the input control signal CMD _ P, a source and a well potential of the seventeenth transistor MP8 are connected to the power supply VCC, and a drain of the seventeenth transistor MP8 is connected to a gate of the sixteenth transistor MP 7. Wherein the source and well potential of the sixteenth transistor MP7 are connected to the power supply VCC, and the drain of the sixteenth transistor MP7 is connected to the gate of the twenty-sixth transistor MN 12. Wherein the drain of the transistor MN12 is connected to the gate of the twenty-sixth transistor MN12, the gate of the twenty-sixth transistor MN12 is connected to the drain of the twenty-eighth transistor MN14, and the source and substrate of the twenty-sixth transistor MN12 are connected to the ground power supply GND. Wherein a drain of the twenty-eighth transistor MN14 is connected to a gate of the twenty-ninth transistor MN15, a gate of the twenty-eighth transistor MN14 is connected to the input control signal CMD _ N, and a source and a substrate of the twenty-eighth transistor MN14 are connected to the ground power supply GND. Wherein the drain of the twenty-ninth transistor MN15 is connected to the drain of the twenty-first transistor MP12, and the source and substrate of the twenty-ninth transistor MN15 are connected to the ground power supply GND. Wherein the gate of the nineteenth transistor MP10 is connected to the drain of the twentieth transistor MP11, and the source and well potential of the nineteenth transistor MP10 are connected to the power supply VCC. Wherein a gate of the twentieth transistor MP11 is connected to the input control signal CMD _ P, a source and a well potential of the twentieth transistor MP11 are connected to the power supply VCC, and a drain of the twentieth transistor MP11 is connected to a gate of the twenty-first transistor MP 12. Wherein the source and well potential of the twenty-first transistor MP12 are connected to the power supply VCC, and the drain of the twenty-first transistor MP12 is connected to the drain of the twenty-second transistor MP 13. Wherein the gate of the twentieth transistor MP13 is connected to the input control signal CMD _ P, the source and the well potential of the twentieth transistor MP13 are connected to the power supply VCC, and the drain of the twentieth transistor MP13 is connected to the gate of the twenty-third transistor MP 14. Wherein the gate of the twenty-third transistor MP14 is connected to the gate of the thirty-second transistor MN18, the drain of the twenty-third transistor MP14 is connected to the drain of the thirty-second transistor MN18, and the source and well potential of the twenty-third transistor MP14 are connected to the power supply VCC. Wherein the drain of the thirty-second transistor MN18 is connected to the output terminal Vout of the comparator, and the source and substrate of the thirty-second transistor MN18 are connected to the power supply VCC.

The invention adopts a fully differential self-adaptive input structure to realize differential amplification and pre-amplification processing of an input signal, in particular, when a positive high-speed common-mode transient occurs, constant current Cdu/dt is injected outwards into input ends Vin + and Vin-, wherein C1 and C2 are external capacitors, the value of the external capacitors is C, du/dt is the positive high-speed common-mode transient, the input common-mode voltage is equal to-Cdu/dt R1 or-Cdu/dt R2, and R1 is R2; when a negative high-speed common-mode transient occurs, constant current Cdu/dt is injected into the input ends Vin + and Vin-, wherein C is the value of the external capacitor C3 ═ C4 ═ C, and the structure formed by input common-mode transient voltage Cdu/dt × R1, Cdu/dt × R2, R1 ═ R2 and MN1-MN4 can effectively adapt to two common-mode input voltages in different directions, ensure to work in a proper amplification detection direct-current working point, and provide a correct working point for the Vin +/Vin-differential input signal of the input signal.

The first current source I1 in the current generation and mirror circuit flows through the third transistor MN3 connected to provide a bias voltage for the first transistor MN1, so that the bias voltage of the third transistor MN3 is equal to V_GS3+ Vin +; wherein V_GS3Is the gate-source voltage of the third transistor MN 3; the second current source I2 flows through the fourth transistor MN4 connected to provide a bias voltage to the second transistor MN2, so that the bias voltage of the second transistor MN2 is equal to V_GS4+ Vin-, where V_GS4Is the gate-source voltage of the fourth transistor MN 4; since I1 is I2, V_GS3＝V_GS4The input common-mode voltages are equal, so the common-mode bias voltages of the third transistor MN3 and the fourth transistor MN4 are equal, and at the same time, because the third transistor MP3 and the fourth transistor MP4 are identical, the common-mode voltages of the first path current bias S1 and the second path current bias S2 are equal.

The sum of the common mode voltages of the third current bias S3 and the fourth current bias S4 in the common mode feedback circuit generates a current sum through the eighth transistor MP4 and the ninth transistor MP 5:

IMP4+IMP5＝1/2*un*Cox(W/L)₄(|VGS4|-VTH)^2+1/2*un*Cox(W/L)₅(|VGS4|-VT

H)^2

wherein un is electron mobility, Cox is unit area gate oxide capacitance, and V_THIs the threshold voltage, (W/L)₄Is the width-to-length ratio of the eighth transistor MP 4; (W/L)₅Is the width-to-length ratio of the ninth transistor MP 5.

Common mode negative feedback loop stabilization V_GS4+V_GS5That is, the common mode voltage of the third path current bias S3 and the fourth path current bias S4 is stabilized.

The pre-amplification circuit utilizes the first transistor Q1 and the second transistor Q2 to provide speed and achieve high speed and low gain.

The comparison circuit generates a comparison threshold voltage V through a fifth resistor R5_TH1，

VTH1＝IMP9*R5

Wherein, I_MP9Is the current through the eighteenth transistor MP9, I when at the comparator inversion point_MP9＝I_MP10＝1/2*I_MN13In which I_MP10Is the current, I, flowing through the nineteenth transistor MP10_MN13Is the current flowing through the twenty-seventh transistor MN13, the comparison threshold voltage V can be set by designing the current of the twenty-seventh transistor MN13 and the value of the fifth resistor R5_TH1。

V_TH1The voltage can effectively inhibit differential mode noise and prevent false triggering.

The filter is used in a digital or analog manner to restore the discrete square wave to the same square wave as the input voltage Vin.

Therefore, the following advantages are provided as compared with the conventional receiving circuit: 1. the method can be simultaneously suitable for signal communication under high-speed severe common-mode interference in positive and negative directions; 2. the structure is simple, and when the input common-mode voltage generates high-speed common-mode interference, the safe and reliable floating common-mode input voltage can be realized according to the severity of the interference. 3. When serious high-speed common mode interference occurs, the stability of the output common mode voltage of the pre-amplifying circuit can be realized, and the reliability of the circuit is ensured.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is to be understood that the word "comprising" does not exclude other modules or steps, and the singular does not exclude the plural.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.