阅读说明：本技术 一种混合双尾动态锁存比较器 (Hybrid two-tail dynamic latch comparator ) 是由 苏杰 李孙华 徐祎喆 朱勇 于 2020-12-14 设计创作，主要内容包括：本申请公开了一种混合双尾动态锁存比较器,属于电路设计领域。本申请的一种混合双尾动态锁存比较器包括预放大时钟控制单元,其通过同相时钟信号控制其中间输出节点的电位状态,其中电位状态包括充电状态和放电状态；交叉耦合单元,其对混合双尾动态锁存比较器的有效跨导和中间差分电压进行调节,其两个输入端分别对应连接预放大输入单元的两个输出端和锁存结构单元的两个输入端；反馈控制单元,其对中间输出节点接收到的信号进行反馈,并根据锁存结构单元的输入信号控制反馈控制单元的通断,其两个输入端对应连接交叉耦合单元的两个输入端。本申请减小了混合双尾动态锁存比较器的延迟,减小了功耗和噪声影响。(The application discloses mixed two tail developments latch comparator belongs to the circuit design field. The hybrid two-tail dynamic latch comparator comprises a pre-amplification clock control unit, a first-stage latch unit and a second-stage latch unit, wherein the pre-amplification clock control unit controls the potential state of an intermediate output node of the pre-amplification clock control unit through an in-phase clock signal, and the potential state comprises a charging state and a discharging state; the cross coupling unit is used for adjusting the effective transconductance and the intermediate differential voltage of the hybrid two-tail dynamic latch comparator, and two input ends of the cross coupling unit are respectively and correspondingly connected with two output ends of the pre-amplification input unit and two input ends of the latch structure unit; and the feedback control unit feeds back the signal received by the intermediate output node and controls the on-off of the feedback control unit according to the input signal of the latching structure unit, and two input ends of the feedback control unit are correspondingly connected with two input ends of the cross coupling unit. The delay of the hybrid two-tail dynamic latch comparator is reduced, and the power consumption and the noise influence are reduced.)

1. A mixed double-tail dynamic latch comparator comprises a pre-amplification input unit and a latch structure unit, and is characterized by comprising:

a pre-amplification clock control unit which controls a potential state of an intermediate output node thereof by an in-phase clock signal, wherein the potential state includes a charging state and a discharging state;

the cross coupling unit is used for adjusting the effective transconductance and the intermediate differential voltage of the hybrid two-tail dynamic latch comparator, and two input ends of the cross coupling unit are respectively and correspondingly connected with two output ends of the pre-amplification input unit and two input ends of the latch structure unit;

and the feedback control unit feeds back the signal received by the intermediate output node and controls the on-off of the feedback control unit according to the input signal of the latch structure unit, and two input ends of the feedback control unit are correspondingly connected with two input ends of the cross coupling unit.

2. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the intermediate output nodes include an intermediate forward output node and an intermediate backward output node, wherein in the charging state, the potential of the intermediate output node rises to eventually be the same as the external power supply potential, and in the discharging state, the potential of the intermediate output node falls to eventually be the same as the ground potential.

3. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the latching structure unit includes a latching clock control circuit that receives an inverted clock signal to control the operational phase of the output node of the latching structure unit, wherein the operational phase includes a reset phase and an evaluation phase.

4. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the cross-coupling unit includes a first load NMOS transistor and a second load NMOS transistor, wherein,

the drain electrode of the first load NMOS transistor is connected with the positive input end of the latch structure unit, the grid electrode of the first load NMOS transistor is connected with the negative input end of the latch structure unit, and the source electrode of the first load NMOS transistor is grounded;

the drain electrode of the second load NMOS transistor is connected with the negative input end of the latch structure unit, the grid electrode of the second load NMOS transistor is connected with the positive input end of the latch structure unit, and the source electrode of the second load NMOS transistor is grounded.

5. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the pre-amplification clock control unit includes a third NMOS transistor, a fourth NMOS transistor, and a thirteenth PMOS transistor, wherein,

the in-phase clock signal is input through the grid electrode of the third NMOS transistor, the grid electrode of the fourth NMOS transistor and the grid electrode of the thirteenth PMOS transistor, the source electrode of the third NMOS transistor and the source electrode of the fourth NMOS transistor are grounded, and the source electrode of the thirteenth PMOS transistor is connected with an external power supply.

6. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the pre-amplification input cell includes a first PMOS transistor and a second PMOS transistor, wherein,

the grid electrode of the first PMOS transistor is connected with the positive input end of a differential signal, and the drain electrode of the first PMOS transistor is connected with the drain electrode of the third NMOS transistor in the pre-amplification clock control unit;

the grid electrode of the second PMOS transistor is connected with the negative input end of the differential signal, and the drain electrode of the second PMOS transistor is connected with the drain electrode of the fourth NMOS transistor in the pre-amplification clock control unit.

7. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the feedback control unit includes a first switching PMOS transistor and a second switching PMOS transistor, wherein,

a gate of the first switching PMOS transistor is connected to the intermediate forward output node, a drain thereof is connected to a source of the first PMOS transistor in the pre-amplification input unit, and a source thereof is connected to a drain of the thirteenth PMOS transistor in the pre-amplification clock control unit;

the gate of the second switching PMOS transistor is connected to the intermediate inverted output node, the drain thereof is connected to the source of the second PMOS transistor in the pre-amplification input unit, and the source thereof is connected to the drain of the thirteenth PMOS transistor in the pre-amplification clock control unit.

8. The hybrid two-tailed dynamic latching comparator as claimed in claim 1, wherein the latching structural unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, wherein,

the grid electrode of the eleventh NMOS transistor is connected with the negative input end of the latch structure unit, the drain electrodes of the eleventh NMOS transistor and the eleventh PMOS transistor are respectively connected with the drain electrode of the fifth PMOS transistor and the drain electrode of the seventh PMOS transistor, the source electrode of the eleventh NMOS transistor is connected with the drain electrode of the ninth NMOS transistor, the source electrode of the ninth NMOS transistor is grounded, the grid electrode of the ninth NMOS transistor is connected with the grid electrode of the seventh PMOS transistor, and the source electrode of the fifth PMOS transistor and the source electrode of the seventh PMOS transistor are connected with an external power supply;

the twelfth NMOS transistor has a gate connected to the positive input end of the latch structure unit, a drain connected to the drain of the sixth PMOS transistor and the drain of the eighth PMOS transistor, respectively, a source connected to the drain of the tenth NMOS transistor, a source connected to the ground, a gate connected to the gate of the eighth PMOS transistor, and a source connected to the external power supply.

9. The hybrid two-tailed dynamic latching comparator as claimed in claim 3, wherein the latching clock control circuit includes the fifth PMOS transistor and the sixth PMOS transistor, the inverted clock signal being input through a gate of the fifth PMOS transistor and a gate of the sixth PMOS transistor.

10. The hybrid two-tailed dynamic latching comparator as claimed in claim 3, wherein the output nodes of the latching structural unit include an inverting output node and a non-inverting output node, wherein the inverting output node is respectively connected to the drain of the eleventh NMOS transistor and the gate of the tenth NMOS transistor, and the non-inverting output node is respectively connected to the drain of the twelfth NMOS transistor and the gate of the ninth NMOS transistor.

Technical Field

The application relates to the field of circuit design, in particular to a hybrid two-tail dynamic latch comparator.

Background

The comparator is a key module of all analog-to-digital converters, and the speed and the power consumption of the comparator have a crucial influence on the speed and the power consumption of the whole analog-to-digital converter, but the conventional comparator has difficulty in meeting the requirements of the analog-to-digital converter on the speed and the power consumption at the same time, and therefore the conventional circuit structure needs to be improved to meet the application requirements. Conventional dynamic latch comparators have small delay times and low kickback noise, but these high levels come at the expense of large chip area and high loss.

In the prior art, although the cross-coupled configuration of PMOS transistors can be used to improve the signal processing speed of the dynamic latch comparator, its power consumption is significantly increased and is susceptible to long-term kickback noise.

Disclosure of Invention

The application mainly provides a mixed two tail developments latch comparator to it is higher to solve the developments among the prior art latch comparator consumption, easily receives the problem of kickback noise influence.

The technical scheme adopted by the application is as follows: the mixed double-tail dynamic latch comparator comprises a pre-amplification input unit, a latch structure unit and a pre-amplification clock control unit, wherein the pre-amplification clock control unit controls the potential state of a middle output node of the pre-amplification clock control unit through an in-phase clock signal, and the potential state comprises a charging state and a discharging state; the cross coupling unit is used for adjusting the effective transconductance and the intermediate differential voltage of the hybrid two-tail dynamic latch comparator, and two input ends of the cross coupling unit are respectively and correspondingly connected with two output ends of the pre-amplification input unit and two input ends of the latch structure unit; and the feedback control unit feeds back the signal received by the intermediate output node and controls the on-off of the feedback control unit according to the input signal of the latching structure unit, and two input ends of the feedback control unit are correspondingly connected with two input ends of the cross coupling unit.

The technical scheme of the application can reach the beneficial effects that: the application designs a mixed two-tailed dynamic latch comparator, and the cross-coupling configuration that this application used the NMOS transistor has improved the signal processing speed of mixed two-tailed dynamic latch comparator, has also reduced the consumption simultaneously, has reduced the influence of long-term kickback noise.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of one embodiment of a conventional dynamic latch comparator in the prior art;

FIG. 2 is a schematic diagram of one embodiment of a hybrid two-tailed dynamic latch comparator according to the present application;

fig. 3 is a schematic diagram of an embodiment of a hybrid two-tailed dynamic latching comparator according to the present application.

The components in the drawings are numbered as follows: m₁A first PMOS transistor, M₂A second PMOS transistor M₃-a third NMOS transistor, M₄A fourth NMOS transistor, M₅A fifth PMOS transistor M₆A sixth PMOS transistor M₇A seventh PMOS transistor M₈An eighth PMOS transistor M₉-a ninth NMOS transistor, M₁₀A tenth NMOS transistor, M₁₁An eleventh NMOS transistor, M₁₂A twelfth NMOS transistor, M₁₃A thirteenth PMOS transistor M_L1A first load NMOS transistor, M_L2A second load NMOS transistor, M_SW1A first switching PMOS transistor, M_SW2-a second switched PMOS transistor, VDD-external power supply, CLK-in-phase clock signal, CLKn-inverted clock signal, Vin + -differential signal positive voltage, Vin-differential signal negative voltage, IO + -intermediate forward output node, IO-intermediate inverted output node, OUTn-inverted output node, OUTp-in-phase output node.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 is a schematic diagram of a specific example of a conventional dynamic latch comparator in the prior art.

In one specific example of the present application, the conventional dynamic latching comparator shown in fig. 1 includes two stages, namely a pre-amplification stage and a delay stage. When the in-phase clock signal CLK is "1" and the inverted clock signal CLKn is "0", the dynamic latch comparator circuit operates in the reset stage. In the reset phase, the thirteenth PMOS transistor M₁₃In the off state, the third NMOS transistor M₃And a fourth NMOS transistor M₄And is in a conducting state, so that the intermediate forward output node IO + and the intermediate backward output node IO-are discharged to the ground GND, and the potentials of the intermediate forward output node IO + and the intermediate backward output node IO-are finally the same as the potential of the ground terminal. When the fifth PMOS transistor M₅And a sixth PMOS transistor M₆When turned on, the potentials of the inverting output node OUTn and the non-inverting output node OUTp of the latch structure unit are pulled up to the external power supply VDD. When the in-phase clock signal CLK is '0' and the inverted clock signal CLKn is '1', the dynamic latch comparator circuit enters a delay stage where the thirteenth PMOS transistor M enters a delay stage₁₃Turn on, third NMOS transistor M₃And a fourth NMOS transistor M₄And closing. Intermediate forward output node IO + and intermediate reverse output nodePoint IO-charge is started. An intermediate differential voltage Δ VIO + (-) is generated due to the differential input Δ Vin. The intermediate forward output node IO + and the intermediate backward output node IO-are respectively connected to the eleventh NMOS transistor M₁₁And a twelfth NMOS transistor M₁₂A gate electrode of (1). When the intermediate forward output node IO + and the intermediate backward output node IO-are charged to the eleventh NMOS transistor M₁₁And a twelfth NMOS transistor M₁₂Upon entering the cutoff region, the dynamic latch comparator circuit begins entering the evaluation phase. If the differential signal positive voltage Vin + is greater than the differential signal negative voltage Vin-, the potential of the intermediate reverse output node IO-node rises faster than that of the intermediate forward output node IO +. Therefore, at the end of the evaluation, the inverted output node OUTn is discharged back to GND and outputs the charge to the external power supply VDD.

In this embodiment, the conventional dynamic latch comparator circuit is in the delay phase before entering the evaluation phase, which increases power consumption and may pass through the parasitic capacitance of the input transistor of the conventional dynamic latch comparator circuit, i.e. the first PMOS transistor M₁And a second PMOS transistor M₂The parasitic capacitance of (a) generates kickback noise for the input differential signal.

FIG. 2 is a schematic diagram of one embodiment of a hybrid two-tailed dynamic latch comparator according to the present application.

As shown in fig. 2, the hybrid two-tailed dynamic latch comparator of the present application includes a pre-amplification input unit, a latch structure unit, and a pre-amplification clock control unit, which controls the potential state of its intermediate output node by an in-phase clock signal, where the potential state includes a charging state and a discharging state; the cross coupling unit is used for adjusting the effective transconductance and the intermediate differential voltage of the hybrid two-tail dynamic latch comparator, and two input ends of the cross coupling unit are respectively and correspondingly connected with two output ends of the pre-amplification input unit and two input ends of the latch structure unit; and the feedback control unit feeds back the signal received by the intermediate output node and controls the on-off of the feedback control unit according to the input signal of the latching structure unit, and two input ends of the feedback control unit are correspondingly connected with two input ends of the cross coupling unit.

In a specific embodiment of the present application, the intermediate output nodes include an intermediate forward output node and an intermediate backward output node, and the potential states of the intermediate output nodes include a charging state and a discharging state, wherein in the charging state, the potential of the intermediate output node is increased and finally is the same as the potential of the external power source, and in the discharging state, the potential of the intermediate output node is decreased and finally is the same as the potential of the ground terminal.

Fig. 3 is a schematic diagram of an embodiment of a hybrid two-tailed dynamic latching comparator according to the present application.

In one embodiment of the present application, as shown in FIG. 3, when the intermediate output node is in a charged state, the intermediate forward output node IO + and the intermediate backward output node IO-are charged at unequal rates, which are determined by the differential signal positive voltage Vin + and the differential signal negative voltage Vin-, and if Vin + is greater than Vin-, the intermediate backward output node IO-is charged at a greater rate than the intermediate forward output node IO +. When the middle output node is in a discharging state, the potentials of the middle forward output node IO + and the middle reverse output node IO-are directly reduced to be equal to the potential of the ground end.

In one embodiment of the present application, the latch structure unit includes a latch clock control circuit, and the latch clock control circuit receives an inverted clock signal to control an operation phase of an output node of the latch structure unit, wherein the operation phase includes a reset phase and an evaluation phase.

In a specific embodiment of the present application, the latch structure unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, wherein a gate of the eleventh NMOS transistor is connected to the negative input terminal of the latch structure unit, a drain of the eleventh NMOS transistor is connected to a drain of the fifth PMOS transistor and a drain of the seventh PMOS transistor, a source of the eleventh NMOS transistor is connected to a drain of the ninth NMOS transistor, a source of the ninth NMOS transistor is grounded, a gate of the ninth NMOS transistor is connected to a gate of the seventh PMOS transistor, and a source of the fifth PMOS transistor and a source of the seventh PMOS transistor are connected to the external power supply; the grid electrode of the twelfth NMOS transistor is connected with the positive input end of the latch structure unit, the drain electrodes of the twelfth NMOS transistor and the eighth PMOS transistor are respectively connected with the drain electrode of the sixth PMOS transistor and the drain electrode of the eighth PMOS transistor, the source electrode of the twelfth NMOS transistor is connected with the drain electrode of the tenth NMOS transistor, the source electrode of the tenth NMOS transistor is grounded, the grid electrode of the tenth NMOS transistor is connected with the grid electrode of the eighth PMOS transistor, and the source electrode of the sixth PMOS transistor and the source electrode of the eighth PMOS transistor are connected with an external power supply.

In a specific embodiment of the present application, the latch clock control circuit includes a fifth PMOS transistor and a sixth PMOS transistor, and the inverted clock signal is input through a gate of the fifth PMOS transistor and a gate of the sixth PMOS transistor.

In a specific embodiment of the present application, the output nodes of the latch structure unit include an inverting output node and a non-inverting output node, wherein the inverting output node is respectively connected to the drain of the eleventh NMOS transistor and the gate of the tenth NMOS transistor, and the non-inverting output node is respectively connected to the drain of the twelfth NMOS transistor and the gate of the ninth NMOS transistor.

In a specific example of the present application, the eleventh NMOS transistor M₁₁With its gate as the negative input of the latch structure unit, an eleventh NMOS transistor M₁₁Is connected to the fifth PMOS transistor M₅And a seventh PMOS transistor M₇Of the eleventh NMOS transistor M₁₁Is connected to the ninth NMOS transistor M₉To the ninth NMOS transistor M₉Is grounded, a ninth NMOS transistor M₉Is connected with a seventh PMOS transistor M₇A gate of the fifth PMOS transistor M₅And a seventh PMOS transistor M₇The source of the NMOS transistor M is connected with an external power supply VDD₁₂The gate of the first NMOS transistor M is used as the positive input terminal of the latch structure unit₁₂Is connected to the sixth PMOS transistor M₆And an eighth PMOS transistor M₈Of the twelfth NMOS transistor M₁₂Is connected to the tenth NMOS transistor M₁₀Drain of (1), tenth NMOS transistor M₁₀Is grounded, a tenth NMOS transistor M₁₀Of a grid electrodeConnect the eighth PMOS transistor M₈A sixth PMOS transistor M₆And an eighth PMOS transistor M₈The source of the transistor is connected with an external power supply VDD. The inverting output node OUTN is connected to the eleventh NMOS transistor M₁₁Drain of (1), fifth PMOS transistor M₅And a seventh PMOS transistor M₇Is connected to the twelfth NMOS transistor M, the in-phase output node OUTP is connected to the twelfth NMOS transistor M₁₂Drain electrode of (1), sixth PMOS transistor M₆And an eighth PMOS transistor M₈Between the drain electrodes.

In a specific example of the present application, during the reset phase, the potentials of the inverted output node OUTn and the non-inverted output node OUTp in the output nodes are both pulled up to a high potential equal to the external power supply VDD, wherein the intermediate forward output node IO + and the intermediate backward output node IO-are grounded; in the evaluation stage, if the value of the positive voltage Vin + of the differential signal is greater than that of the negative voltage Vin-, because the charging rate of the intermediate reverse output node IO-is greater than that of the intermediate forward output node IO +, the intermediate reverse output node IO-will be in a fully charged state, the potential of the intermediate forward output node IO + is close to the ground, the discharging speed of the inverted output node OUTn in the output nodes is faster than that of the in-phase output node OUTp, and the inverted output node OUTn is discharged to the ground.

In a specific embodiment of the present application, the cross-coupling unit includes a first load NMOS transistor and a second load NMOS transistor, wherein a drain of the first load NMOS transistor is connected to the positive input terminal of the latch structure unit, a gate thereof is connected to the negative input terminal of the latch structure unit, and a source thereof is grounded; the drain electrode of the second load NMOS transistor is connected with the negative input end of the latch structure unit, the grid electrode of the second load NMOS transistor is connected with the positive input end of the latch structure unit, the source electrode of the second load NMOS transistor is grounded, the negative input end of the latch structure unit is connected with the middle reverse output node, and the positive input end of the latch structure unit is connected with the middle forward output node.

In a specific example of the present application, the first load NMOS transistor M in the cross-coupled cell_L1And the second load NMOS transistor M_L2The grid electrodes are all connected with the middleA forward output node IO + and a first load NMOS transistor M_L1And the second load NMOS transistor M_L2Is connected to the intermediate inverted output node IO-, a first load NMOS transistor M_L1And the second load NMOS transistor M_L2Are all grounded.

In a specific embodiment of the present application, the pre-amplification clock control unit includes a third NMOS transistor, a fourth NMOS transistor, and a thirteenth PMOS transistor, wherein the in-phase clock signal is input through a gate of the third NMOS transistor, a gate of the fourth NMOS transistor, and a gate of the thirteenth PMOS transistor, a source of the third NMOS transistor and a source of the fourth NMOS transistor are grounded, and a source of the thirteenth PMOS transistor is connected to the external power supply.

In a specific embodiment of the present application, the pre-amplification input unit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the first PMOS transistor is connected to the positive input terminal of the differential signal, and a drain of the first PMOS transistor is connected to a drain of a third NMOS transistor in the pre-amplification clock control unit; the grid electrode of the second PMOS transistor is connected with the negative input end of the differential signal, and the drain electrode of the second PMOS transistor is connected with the drain electrode of the fourth NMOS transistor in the pre-amplification clock control unit.

In one specific example of the present application, the positive input terminal of the differential signal inputs a differential signal positive voltage Vin +, and the negative input terminal of the differential signal inputs a differential signal negative voltage Vin-.

In a specific embodiment of the present application, the feedback control unit includes a first switching PMOS transistor and a second switching PMOS transistor, wherein a gate of the first switching PMOS transistor is connected to the intermediate forward output node, a drain thereof is connected to a source of the first PMOS transistor in the pre-amplification input unit, and a source thereof is connected to a drain of a thirteenth PMOS transistor in the pre-amplification clock control unit; the gate of the second switching PMOS transistor is connected to the intermediate inverted output node, the drain thereof is connected to the source of the second PMOS transistor in the pre-amplification input unit, and the source thereof is connected to the drain of the thirteenth PMOS transistor in the pre-amplification clock control unit.

In one embodiment of the present application, the in-phase clock signal CLK passes through the third NMOS transistor M in the pre-amplification clock control unit₃Gate of (3), fourth NMOS transistor M₄And a thirteenth PMOS transistor M₁₃The differential signal positive voltage Vin + passes through the first PMOS transistor M in the pre-amplification input unit₁Differential signal negative voltage Vin-through the second PMOS transistor M in the pre-amplification input unit₂Gate input of (1), thirteenth PMOS transistor M₁₃Source of (1) is connected with an external power supply, a thirteenth PMOS transistor M₁₃Is connected to the first switching PMOS transistor M in the feedback control unit_SW1And a second switching PMOS transistor M_SW2A first switching PMOS transistor M_SW1Is connected to the intermediate forward output node IO +, a first switching PMOS transistor M_SW1Is connected to the first PMOS transistor M₁Source of (1), second switching PMOS transistor M_SW2Is connected to the intermediate inverted output node IO-, and a second switching PMOS transistor M_SW2Is connected to the second PMOS transistor M₂A first PMOS transistor M₁Is connected to the third NMOS transistor M₃Drain electrode of (1), second PMOS transistor M₂Is connected to the fourth NMOS transistor M₄Drain of (3), third NMOS transistor M₃And the fourth NMOS transistor M₄Is grounded, and an intermediate forward output node IO + is disposed in the first PMOS transistor M₁And the third NMOS transistor M₃Is arranged between the drains of the second PMOS transistors M, the intermediate inverted output node IO-is arranged between the drains of the second PMOS transistors M₂And the fourth NMOS transistor M₄Between the drain electrodes.

In one embodiment of the present application, the overall operation of the hybrid two-tailed dynamic latch comparator of the present application is described with reference to fig. 3. A hybrid two-tailed dynamic latching comparator, as shown in fig. 3, which makes a new improvement over the conventional dynamic latching comparator. FIG. 3 designs a pair of cross-coupled first load NMOS transistors M_L1And a second load NMOS transistor M_L2To improve the effective transconductance and the intermediate differential voltage delta VIO + (-) and further improve the signal processing speed of the circuitAnd (4) degree. First switching PMOS transistor M_SW1And a second switching PMOS transistor M_SW2Is sandwiched between the thirteenth PMOS transistor M₁₃And a first PMOS transistor M₁And a second PMOS transistor M₂The middle acts as a switch to stop static power consumption. Thus, the delay of the hybrid two-tailed dynamic latching comparator is effectively reduced compared to conventional designs due to the exponential increase of the intermediate differential voltage Δ VIO + (-) with optimal power consumption. In the reset phase, i.e., the in-phase clock signal CLK is equal to "1" and the inverted clock signal CLKn is equal to "0", the third NMOS transistor M₃And a fourth NMOS transistor M₄So that the intermediate reverse output node IO-and the intermediate forward output node IO + node are both grounded, and thus, the first load NMOS transistor M_L1And a second load NMOS transistor M_L2Is cut off, the fifth PMOS transistor M₅And a sixth PMOS transistor M₆The potentials of the inverting output node OUTn and the non-inverting output node OUTp are pulled to the external power supply VDD. In the evaluation phase, i.e., the in-phase clock signal CLK is "0" and the inverted clock signal CLKn is "1", the third NMOS transistor M₃And a fourth NMOS transistor M₄And closing. At the beginning of this evaluation phase, the first load NMOS transistor M_L1And a second load NMOS transistor M_L2Still in the off state because the potentials of both the intermediate backward output node IO-and the intermediate forward output node IO + are close to ground GND. The intermediate backward output node IO-and the intermediate forward output node IO + start to charge at unequal rates, depending on Vin + and Vin-. When Vin +>Vin-, the intermediate backward output node IO-is charged faster than the intermediate forward output node IO +. As long as the intermediate inverted output node IO-continues to charge, the corresponding first load NMOS transistor M_L1It starts to turn on, the first load NMOS transistor M_L1Pulling the potential of the intermediate forward output node IO + node to GND. Thus, the second load NMOS transistor M_L2Remains off and the intermediate inverted output node IO-is fully charged due to the first load NMOS transistor M_L1In the second load NMOS transistor M_L2Previously turned on, the inverted output node OUTn discharges faster than the in-phase output node OUTp. When the eighth PMOS transistor M₈In the seventh PMOS transistor M₇When previously turned on, the potential of the inverted output node OUTn is pulled back to the external power supply VDD. At the end of the evaluation phase (or with the latch set), the inverted output node OUTn discharges to ground GND and outputs the precharged external power supply VDD.

In one embodiment of the present application, in the circuit structure of the hybrid two-tailed dynamic latch comparator, the voltage difference (VIO- (+)) between the intermediate backward output node IO-and the intermediate forward output node IO + is exponentially increased, and the regeneration time is shorter than that of the conventional dynamic latch comparator. Although the idea proposed by the present application is successful, it is considered that one point of the load NMOS transistors, i.e., the dc path of the external power supply VDD to the ground GND through the third NMOS transistor and the fourth NMOS transistor at the input and tail of the thirteenth PMOS transistor, thereby causing static power consumption. To solve this problem, two switching PMOS transistors (M)_SW1And M_SW2) The circuit structure of the hybrid double-tail dynamic latching comparator is provided, and is shown in figure 3.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.