阅读说明：本技术 模拟开关多路复用器系统及相关方法 (Analog switch multiplexer system and related method ) 是由 田木幸之助 于 2020-09-29 设计创作，主要内容包括：本发明题为“模拟开关多路复用器系统及相关方法”。本发明公开了一种马达控制器系统,该马达控制器系统包括模拟开关多路复用器系统。具体实施方式包括多个场效应晶体管(FET),该多个FET可被配置为与马达的一个或多个相可操作地耦合。该多个FET中的每一个FET可包括：栅极；模拟开关多路复用器,该模拟开关多路复用器与多个FET的栅极中的每一个栅极耦合并与模拟输出耦合；以及数字控制块,该数字控制块与模拟开关多路复用器耦合并可被配置为响应于接收到串行外围接口信号而向模拟开关多路复用器发送多路复用器选择控制信号。(The invention provides an analog switch multiplexer system and related method. A motor controller system includes an analog switch multiplexer system. Particular embodiments include a plurality of Field Effect Transistors (FETs) that may be configured to be operably coupled with one or more of the motors. Each of the plurality of FETs may include: a gate electrode; an analog switch multiplexer coupled to each of the gates of the plurality of FETs and to the analog output; and a digital control block coupled with the analog switch multiplexer and configurable to send a multiplexer select control signal to the analog switch multiplexer in response to receiving the serial peripheral interface signal.)

1. A motor controller system comprising:

a plurality of Field Effect Transistors (FETs) configured to be operably coupled with one or more phases of a motor, each FET of the plurality of FETs comprising a gate;

an analog switch multiplexer coupled with each of the gates of the plurality of FETs and with an analog output; and

a digital control block coupled with the analog switching multiplexer and configured to send a multiplexer select control signal to the analog switching multiplexer in response to receiving a serial peripheral interface signal.

2. The system of claim 1, wherein a voltage at an analog output pin coupled with the analog switch multiplexer is equal to a gate voltage of one of the plurality of FETs.

3. The system of claim 1, wherein a voltage at an analog output pin coupled with the analog switch multiplexer is substantially equal to a drain breakdown voltage of an NMOS transistor or a PMOS transistor included in the analog switch multiplexer.

4. An analog switch-multiplexer system comprising:

a first PMOS transistor coupled with a first diode, the first diode pointing inward;

a second PMOS transistor coupled with a second diode, the second PMOS transistor and the second diode coupled in series with the first PMOS transistor and the first diode, the second diode pointing inward;

a first NMOS transistor coupled with a third diode, the third diode pointing outward; and

a second NMOS transistor coupled with a fourth diode, the second NMOS transistor and the fourth diode coupled in series with the first NMOS transistor and the third diode, the fourth diode pointing outward;

wherein the first PMOS transistor and the second PMOS transistor are coupled in parallel with the first NMOS transistor and the second NMOS transistor.

5. The system of claim 4, further comprising a third NMOS transistor comprising a gate coupled with a digital control block and coupled with a gate of the first NMOS transistor and a gate of the second NMOS transistor.

6. The system of claim 4, further comprising a first current source coupled with a fifth diode, the fifth diode coupled with a third NMOS transistor, the first current source coupled with a resistor, the resistor coupled with a fourth NMOS transistor, the fourth NMOS transistor coupled with a sixth diode, the sixth diode coupled to a gate control voltage input.

7. A method of operating an analog switch-multiplexer circuit, the method comprising:

applying, using a digital control block, a turn-on voltage to a gate of an NMOS transistor coupled to a diode and a current source;

turning on two NMOS transistors coupled in parallel with the turn-on voltage in response to receiving the turn-on voltage at the two NMOS transistors, the two NMOS transistors coupled in parallel with a first PMOS transistor and a second PMOS transistor;

turning on the first and second PMOS transistors; and

transmitting an analog gate voltage of a Field Effect Transistor (FET) from a first pin to a second pin through a channel of the first PMOS transistor and a channel of the second PMOS transistor when the first PMOS transistor and the second PMOS transistor are turned on;

wherein the analog gate voltage is at an operating voltage of the FET and greater than 3.6 volts.

8. The method of claim 7, wherein the gate control voltage flows to ground through the fourth NMOS transistor, the resistor, and the first current source.

9. The method of claim 7, further comprising transmitting the analog gate voltage to one of the first pin or the second pin in response to applying a voltage to one of the second pin or the first pin, respectively.

10. The method of claim 7, further comprising sequentially transmitting the analog gate voltage of each FET in response to receiving a sequence signal from the digital control block using an analog switching multiplexer.

Technical Field

Aspects of this document relate generally to switching circuits.

Background

The analog switch circuit operates by switching or routing signals based on digital control signals. The analog switch acts as a solid state relay that can conduct both analog and digital signals when turned on.

Disclosure of Invention

An embodiment of a motor controller system may include: a plurality of Field Effect Transistors (FETs) that may be configured to be operably coupled with one or more of the motors. Each of the plurality of FETs may include: a gate electrode; an analog switch multiplexer coupled to each of the gates of the plurality of FETs and to the analog output; and a digital control block coupled with the analog switch multiplexer and configurable to send a multiplexer select control signal to the analog switch multiplexer in response to receiving the serial peripheral interface signal.

An embodiment of a motor controller system may comprise one, all or any of the following:

may include a pin configured to operably couple with the serial peripheral interface.

An analog output pin may be included that is operatively coupled to the analog switch multiplexer.

The voltage at the analog output pin may be equal to a gate voltage of one of the plurality of FETs.

The voltage at the analog output pin may be substantially equal to a drain breakdown voltage of an NMOS transistor or a PMOS transistor included in the analog switch multiplexer.

An embodiment of an analog switch-multiplexer system may include: a first PMOS transistor coupled with a first diode, the first diode pointing inward; a second PMOS transistor coupled with a second diode, the second PMOS transistor and the second diode coupled in series with the first PMOS transistor and the first diode, the second diode pointing inward; a first NMOS transistor coupled to a third diode, the third diode pointing to the outside; and a second NMOS transistor coupled with a fourth diode, the second NMOS transistor and the fourth diode coupled in series with the first NMOS transistor and the third diode, the fourth diode pointing inward. In various embodiments, the first PMOS transistor and the second PMOS transistor may be coupled in parallel with the first NMOS transistor and the second NMOS transistor.

An implementation of an analog switch-multiplexer system may include one, all, or any of the following:

the first pin may be coupled to a first PMOS transistor and a second NMOS transistor.

The first resistor may be coupled between the first pin and the first PMOS transistor.

The second pin may be coupled to a second PMOS transistor and a second NMOS transistor.

The second resistor may be coupled between the second pin and the second PMOS transistor.

The third NMOS transistor may include a gate coupled to the digital control block and to the gates of the first and second NMOS transistors.

The first current source may be coupled with a fifth diode coupled with a third NMOS transistor, the first current source coupled with a resistor coupled with a fourth NMOS transistor coupled with a sixth diode coupled to the gate control voltage input.

The second current source may be coupled in parallel with the gate of the fourth NMOS transistor and coupled with the resistor.

A gate of the fourth NMOS transistor may be coupled between the first PMOS transistor, the second PMOS transistor, and the first diode and the second diode.

An embodiment of a method of operating an analog switch-multiplexer circuit may include: using a digital control block, a turn-on voltage is applied to the gate of an NMOS transistor coupled to a diode and a current source. In response to receiving the turn-on voltage at two NMOS transistors coupled in parallel with the turn-on voltage, the method may include turning on two NMOS transistors coupled in parallel with the first PMOS transistor and the second PMOS transistor. The method may also include turning on the first PMOS transistor and the second PMOS transistor. When the first PMOS transistor and the second PMOS transistor are on, the method may include transmitting an analog gate voltage of a Field Effect Transistor (FET) from the first pin to the second pin through a channel of the first PMOS transistor and a channel of the second PMOS transistor. The analog gate voltage may be at an operating voltage of the FET and greater than 3.6 volts.

An embodiment of a method of operating an analog switch-multiplexer circuit may comprise one, all or any of the following:

the method may include applying a turn-off voltage to a gate of an NMOS transistor coupled to a diode and a current source using a digital control block.

The method may include applying the turn-off voltage may further include turning off current from the current source and closing the NMOS transistor and turning off each gate of the PMOS transistor.

The gate control voltage may flow to ground through the fourth NMOS transistor, the resistor, and the first current source.

The method may include transmitting an analog gate voltage to one of the first pin or the second pin in response to applying a voltage to one of the second pin or the first pin, respectively.

The method may include sequentially transmitting the analog gate voltage of each FET in response to receiving a sequence signal from the digital control block using an analog switching multiplexer.

The above and other aspects, features and advantages will be apparent to one of ordinary skill in the art from the specification and drawings, and from the claims.

Drawings

Embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and:

FIG. 1 illustrates an embodiment of an analog switching system;

FIG. 2 illustrates an embodiment of an analog switch multiplexer system;

FIG. 3 illustrates an embodiment of a motor controller system; and is

Fig. 4 illustrates an embodiment of a motor controller system including an embodiment of an analog switch-multiplexer system.

Detailed Description

The present disclosure, aspects, and embodiments thereof, are not limited to the specific components, assembly processes, or method elements disclosed herein. It will be apparent that many additional components, assembly procedures, and/or method elements known in the art consistent with the contemplated analog switch system are used with the embodiments of the present disclosure. Thus, for example, although specific embodiments are disclosed, such embodiments and implementation components may include any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, etc. known in the art for such analog switch systems and implementation components and methods consistent with the intended operation and method.

Referring to fig. 1, an embodiment of an analog switching system is shown. As shown, two PMOS transistors 6 are coupled in parallel with two NMOS transistors 8. As shown, the first PMOS transistor is coupled in series with the second PMOS transistor, and the first NMOS transistor is coupled in series with the second NMOS transistor. As shown, PMOS transistor 6 and NMOS transistor 8 are each individually coupled with diode 4. In this analog switching system, each diode 4 points outwards, or in other words, the diode 4 coupled to the first PMOS transistor points/biases/orients in the opposite direction to the diode 4 coupled to the second PMOS transistor. As shown, the transistors each include gates 2 that are electrically coupled together for PMOS transistor 6 and electrically coupled together for NMOS transistor 8. Because the gates 2 are conductive together, an analog input signal (shown as an analog signal in the range of 0V to 3.3V) when applied to the input only switches the analog switching system if the input signal does not exceed the gate breakdown voltage (3.3V in this case). This is because the externally directed diode 4 causes all current to flow through the channel of the NMOS or PMOS transistor (depending on which state the analog switch circuit is in, and the only control of the current is via the gate voltage). If the gate voltage is exceeded, damage to the NMOS and/or PMOS transistors will result, causing the analog switching system to become inoperable.

Due to this behavior of the switching system, the analog input signal to the system cannot exceed the gate breakdown voltage for an analog switching system similar to that shown in fig. 1. Because the gate breakdown voltages of NMOS and PMOS transistors are typically no greater than 3V to 3.3V, when implementing an analog switch design similar to that shown in fig. 1 for analog signals exceeding 3.3V, various voltage regulation circuits must be employed to reduce the voltage to no more than the gate breakdown voltage. This generally increases the complexity of the resulting circuit, making it more difficult to implement an analog switching system design similar to that shown in fig. 1 in higher voltage analog circuit applications.

Referring to fig. 2, another embodiment of an analog switch-multiplexer system is shown. As shown, a first PMOS transistor 10 is coupled with a first diode 12 pointing inwards. As shown, the second PMOS transistor 14 is coupled with a second diode 16, which also points inward toward the diode 12. In various embodiments, a second PMOS transistor 14 and a second diode 16 are coupled in series with the first PMOS transistor 10 and the first diode 12. As shown, the first NMOS transistor 18 is coupled with a third diode 20, which is directed outwards. As shown, the second NMOS transistor 22 is coupled with a fourth diode 24 that also points outward or away from the third diode 20. As shown, a second NMOS transistor 22 and a fourth diode 24 are coupled in series with the first NMOS transistor 18 and the third diode 20. The internal orientation of the first diode 12 and the second diode 16 is in contrast to the arrangement in the analog switching system embodiment of fig. 1, in which the corresponding diodes are directed inward. As shown, the first and second PMOS transistors 10 and 14 are coupled in parallel with the first and second NMOS transistors 18 and 22.

Still referring to fig. 2, a first pin 26 is coupled to the first PMOS transistor 10 and the second NMOS transistor 22 for analog signal input or output to the transistors. As shown, a first resistor 28 is coupled between the first pin 26 and the first PMOS transistor 10 for protecting these devices from ESD stress. As shown, a second pin 30 and a corresponding second resistor 32 are coupled to the second PMOS transistor 14 and the second NMOS transistor 22, also serving as analog signal inputs or outputs for the transistors. In various embodiments, the second PMOS transistor 14 includes a gate C, and the first PMOS transistor 10 includes a gate B.

As shown, the third NMOS transistor 34 includes a gate 36 coupled to a digital control block 38 and to a gate 40 of the first NMOS transistor 18 and a gate 42 of the second NMOS transistor 22. As shown, the first current source 44 is coupled to a fifth diode 46, which is coupled to the third NMOS transistor 34. As shown, the first current source 44 is also coupled to a resistor (R) 48. Resistor 48 is coupled in series with a fourth NMOS transistor 50 that is coupled with a sixth diode 52 that is coupled in parallel with a gate control voltage input 54. As shown, a second current source (I2)56 is diode connected to the gate 58 of the fourth NMOS transistor 50 and is also coupled to the resistor 48. In various embodiments, the gate 58 of the fourth NMOS transistor 50 is coupled to a node a between the first PMOS transistor 10, the second PMOS transistor 14, and the first diode 12 and the second diode 16.

Will have a voltage V during operation of the analog switching system_aIs applied to the first pin 26 or the second pin 30 and a corresponding switch output (on or off) is provided at the second pin 30 or the first pin 26, respectively, by the analog switching system. At this time, the voltage at the node A is V_a-V_F(analog input voltage-forward voltage). The forward voltage is applied using a diode 12. When the control system desires to activate the switch and transfer the analog input/feed signal from the first pin 26 to the second pin 30 (or vice versa), the digital control block 38 is used to apply a turn-on voltage to the gate 36 of the third NMOS transistor 34, thereby causing current to flow from the current source I1(44) through the third NMOS transistor 36 to ground. Meanwhile, since the node a is connected to the gate of the NMOS transistor source follower, the voltage V at the node a_thR × I1 is applied to the gates of the first PMOS transistor 10 and the second PMOS transistor 14, turning on the PMOS transistors. In other words, a forward diode 12, NMOS transistor source is usedThe pole follower and the voltage drop caused by the constant current source I1 and the resistor R generate a gate voltage of the first PMO transistor responsive to the analog input signal. In the foregoing equation, V_thIs the voltage associated with the fourth NMOS transistor 50. In such embodiments, when the first PMOS transistor 10 and the second PMOS transistor 14 are turned on, current from the first pin 26 to the second pin 30 (or vice versa) is transmitted through the channel of the first PMOS transistor 10 and the channel of the second PMOS transistor 14.

Because gates 40 and 42 are coupled in parallel with gate 36, the turn-on voltage from digital control block 38 is applied to gates 40 and 42 simultaneously, also switching both NMOS transistors 18 and 22 on, thus allowing current to flow from pin 26 to pin 30 (or vice versa) through the channels of NMOS transistors 18 and 22, as directed by outwardly directed fourth diode 24 and third diode 20. This turns on the switching system, allowing the analog input signal to pass directly through the transistor channel (source to drain) rather than being applied to the gate of the transistor. This movement of the signal through the channel allows the voltage of the analog input signal to be as high as the drain breakdown voltage (not just the gate breakdown voltage) of the NMOS and PMOS transistors themselves. Since the drain breakdown voltages of the NMOS and PMOS transistors can be much higher than 3.3V (40V or higher), the analog switching system no longer requires any voltage dropping circuit to prevent the transistors from being damaged at various voltages up to the drain breakdown voltage.

To stop the flow of the analog signal from the first pin 26 to the second pin 30 (or vice versa) when the analog switching system is to be turned off, a digital control block 38 may be used to apply a turn-off voltage to the gate 36 of the third NMOS transistor 34. In such embodiments, the turn-off voltage is applied when digital control block 38 reduces the voltage applied at gate 36 to the low voltage of third NMOS transistor 34. This simultaneously changes the gate voltages applied to the gates 42 and 40, thereby turning off the second NMOS transistor 22 and the first NMOS transistor 20. Then, the gate voltages at B and C of the first PMOS transistor 10 and the second PMOS transistor 14 are forced to become V_GC-R × I2. This forces both the first PMOS transistor 10 and the second PMOS transistorThe source of the tube 14 becomes V_GC-V_F. Since the voltage R I2 is less than V_FThe PMOS transistor is then turned off and prevents any further analog signal from flowing.

This ability to switch the PMOS and NMOS transistors on in response to a signal from digital control block 38 to pass an analog signal from the first pin to the second pin and from the second pin to the first pin allows the analog switching system to function as an analog switching multiplexer. Where the analog switching system is coupled to two or more Field Effect Transistors (FETs), the system may be used to sequentially transmit the analog gate voltage of each FET in response to receiving a sequence signal from digital control block 38.

Referring to fig. 3, an embodiment of a motor controller system is shown. As shown, a plurality of Field Effect Transistors (FETs) 60 (each represented by 3 in each group) are coupled to one or more phases 64, 66, and 68 of a motor 65. In various embodiments, the phases include a W-phase 64, a V-phase 66, and a U-phase 68. As shown, each of the plurality of FETs 60 includes a gate 62. As shown, the system also includes a pad or output 70 from the Integrated Circuit (IC) and a corresponding board output or pin 72. In this system, the controller cannot pass the voltage at the gate 62 during operation of the system because there is no separate path for passing the gate voltage out of the semiconductor package via the controller.

Referring to fig. 4, an embodiment of a motor controller system including an analog switch-multiplexer system embodiment similar to that disclosed herein is shown. The use of an analog switch-multiplexer system allows the FET gate voltage to be transmitted using a single analog output pin AOUT during operation of the system. As shown, a plurality of Field Effect Transistors (FETs) 74 (six in total) are each coupled to one or more phases 76, 78, and 80 of a motor 82. In various embodiments, the phases may include a W-phase 80, a V-phase 78, and a U-phase 76. As shown, each of the plurality of FETs 74 includes a gate 84. As shown, an analog switch-multiplexer system 86 is coupled to each of the gates 84 of the plurality of FETs 74 and to an analog output AOUT 88. As shown, a digital control block 90 is coupled to the analog switch multiplexer 86. In various embodiments, the digital control block 90 is configured to send one or more multiplexer select control signals 92 to the analog switch multiplexer 86 in response to receiving a signal from a serial peripheral interface 94 (SPI). The signals from the SPIs are designed to cause the digital control block 90 to send sequential multiplexer control signals to cycle the output from the AOUT through each gate voltage of the plurality of FETs 60, or in particular embodiments, may cause the digital control block 90 to send specific multiplexer control signals to transmit specific gate voltages from the plurality of FETs 60 to the AOUT pin. In various embodiments, at least the analog switch multiplexer and the digital control block are contained within a motor controller or motor driver.

Still referring to fig. 4, in various embodiments, the pins or pads may be configured to be operatively coupled with the serial peripheral interface 94. In various other embodiments, analog output 88 or analog output pins or pads may be operatively coupled to analog switch multiplexer 86. In such embodiments, when the analog switch multiplexer 86 is on and transmits the analog gate voltage of the FET to the analog output, the voltage at the analog output pin 88 is equal to the gate voltage of one FET 74. In the case where the analog gate voltage is higher than 3.3V, the system may be designed such that the voltage at the analog output pin 88 is substantially equal to or less than the drain breakdown voltage of an NMOS transistor or a PMOS transistor included in the analog switch multiplexer 86.

By way of non-limiting example, the solid-state analog switches and multiplexers disclosed herein may be used in a variety of applications, including multi-channel data acquisition systems, process control, instrumentation, video systems, and any other system that requires switching between various analog control signals of different voltages. In various embodiments, the analog switching system is controlled by an N-channel (NMOS) device that is turned on for positive gate-source voltages and turned off for negative gate-source voltages, while a P-channel device (PMOS) is switched by a complementary signal so that the PMOS device is turned on accordingly at the same time as the N-channel device. In a specific embodiment, the analog switching system is turned on and off by driving the gates to opposite supply voltage rails.

Whenever the analog switch input voltage exceeds the supply voltage, the internal ESD protection diode becomes forward biased, allowing a larger current to flow even if the supply voltage is turned off (which may result in exceeding the voltage rating). The disclosed analog switch systems and methods allow the analog switch input voltage to not exceed the drain breakdown voltage, which may prevent such damage to the system. In various system embodiments, the analog switch system may be implemented in a multi-chip package similar to an Integrated Power Module (IPM). When included in an IPM, testing (routing of signals to another pin output via the interior of the package) can be performed even if the AOUT pin is not the actual output of the actual package. In various IPM implementations in which FETs are used as drivers for the motor, the analog switching system may also be used to measure the leakage current of each FET by coupling to the drain side of each FET instead of or in addition to the gate of the FET.

The system components disclosed herein may be made from a variety of materials, such as silicon, silicon dioxide, tantalum, palladium, semiconductor materials, metals, plastics, alloys, composites, and the like.

In various method embodiments, the method may include applying a turn-off voltage to a gate of an NMOS transistor coupled to a diode and a current source using a digital control block.

In various method embodiments, applying the turn-off voltage may further include turning off current from the current source and closing each gate of the NMOS transistor and turning off the PMOS transistor.

In various system embodiments, the system may include a pin configured to operably couple with a serial peripheral interface.

In various system embodiments, the system may further include an analog output pin operably coupled to the analog switch multiplexer.

In various system embodiments, the system may include a first pin coupled to a first PMOS transistor and a second NMOS transistor.

In various system embodiments, the system may include a first resistor coupled to a second PMOS transistor and a second NMOS transistor.

In various system embodiments, the system may include a second pin coupled to a second PMOS transistor and a second NMOS transistor.

In various system embodiments, the system may include a second resistor coupled between the second pin and the second PMOS transistor.

In various system embodiments, the system may include a second current source coupled in parallel with the gate of the fourth NMOS transistor and coupled with the resistor.

In various system embodiments, the gate of the fourth NMOS transistor may be coupled between the first PMOS transistor, the second PMOS transistor, and the first diode and the second diode.

Where the above description refers to particular embodiments of analog switch systems and implementing components, subcomponents, methods and submethods, it should be apparent that various modifications can be made without departing from the spirit thereof and that the embodiments, implementing components, subcomponents, methods and submethods can be applied to other analog switch systems.