CN112653438A - 模拟开关多路复用器系统及相关方法 - Google Patents
模拟开关多路复用器系统及相关方法 Download PDFInfo
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- CN112653438A CN112653438A CN202011048299.XA CN202011048299A CN112653438A CN 112653438 A CN112653438 A CN 112653438A CN 202011048299 A CN202011048299 A CN 202011048299A CN 112653438 A CN112653438 A CN 112653438A
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- 238000000034 method Methods 0.000 description 2
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- 239000010703 silicon Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum Chemical compound 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[Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
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- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
Abstract
本发明题为“模拟开关多路复用器系统及相关方法”。本发明公开了一种马达控制器系统,该马达控制器系统包括模拟开关多路复用器系统。具体实施方式包括多个场效应晶体管(FET),该多个FET可被配置为与马达的一个或多个相可操作地耦合。该多个FET中的每一个FET可包括:栅极;模拟开关多路复用器,该模拟开关多路复用器与多个FET的栅极中的每一个栅极耦合并与模拟输出耦合;以及数字控制块,该数字控制块与模拟开关多路复用器耦合并可被配置为响应于接收到串行外围接口信号而向模拟开关多路复用器发送多路复用器选择控制信号。
Description
相关专利申请的交叉引用
本申请要求授予Konosuke Taki的名称为“ANALOG SWITCH MULTIPLEXER SYSTEMSAND RELATED METHODS”的美国临时专利申请62/912,758的提交日期的权益,该临时专利申请提交于2019年10月9日,其公开内容据此全文以引用方式并入本文。
技术领域
本文档的各方面整体涉及开关电路。
背景技术
模拟开关电路通过基于数字控制信号切换或路由信号来操作。模拟开关充当固态继电器,该固态继电器在接通时可以传导模拟信号和数字信号两者。
发明内容
一种马达控制器系统的实施方式可包括:多个场效应晶体管(FET),多个FET可被配置为与马达的一个或多个相可操作地耦合。该多个FET中的每一个FET可包括:栅极;模拟开关多路复用器,该模拟开关多路复用器与多个FET的栅极中的每一个栅极耦合并与模拟输出耦合;以及数字控制块,该数字控制块与模拟开关多路复用器耦合并可被配置为响应于接收到串行外围接口信号而向模拟开关多路复用器发送多路复用器选择控制信号。
一种马达控制器系统的实施方式可包括以下各项中的一者、全部或任一者:
可包括引脚,该引脚被配置为与串行外围接口可操作地耦合。
可包括模拟输出引脚,该模拟输出引脚可操作地耦合到模拟开关多路复用器。
该模拟输出引脚处的电压可等于多个FET中的一个FET的栅极电压。
模拟输出引脚处的电压可基本上等于包括在模拟开关多路复用器中的NMOS晶体管或PMOS晶体管的漏极击穿电压。
一种模拟开关多路复用器系统的实施方式可包括:与第一二极管耦合的第一PMOS晶体管,该第一二极管指向内部;与第二二极管耦合的第二PMOS晶体管,该第二PMOS晶体管和该第二二极管与该第一PMOS晶体管和该第一二极管串联耦合,该第二二极管指向内部;与第三二极管耦合的第一NMOS晶体管,该第三二极管指向外部;以及与第四二极管耦合的第二NMOS晶体管,该第二NMOS晶体管和该第四二极管与该第一NMOS晶体管和该第三二极管串联耦合,该第四二极管指向内部。在各种实施方式中,第一PMOS晶体管和第二PMOS晶体管可与第一NMOS晶体管和第二NMOS晶体管并联耦合。
一种模拟开关多路复用器系统的实施方式可包括以下各项中的一者、全部或任一者:
第一引脚可耦合到第一PMOS晶体管和第二NMOS晶体管。
第一电阻器可耦合在第一引脚和第一PMOS晶体管之间。
第二引脚可耦合到第二PMOS晶体管和第二NMOS晶体管。
第二电阻器可耦合在第二引脚和第二PMOS晶体管之间。
第三NMOS晶体管可包括栅极,该栅极与数字控制块耦合并与第一NMOS晶体管的栅极和第二NMOS晶体管的栅极耦合。
第一电流源可与第五二极管耦合,该第五二极管与第三NMOS晶体管耦合,第一电流源与电阻器耦合,该电阻器与第四NMOS晶体管耦合,该第四NMOS晶体管与第六二极管耦合,该第六二极管耦合到栅极控制电压输入。
第二电流源可与第四NMOS晶体管的栅极并联耦合并与电阻器耦合。
第四NMOS晶体管的栅极可耦合在第一PMOS晶体管、第二PMOS晶体管以及第一二极管和第二二极管之间。
一种操作模拟开关多路复用器电路的方法的实施方式可包括:使用数字控制块,将接通电压施加到与二极管和电流源耦合的NMOS晶体管的栅极。响应于在与接通电压并联耦合的两个NMOS晶体管处接收到接通电压,方法可包括接通两个NMOS晶体管,该两个NMOS晶体管与第一PMOS晶体管和第二PMOS晶体管并联耦合。方法还可包括接通第一PMOS晶体管和第二PMOS晶体管。当第一PMOS晶体管和第二PMOS晶体管接通时,方法可包括将场效应晶体管(FET)的模拟栅极电压通过第一PMOS晶体管的沟道和第二PMOS晶体管的沟道从第一引脚传输到第二引脚。模拟栅极电压可处于FET的操作电压并且大于3.6伏。
一种操作模拟开关多路复用器电路的方法的实施方式可包括以下各项中的一者、全部或任一者:
方法可包括使用数字控制块,将断开电压施加到与二极管和电流源耦合的NMOS晶体管的栅极。
方法可包括施加断开电压还可包括关断来自电流源的电流并闭合NMOS晶体管以及关断PMOS晶体管的每个栅极。
栅极控制电压可通过第四NMOS晶体管、电阻器和第一电流源流到接地。
方法可包括响应于将电压分别施加到第二引脚或第一引脚中的一者而将模拟栅极电压传输到第一引脚或第二引脚中的一者。
方法可包括使用模拟开关多路复用器,响应于从数字控制块接收到顺序信号而顺序地传输每个FET的模拟栅极电压。
对于本领域的普通技术人员而言,通过说明书和附图并且通过权利要求书,上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述实施方式,在附图中类似标号表示类似元件,并且:
图1示出了模拟开关系统的实施方式;
图2示出了模拟开关多路复用器系统的实施方式;
图3示出了马达控制器系统的实施方式;并且
图4示出了包括模拟开关多路复用器系统实施方式的马达控制器系统的实施方式。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法要素。符合预期模拟开关系统的本领域已知的许多附加部件、组装工序和/或方法元素与本公开的具体实施方式一起使用将显而易见。因此,例如,尽管公开了具体实施方式,但是此类实施方式和实施部件可包括符合预期操作和方法的本领域已知的用于此类模拟开关系统以及实施部件和方法的任何形状、尺寸、样式、类型、型号、版本、量度、浓度、材料、数量、方法元素、步骤等。
参见图1,示出了模拟开关系统的实施方式。如图所示,两个PMOS晶体管6与两个NMOS晶体管8并联耦合。如图所示,第一PMOS晶体管与第二PMOS晶体管串联耦合,并且第一NMOS晶体管与第二NMOS晶体管串联耦合。如图所示,PMOS晶体管6和NMOS晶体管8各自单独地与二极管4耦合。在该模拟开关系统中,每个二极管4指向外部,或者换句话讲,耦合到第一PMOS晶体管的二极管4在与耦合到第二PMOS晶体管的二极管4相反的方向上指向/偏置/取向。如图所示,晶体管各自包括栅极2,该栅极对于PMOS晶体管6电耦合在一起并且对于NMOS晶体管8电耦合在一起。因为栅极2在一起导电,所以模拟输入信号(被示出为在0V至3.3V范围内的模拟信号)在被施加到输入时仅在输入信号不超过栅极击穿电压(在这种情况下为3.3V)的情况下使模拟开关系统切换。这是因为指向外部的二极管4使所有电流都流过NMOS或PMOS晶体管的沟道(取决于模拟开关电路处于哪种状态,并且对电流的唯一控制是经由栅极电压)。如果超过栅极电压,则将导致NMOS和/或PMOS晶体管损坏,从而导致模拟开关系统变得不可操作。
由于开关系统的这种行为,对于类似于图1所示的模拟开关系统,到系统的模拟输入信号不能超过栅极击穿电压。因为NMOS和PMOS晶体管的栅极击穿电压通常不大于3V至3.3V,所以当针对超过3.3V的模拟信号实施类似于图1所示的模拟开关设计时,必须采用各种电压调节电路来将电压降低至不超过栅极击穿电压。这通常会增加所得电路的复杂性,使得更难在较高电压模拟电路应用中实施类似于图1所示的模拟开关系统设计。
参见图2,示出了模拟开关多路复用器系统的另一种实施方式。如图所示,第一PMOS晶体管10与指向内部的第一二极管12耦合。如图所示,第二PMOS晶体管14与朝向二极管12也指向内部的第二二极管16耦合。在各种实施方式中,第二PMOS晶体管14和第二二极管16与第一PMOS晶体管10和第一二极管12串联耦合。如图所示,第一NMOS晶体管18与指向外部的第三二极管20耦合。如图所示,第二NMOS晶体管22与也指向外部或远离第三二极管20的第四二极管24耦合。如图所示,第二NMOS晶体管22和第四二极管24与第一NMOS晶体管18和第三二极管20串联耦合。第一二极管12和第二二极管16的内部指向与图1的模拟开关系统实施方式(其中对应的二极管向内指向)中的布置形成对比。如图所示,第一PMOS晶体管10和第二PMOS晶体管14与第一NMOS晶体管18和第二NMOS晶体管22并联耦合。
仍然参见图2,第一引脚26耦合到第一PMOS晶体管10和第二NMOS晶体管22,用作对晶体管的模拟信号输入或输出。如图所示,第一电阻器28耦合在第一引脚26和第一PMOS晶体管10之间,用于保护这些器件免受ESD应力。如图所示,第二引脚30和对应的第二电阻器32耦合到第二PMOS晶体管14和第二NMOS晶体管22,也用作晶体管的模拟信号输入或输出。在各种实施方式中,第二PMOS晶体管14包括栅极C,并且第一PMOS晶体管10包括栅极B。
如图所示,第三NMOS晶体管34包括栅极36,该栅极与数字控制块38耦合并与第一NMOS晶体管18的栅极40和第二NMOS晶体管22的栅极42耦合。如图所示,第一电流源44与第五二极管46耦合,该第五二极管与第三NMOS晶体管34耦合。如图所示,第一电流源44还与电阻器(R)48耦合。电阻器48与第四NMOS晶体管50串联耦合,该第四NMOS晶体管与第六二极管52耦合,该第六二极管与栅极控制电压输入54并联耦合。如图所示,第二电流源(I2)56与二极管连接到第四NMOS晶体管50的栅极58并且还与电阻器48耦合。在各种实施方式中,第四NMOS晶体管50的栅极58耦合到位于第一PMOS晶体管10、第二PMOS晶体管14以及第一二极管12和第二二极管16之间的节点A。
在模拟开关系统的操作期间,将具有电压Va的模拟输入/馈电信号施加到第一引脚26或第二引脚30,并且由模拟开关系统分别在第二引脚30或第一引脚26处提供对应的开关输出(接通或断开)。此时,节点A处的电压为Va-VF(模拟输入电压-正向电压)之间的差值。正向电压是使用二极管12施加的。当控制系统期望激活开关并将模拟输入/馈电信号从第一引脚26转移到第二引脚30(或反之亦然)时,数字控制块38用于将接通电压施加到第三NMOS晶体管34的栅极36,从而使电流从电流源I1(44)流过第三NMOS晶体管36到接地。同时,由于节点A连接到NMOS晶体管源极跟随器的栅极,因此节点A处的电压Vth-R*I1被施加到第一PMOS晶体管10和第二PMOS晶体管14的栅极,从而接通PMOS晶体管。换句话说,使用正向二极管12、NMOS晶体管源极跟随器以及由恒定电流源I1和电阻器R引起的电压降来生成响应于模拟输入信号的第一PMO晶体管的栅极电压。在前述等式中,Vth是与第四NMOS晶体管50相关联的电压。在此类实施方式中,当第一PMOS晶体管10和第二PMOS晶体管14接通时,从第一引脚26到第二引脚30(或反之亦然)的电流通过第一PMOS晶体管10的沟道和第二PMOS晶体管14的沟道传输。
因为栅极40和42与栅极36并联耦合,所以来自数字控制块38的接通电压被同时施加到栅极40和42,也将两个NMOS晶体管18和22切换为接通,因此允许电流通过NMOS晶体管18和22的沟道从引脚26流到引脚30(或反之亦然),如由向外指向的第四二极管24和第三二极管20所指向的。这会接通开关系统,从而允许模拟输入信号直接通过晶体管沟道(源极到漏极)而不是被施加到晶体管的栅极。信号通过沟道的这种移动允许模拟输入信号的电压与NMOS晶体管和PMOS晶体管本身的漏极击穿电压(而不仅仅是栅极击穿电压)一样高。由于NMOS晶体管和PMOS晶体管的漏极击穿电压可以远高于3.3V(40V或更高),因此模拟开关系统不再需要任何降压电路来防止在高至漏极击穿电压的多种电压下损坏晶体管。
当要关闭模拟开关系统时,为了使模拟信号从第一引脚26到第二引脚30(或反之亦然)的流动停止,可使用数字控制块38将断开电压施加到第三NMOS晶体管34的栅极36。在此类实施方式中,当数字控制块38将施加在栅极36处的电压降低到第三NMOS晶体管34的低电压时,施加断开电压。这同时会改变施加到栅极42和40的栅极电压,从而关断第二NMOS晶体管22和第一NMOS晶体管20。然后,第一PMOS晶体管10和第二PMOS晶体管14的B和C处的栅极电压被迫变为VGC-R*I2。这同时会迫使第一PMOS晶体管10和第二PMOS晶体管14的源极变为VGC-VF。由于电压R*I2小于VF,因此PMOS晶体管随后关断并防止任何另外的模拟信号流动。
这种响应于来自数字控制块38的信号而将PMOS晶体管和NMOS晶体管切换为接通以将模拟信号从第一引脚传递到第二引脚并且将模拟信号从第二引脚传递到第一引脚的能力允许模拟开关系统用作模拟开关多路复用器。在模拟开关系统耦合到两个或更多个场效应晶体管(FET)的情况下,该系统可以用于响应于从数字控制块38接收到顺序信号而顺序地传输每个场效应晶体管(FET)的模拟栅极电压。
参见图3,示出了马达控制器系统的实施方式。如图所示,多个场效应晶体管(FET)60(每个以每组3个表示)与马达65的一个或多个相64、66和68耦合。在各种实施方式中,相包括W相64、V相66和U相68。如图所示,多个FET 60中的每一个FET包括栅极62。如图所示,该系统还包括来自集成电路(IC)的焊盘或输出70以及对应的板输出或引脚72。在该系统中,控制器不能在系统的操作期间传输栅极62处的电压,因为没有单独的路径用于经由控制器将栅极电压传输到半导体封装之外。
参见图4,示出了包括类似于本文所公开的模拟开关多路复用器系统实施方式的马达控制器系统的实施方式。使用模拟开关多路复用器系统允许在系统的操作期间使用单个模拟输出引脚AOUT传输FET栅极电压。如图所示,多个场效应晶体管(FET)74(总共六个)各自与马达82的一个或多个相76、78和80耦合。在各种实施方式中,相可包括W相80、V相78和U相76。如图所示,多个FET 74中的每一个FET包括栅极84。如图所示,模拟开关多路复用器系统86与多个FET 74的栅极84中的每一个栅极耦合并与模拟输出AOUT 88耦合。如图所示,数字控制块90与模拟开关多路复用器86耦合。在各种实施方式中,数字控制块90被配置为响应于从串行外围接口94(SPI)接收到信号而向模拟开关多路复用器86发送一个或多个多路复用器选择控制信号92。来自SPI的信号被设计成使数字控制块90发送顺序多路复用器控制信号以使来自AOUT的输出循环通过多个FET 60的每个栅极电压,或者在具体实施方式中可使数字控制块90发送特定多路复用器控制信号以将特定栅极电压从多个FET 60传输到AOUT引脚。在各种实施方式中,至少模拟开关多路复用器和数字控制块包含在马达控制器或马达驱动器内。
仍然参见图4,在各种实施方式中,引脚或焊盘可被配置为与串行外围接口94可操作地耦合。在各种其他实施方式中,模拟输出88或者模拟输出引脚或焊盘可以可操作地耦合到模拟开关多路复用器86。在此类实施方式中,当模拟开关多路复用器86接通并且将FET的模拟栅极电压传输到模拟输出时,模拟输出引脚88处的电压等于一个FET 74的栅极电压。在模拟栅极电压高于3.3V的情况下,该系统可以被设计成使模拟输出引脚88处的电压基本上等于或小于包括在模拟开关多路复用器86内的NMOS晶体管或PMOS晶体管的漏极击穿电压。
作为非限制性示例,本文所公开的固态模拟开关和多路复用器可用于多种应用中,包括多通道数据采集系统、过程控制、仪器、视频系统以及需要在不同电压的各种模拟控制信号之间进行切换的任何其他系统。在各种实施方式中,模拟开关系统由N沟道(NMOS)器件控制,该NMOS器件针对正的栅极-源极电压接通并且针对负的栅极-源极电压断开,而P沟道器件(PMOS)通过互补信号切换,因此PMOS器件与N沟道器件同时被相应地接通。在具体的实施方式中,通过将栅极驱动到相反的供电电压轨来接通和断开模拟开关系统。
每当模拟开关输入电压超过供电电压时,内部ESD保护二极管变为正向偏置,从而允许较大电流流动,即使供电电压被关断(这可能导致超过电压额定值)也是如此。所公开的模拟开关系统和方法允许模拟开关输入电压不超过漏极击穿电压,这可防止对系统造成这种损坏。在各种系统实施方式中,模拟开关系统可在类似于集成功率模块(IPM)的多芯片封装中实施。当包括在IPM中时,即使AOUT引脚不是实际封装的实际输出,也可以进行测试(经由封装内部到另一个引脚输出的信号路由)。在FET用作马达的驱动器的各种IPM实施方式中,模拟开关系统还可用于通过与每个FET的漏极侧而不是FET的栅极耦合或者除了与FET的栅极耦合之外还与每个FET的漏极侧耦合来测量每个FET的泄漏电流。
本文所公开的系统部件可由各种材料(诸如硅、二氧化硅、钽、钯、半导体材料、金属、塑料、合金、复合材料等)制成。
在各种方法实施方式中,该方法可包括使用数字控制块将断开电压施加到与二极管和电流源耦合的NMOS晶体管的栅极。
在各种方法实施方式中,施加断开电压还可包括关断来自电流源的电流并闭合NMOS晶体管以及关断PMOS晶体管的每个栅极。
在各种系统实施方式中,该系统可包括被配置为与串行外围接口可操作地耦合的引脚。
在各种系统实施方式中,该系统还可包括可操作地耦合到模拟开关多路复用器的模拟输出引脚。
在各种系统实施方式中,该系统可包括耦合到第一PMOS晶体管和第二NMOS晶体管的第一引脚。
在各种系统实施方式中,该系统可包括耦合到第二PMOS晶体管和第二NMOS晶体管的第一电阻器。
在各种系统实施方式中,该系统可包括耦合到第二PMOS晶体管和第二NMOS晶体管的第二引脚。
在各种系统实施方式中,该系统可包括耦合在第二引脚和第二PMOS晶体管之间的第二电阻器。
在各种系统实施方式中,该系统可包括与第四NMOS晶体管的栅极并联耦合并与电阻器耦合的第二电流源。
在各种系统实施方式中,第四NMOS晶体管的栅极可耦合在第一PMOS晶体管、第二PMOS晶体管以及第一二极管和第二二极管之间。
在以上描述提及模拟开关系统的具体实施方式以及实施部件、子部件、方法和子方法的地方,应当显而易见的是,可在不脱离其实质的情况下作出多种修改,并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他模拟开关系统。