阅读说明：本技术 一种芯片的封装结构及其制备方法 (Chip packaging structure and preparation method thereof ) 是由 张文斌 于 2020-12-22 设计创作，主要内容包括：本发明提供一种芯片的封装结构及其制备方法,方法包括：提供承载片；在所述承载片沿其厚度方向的第一表面形成金属盲孔；在所述承载片的所述第一表面形成第一钝化层,图形化所述第一钝化层以形成过孔；在所述图形化后的第一钝化层上形成金属凸块,所述金属凸块通过所述过孔与所述金属盲孔电连接,以制备得到封装结构。本发明通过在承载片上设计出金属盲孔、第一钝化层和金属凸块,金属凸块通过设置在第一钝化层上的过孔与金属盲孔电连接,可以使金属盲孔的厚度超过20μm,金属盲孔的厚度范围可以达到30μm～100μm,降低了对钝化层厚度的要求,使较薄的钝化层即可完全覆盖金属盲孔,从而防止因金属盲孔与上层金属发生短接而导致器件失效。(The invention provides a chip packaging structure and a preparation method thereof, wherein the method comprises the following steps: providing a bearing sheet; forming a metal blind hole on the first surface of the bearing sheet along the thickness direction of the bearing sheet; forming a first passivation layer on the first surface of the carrier sheet, and patterning the first passivation layer to form a via hole; and forming a metal bump on the patterned first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole so as to prepare the packaging structure. According to the invention, the metal blind hole, the first passivation layer and the metal bump are designed on the bearing sheet, and the metal bump is electrically connected with the metal blind hole through the via hole arranged on the first passivation layer, so that the thickness of the metal blind hole exceeds 20 μm, the thickness range of the metal blind hole can reach 30 μm-100 μm, the requirement on the thickness of the passivation layer is reduced, the thinner passivation layer can completely cover the metal blind hole, and the device failure caused by the short circuit of the metal blind hole and the upper layer metal is prevented.)

1. A preparation method of a chip packaging structure is characterized by comprising the following steps:

providing a bearing sheet;

forming a metal blind hole on the first surface of the bearing sheet along the thickness direction of the bearing sheet;

forming a first passivation layer on the first surface of the carrier sheet, and patterning the first passivation layer to form a via hole;

and forming a metal bump on the patterned first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole so as to prepare the packaging structure.

2. The method according to claim 1, wherein the number of the first passivation layers is multiple, and the forming of the metal bump on the patterned first passivation layer, the metal bump being electrically connected to the blind metal via through the via, comprises:

forming metal wiring lines on the rest first passivation layers except the first passivation layer on the topmost layer after patterning, wherein the metal wiring lines of each layer are electrically connected with the metal blind holes through the corresponding via holes;

and forming the metal bump on the patterned topmost first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole on the topmost first passivation layer and the metal wiring of each layer.

3. The method of claim 1 or 2, wherein the blind metal vias have a thickness in the range of 30 μm to 100 μm.

4. The method of claim 2, wherein a thickness of a lowermost first passivation layer of the plurality of first passivation layers is equal to or greater than 5 μ ι η.

5. The method of claim 4, wherein the thickness of the lowermost of the plurality of first passivation layers ranges from 5 μm to 20 μm.

6. The method according to claim 1 or 2, characterized in that the method further comprises:

forming a second passivation layer on the metal bump, and patterning the second passivation layer to form a second via hole corresponding to the metal bump;

and forming a solder ball in the second via hole.

7. A chip package structure, comprising:

the bearing piece is provided with a metal blind hole along the first surface of the bearing piece in the thickness direction;

the first passivation layer covers the metal blind hole, a through hole is formed in the first passivation layer, and the through hole corresponds to the metal blind hole;

the metal bump is arranged on the first passivation layer and is electrically connected with the metal blind hole through the through hole.

8. The package structure according to claim 7, wherein the number of layers of the first passivation layer is a plurality of layers;

metal wiring lines are arranged on the rest first passivation layers except the topmost first passivation layer, and the metal wiring lines are electrically connected with the metal blind holes through the corresponding through holes;

the metal bump is arranged on the first passivation layer on the topmost layer and is electrically connected with the metal blind hole through the via hole on the first passivation layer on the topmost layer and the metal wiring of each layer.

9. The package structure according to claim 8, wherein the thickness of the metal blind via is in a range of 30 μm to 100 μm; and/or the presence of a gas in the gas,

the thickness range of the first passivation layer at the bottommost layer in the multiple first passivation layers is 5-20 microns.

10. The package structure according to any one of claims 7 to 9, further comprising:

the second passivation layer covers the metal bump, and a second through hole corresponding to the metal bump is formed in the second passivation layer;

a solder ball disposed in the second via.

Technical Field

The invention belongs to the technical field of chip packaging, and particularly relates to a chip packaging structure and a preparation method thereof.

Background

With the diversification of electronic products, devices with various sizes are required, and the preparation of devices such as filters, transformers, capacitors, inductors and the like with micron-sized line widths is limited by the thickness of a passivation layer material, and the thickness of a lower metal layer cannot exceed 20 μm generally. When the thickness of the lower metal layer exceeds 20 μm, the passivation layer between the upper and lower metal layers cannot cover the lower metal layer, and short circuit occurs between the lower metal layer and the upper metal layer, thereby causing device performance failure.

Disclosure of Invention

The invention aims to at least solve one of the technical problems in the prior art and provides a chip packaging structure and a preparation method thereof.

In one aspect of the present invention, a method for manufacturing a chip package structure is provided, the method including:

providing a bearing sheet;

forming a metal blind hole on the first surface of the bearing sheet along the thickness direction of the bearing sheet;

forming a first passivation layer on the first surface of the carrier sheet, and patterning the first passivation layer to form a via hole;

and forming a metal bump on the patterned first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole so as to prepare the packaging structure.

In some optional embodiments, the number of layers of the first passivation layer is multiple, and the forming of the metal bump on the patterned first passivation layer, the metal bump being electrically connected to the blind metal via through the via, includes:

forming metal wiring lines on the rest first passivation layers except the first passivation layer on the topmost layer after patterning, wherein the metal wiring lines of each layer are electrically connected with the metal blind holes through the corresponding via holes;

and forming the metal bump on the patterned topmost first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole on the topmost first passivation layer and the metal wiring of each layer.

In some alternative embodiments, the thickness of the blind metal via is in the range of 30 μm to 100 μm.

In some optional embodiments, a thickness of a lowermost first passivation layer of the plurality of first passivation layers is equal to or greater than 5 μm.

In some optional embodiments, the lowermost first passivation layer of the plurality of first passivation layers has a thickness ranging from 5 μm to 20 μm.

In some optional embodiments, the method further comprises:

forming a second passivation layer on the metal bump, and patterning the second passivation layer to form a second via hole corresponding to the metal bump;

and forming a solder ball in the second via hole.

In another aspect of the present invention, a package structure of a chip is provided, the package structure including:

the bearing piece is provided with a metal blind hole along the first surface of the bearing piece in the thickness direction;

the first passivation layer covers the metal blind hole, a through hole is formed in the first passivation layer, and the through hole corresponds to the metal blind hole;

the metal bump is arranged on the first passivation layer and is electrically connected with the metal blind hole through the through hole.

In some alternative embodiments, the number of layers of the first passivation layer is multiple;

metal wiring lines are arranged on the rest first passivation layers except the topmost first passivation layer, and the metal wiring lines are electrically connected with the metal blind holes through the corresponding through holes;

the metal bump is arranged on the first passivation layer on the topmost layer and is electrically connected with the metal blind hole through the via hole on the first passivation layer on the topmost layer and the metal wiring of each layer.

In some alternative embodiments, the thickness of the blind metal via ranges from 30 μm to 100 μm; and/or the presence of a gas in the gas,

the thickness range of the first passivation layer at the bottommost layer in the multiple first passivation layers is 5-20 microns.

In some optional embodiments, the package structure further comprises:

the second passivation layer covers the metal bump, and a second through hole corresponding to the metal bump is formed in the second passivation layer;

a solder ball disposed in the second via.

The invention provides a chip packaging structure and a preparation method thereof, wherein the method comprises the following steps: providing a bearing sheet; forming a metal blind hole on the first surface of the bearing sheet along the thickness direction of the bearing sheet; forming a first passivation layer on the first surface of the carrier sheet, and patterning the first passivation layer to form a via hole; and forming a metal bump on the patterned first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole so as to prepare the packaging structure. According to the invention, the metal blind hole, the first passivation layer and the metal bump are designed on the bearing sheet, and the metal bump is electrically connected with the metal blind hole through the via hole arranged on the first passivation layer, so that the thickness of the metal blind hole exceeds 20 μm, the thickness range of the metal blind hole can reach 30 μm-100 μm, the requirement on the thickness of the passivation layer is reduced, the thinner passivation layer can completely cover the metal blind hole, and the device failure caused by the short circuit of the metal blind hole and the upper layer metal is prevented.

Drawings

Fig. 1 is a process flow diagram of a method for manufacturing a chip package structure according to an embodiment of the invention;

fig. 2 to fig. 8 are schematic flow charts illustrating a method for manufacturing a chip package structure according to another embodiment of the invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

In one aspect of the present invention, as shown in fig. 1, a method S100 for manufacturing a chip package structure is provided, where the method S100 includes:

and S110, providing a bearing sheet.

Illustratively, in conjunction with fig. 2, a carrier sheet 110 is provided, and the carrier sheet 110 includes a first surface 111 and a second surface 112 oppositely disposed along a thickness direction thereof. In this step, the carrier sheet 110 may be a flat plate made of materials such as silicon, glass, metal, and organic substrate, and those skilled in the art may select carrier sheets made of other materials according to actual needs, which is not limited in this embodiment.

And S120, forming a metal blind hole on the first surface of the bearing sheet along the thickness direction of the bearing sheet.

For example, in this step, as shown in fig. 2, blind holes may be formed on the first surface 111 of the carrier sheet 110 by etching or the like, and then the blind holes may be formed into the blind metal holes 120 by electroplating or chemical plating or the like. Of course, a person skilled in the art may also form a blind metal hole on the first surface of the carrier sheet along the thickness direction thereof in other ways, which is not limited in this embodiment.

In the step, the blind holes are firstly manufactured on the first surface of the bearing sheet, and then the blind holes are manufactured into the metal blind holes, so that the thickness range of the metal blind holes can reach 30-100 mu m, and the thinner passivation layer can completely cover the metal blind holes, thereby preventing the device from losing efficacy due to short circuit between the metal blind holes and the upper layer metal.

S130, forming a first passivation layer on the first surface of the bearing sheet, and patterning the first passivation layer to form a via hole.

Exemplarily, in this step, as shown in fig. 3, a first passivation layer 131 is formed on the first surface 111 of the carrier sheet 110. The process of forming the first passivation layer 131 in this step may be deposition, sputtering, or other processes, which is not limited in this embodiment. The first passivation layer 131 may be made of silicon dioxide, silicon nitride, or other materials, and those skilled in the art can select the materials according to actual needs, which is not limited in the embodiment. The first passivation layer 131 completely covers the metal blind via 120, and the thickness of the first passivation layer 131 may range from 5 μm to 20 μm, and those skilled in the art may also select the first passivation layer according to actual needs, which is not limited in this embodiment.

As shown in fig. 3, the first passivation layer 131 is patterned to form a via hole 131 a. Patterning the first passivation layer 131 may be performed in the following manner: first, a patterned first mask layer is formed on the first passivation layer 131, and then, the first passivation layer 131 is etched at a suitable position by using the first mask layer as a mask, so as to form a via hole 131 a. The material of the first mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the first passivation layer 131 may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, a person skilled in the art may also select other ways to pattern the first passivation layer 131 to form the via 131a, which is not limited by the embodiment.

And S140, forming a metal bump on the patterned first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole so as to prepare the packaging structure.

Preferably, the number of the first passivation layers is multiple.

For example, there may be only one first passivation layer, or there may be two or three layers of the first passivation layer, and those skilled in the art may select the first passivation layer according to actual needs, which is not limited in this embodiment. Hereinafter, a two-layer first passivation layer will be described in detail with reference to the accompanying drawings.

Preferably, the forming a metal bump on the patterned first passivation layer, the metal bump being electrically connected to the blind metal via, includes:

and forming metal wiring lines on the rest first passivation layers except the first passivation layer on the topmost layer after patterning, wherein the metal wiring lines of each layer are electrically connected with the metal blind holes through the corresponding via holes.

Illustratively, as shown in fig. 4, a metal wire 140 may be formed on the patterned first passivation layer 131 by using electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal wire 140 is electrically connected to the metal blind via 120 through the corresponding via hole 131 a. Of course, a person skilled in the art may also select another way to form a metal wire on the patterned first passivation layer, so that the metal wire is electrically connected to the metal blind via through the corresponding via hole, which is not limited in this embodiment. The thickness of the metal wire 140 may be in a range of 3 μm to 15 μm, and those skilled in the art may select the thickness according to actual needs, which is not limited in this embodiment.

Illustratively, as shown in fig. 5, a first passivation layer 132 may be further formed on the first passivation layer 131. The process of forming the first passivation layer 132 in this step may be deposition, sputtering, or other processes, which is not limited in this embodiment. The first passivation layer 132 may be made of silicon dioxide, silicon nitride, or other materials, and those skilled in the art can select the materials according to actual needs, which is not limited in the embodiment. The first passivation layer 132 completely covers the metal wire 140, and the thickness of the first passivation layer 132 may range from 5 μm to 20 μm, and those skilled in the art may also select the thickness according to actual needs, which is not limited in this embodiment.

Illustratively, as shown in fig. 5, the first passivation layer 132 is patterned to form a via 132 a. Patterning the first passivation layer 132 may be performed in the following manner: first, a patterned second mask layer is formed on the first passivation layer 132, and then, the second mask layer is used as a mask to etch the first passivation layer 132 at a proper position to form a via hole 132 a. The material of the second mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the first passivation layer 132 may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, the skilled person can also select other ways to pattern the first passivation layer 132 to form the via 132a, which is not limited by the embodiment.

And forming the metal bump on the patterned topmost first passivation layer, wherein the metal bump is electrically connected with the metal blind hole through the via hole on the topmost first passivation layer and the metal wiring of each layer.

For example, as shown in fig. 6, a metal bump 150 may be formed on the patterned first passivation layer 132 by using a plating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. The metal bump 150 is electrically connected to the metal wiring 140 through the via 132a on the first passivation layer 132, and electrically connected to the blind metal via 120 through the via 131a on the first passivation layer 131. Of course, a person skilled in the art may select other ways to form the metal bump 150, so that the metal bump 150 is electrically connected to the metal wire 140 through the via 132a and electrically connected to the blind metal via 120 through the via 131a, which is not limited in this embodiment. The line width range and the line distance range of the metal bump 150 may be respectively 5 μm to 300 μm, and may also be set to other values according to actual requirements, which is not limited in this embodiment. The height of the metal bump 150 may be in a range from 5 μm to 20 μm, or may be set to other values according to actual needs, which is not limited in this embodiment.

According to the preparation method of the chip packaging structure, the metal blind hole, the first passivation layer and the metal bump are designed on the bearing sheet, the metal bump is electrically connected with the metal blind hole through the via hole formed in the first passivation layer, so that the thickness of the metal blind hole exceeds 20 micrometers, the thickness range of the metal blind hole can reach 30 micrometers-100 micrometers, the requirement on the thickness of the passivation layer is lowered, the thinner passivation layer can completely cover the metal blind hole, and the device failure caused by the short circuit of the metal blind hole and the upper metal layer is prevented.

Preferably, the thickness of the metal blind hole ranges from 30 micrometers to 100 micrometers.

Illustratively, as shown in fig. 6, the thickness of the blind metal via 120 may be 30 μm, may also be 100 μm, and may also be 40 μm, 50 μm, 60 μm, and the like, which can be selected by a person skilled in the art according to actual needs, and the embodiment is not limited thereto.

Preferably, the thickness of the lowermost first passivation layer among the plurality of first passivation layers is 5 μm or more.

Illustratively, as shown in fig. 6, the thickness of the first passivation layer 131 may be 5 μm or more. For example, the thickness of the first passivation layer 131 may be 5 μm, or 6 μm, or 7 μm, or 8 μm, and the like, and those skilled in the art may select the thickness according to actual needs, which is not limited in this embodiment.

Preferably, the thickness of the lowermost first passivation layer of the plurality of first passivation layers ranges from 5 μm to 20 μm.

Illustratively, as shown in fig. 6, the thickness of the first passivation layer 131 may range from 5 μm to 20 μm. For example, the thickness of the first passivation layer 131 may be 5 μm, or 20 μm, or 10 μm, or 15 μm, and the like, and those skilled in the art may select the thickness according to actual needs, which is not limited in the embodiment.

Preferably, the method S100 further comprises the steps of:

and forming a second passivation layer on the metal bump.

Illustratively, as shown in fig. 7, in this step, a second passivation layer 160 is formed on the metal bump 150. The process of forming the second passivation layer in this step may be deposition, sputtering, or other processes, which is not limited in this embodiment. The second passivation layer may be made of silicon dioxide, silicon nitride, or a polymer adhesive such as Polyimide (PI), or another material, and those skilled in the art may select the material according to actual needs, which is not limited in this embodiment. The thickness of the second passivation layer 160 may be in a range from 5 μm to 30 μm, for example, the thickness of the second passivation layer 160 may be 5 μm, 30 μm, 10 μm, 15 μm, and the like, which may be selected by a person skilled in the art as needed, or other values may be selected by a person skilled in the art according to actual needs, and the embodiment is not limited thereto.

And patterning the second passivation layer to form a second via hole corresponding to the metal bump.

Illustratively, as shown in fig. 7, in this step, patterning the second passivation layer 160 may be performed in the following manner: first, a patterned third mask layer is formed on the second passivation layer 160, and then, the second passivation layer 160 is etched at a suitable position by using the third mask layer as a mask, so as to form a second via hole 160a corresponding to the metal bump 150. The material of the third mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the second passivation layer may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, a person skilled in the art may also select other ways to pattern the second passivation layer to form a second via corresponding to the metal bump, which is not limited in this embodiment.

And forming a solder ball in the second via hole.

Illustratively, as shown in fig. 8, in this step, a solder ball 170 may be formed in the second via 160a by ball-planting, printing, electroplating, electroless plating, or the like. The solder ball 170 is electrically connected to the metal bump 150 through the second via 160a, the metal wiring 140 through the via 132a, and the blind metal via 120 through the via 131 a. Of course, a person skilled in the art may also form a solder ball in the second via through other processes, which is not limited by the embodiment.

The second passivation layer and the solder balls are arranged, so that the subsequent use of the packaging structure can be facilitated.

In another aspect of the present invention, a chip package structure is provided, which includes a carrier, a first passivation layer, and a metal bump. The package structure may be formed by the preparation method described above, and reference may be made to the related description, which is not described herein again.

As shown in fig. 8, a chip package structure 100, the chip package structure 100 includes a carrier sheet 110, a first passivation layer 131, and a metal bump 150.

Illustratively, as shown in fig. 8, the carrier sheet 110 includes a first surface 111 and a second surface 112 oppositely disposed along a thickness direction thereof, and the first surface 111 of the carrier sheet 110 is provided with blind metal vias 120.

Illustratively, as shown in fig. 8, the first passivation layer 131 covers the blind metal vias 120, and vias 131a are disposed on the first passivation layer 131, where the vias 131a correspond to the blind metal vias 120.

Illustratively, as shown in fig. 8, a metal bump is disposed on the first passivation layer 132, and the metal bump is electrically connected to the blind metal via 120 through the via 132 a.

Preferably, the number of the first passivation layers is multiple.

Illustratively, as shown in fig. 8, the package structure 100 may include two first passivation layers, i.e., a first passivation layer 131 and a first passivation layer 132. That is, the package structure 100 may have only one first passivation layer, or may have two or three or more first passivation layers, which can be selected by those skilled in the art according to actual needs, and the embodiment does not limit the present invention.

Preferably, metal wirings are arranged on the rest first passivation layers except the topmost first passivation layer, and each layer of metal wirings is electrically connected with the metal blind hole through the corresponding via hole.

Exemplarily, as shown in fig. 8, a metal wiring 140 is disposed on the first passivation layer 131, and the metal wiring 140 is electrically connected to the blind metal via 120 through a corresponding via 131 a.

Preferably, the metal bump is disposed on the topmost first passivation layer, and the metal bump is electrically connected to the metal blind via through holes on the topmost first passivation layer and the metal wiring of each layer.

Illustratively, as shown in fig. 8, the metal bump 150 is disposed on the topmost first passivation layer 132, and the metal bump 150 is electrically connected to the metal wire 140 through a via 132a on the topmost first passivation layer 132 and electrically connected to the blind metal via 120 through a via 131 a.

It should be noted that the specific material of each structure is not limited in this embodiment, and those skilled in the art can select the material according to actual needs. For example, the carrier sheet may be made of silicon, glass, metal, an organic substrate, or other materials, and the first passivation layer may be made of silicon dioxide, silicon nitride, or other materials, which is not limited in this embodiment.

Preferably, the thickness of the metal blind hole ranges from 30 micrometers to 100 micrometers.

Illustratively, as shown in fig. 8, the thickness of the blind metal via 120 may be 30 μm, may also be 100 μm, and may also be 40 μm, 50 μm, and the like, which can be selected by a person skilled in the art according to actual needs, and the embodiment is not limited thereto.

Preferably, the thickness of the lowermost first passivation layer of the plurality of first passivation layers ranges from 5 μm to 20 μm.

Illustratively, as shown in fig. 8, the thickness of the first passivation layer 131 may be 5 μm, or 20 μm, or may also be 10 μm, 15 μm, and so on, which can be selected by a person skilled in the art according to actual needs, and the embodiment is not limited thereto.

According to the chip packaging structure, the metal blind hole, the first passivation layer and the metal bump are designed on the bearing sheet, the metal bump is arranged on the first passivation layer, the metal bump is electrically connected with the metal blind hole through the via hole arranged on the first passivation layer, the thickness of the metal blind hole can exceed 20 micrometers, the thickness range of the metal blind hole can reach 30 micrometers-100 micrometers, the requirement for the thickness of the passivation layer is lowered, the thinner passivation layer can completely cover the metal blind hole, and therefore the device failure caused by short circuit of the metal blind hole and upper metal is prevented.

Preferably, as shown in fig. 8, the package structure 100 further includes a second passivation layer 160 and a solder ball 170.

Illustratively, as shown in fig. 8, the second passivation layer 160 covers the metal bump 150, and a second via 160a corresponding to the metal bump 150 is disposed on the second passivation layer 160. The solder ball 170 is disposed in the second via 160 a. The thickness of the second passivation layer 160 may be in a range from 5 μm to 30 μm, for example, the thickness of the second passivation layer 160 may be 5 μm, 30 μm, 10 μm, 15 μm, and the like, which may be selected by a person skilled in the art as needed, or other values may be selected by a person skilled in the art according to actual needs, and the embodiment is not limited thereto.

The second passivation layer and the solder balls are arranged, so that the subsequent use of the packaging structure can be facilitated.

It should be noted that the specific material of each structure is not limited in this embodiment, and those skilled in the art can select the material according to actual needs. For example, the second passivation layer may be made of silicon dioxide, silicon nitride, or other materials, or may be made of polymer glue such as Polyimide (PI), or other materials, which is not limited in this embodiment.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.