阅读说明：本技术 一种多相dds产生线性调频信号装置和方法 (Device and method for generating linear frequency modulation signals through multiphase DDS ) 是由 周兴云 杨徐路 于翔 黄凯旋 王瀚卿 于 2021-07-02 设计创作，主要内容包括：本申请提供了一种多相DDS产生线性调频信号装置,所述装置包括依次连接的：频率累加器模块、相位累加器模块,S组串联设置的相位补偿模块和相位/幅度转换器模块,并串转换模块、数模转换器模块和低通滤波器模块,其中：当S大于2时,多组串联设置的相位补偿模块和相位/幅度转换器模块并联分别与所述相位累加器模块和所述并串转换模块连接。(The application provides a heterogeneous DDS produces chirp signal device, the device is including connecting gradually: frequency accumulator module, phase accumulator module, S group phase compensation module and phase/amplitude converter module that the series connection set up, parallel-to-serial conversion module, digital-to-analog converter module and low pass filter module, wherein: and when S is larger than 2, a plurality of groups of phase compensation modules and phase/amplitude converter modules which are arranged in series are connected in parallel and are respectively connected with the phase accumulator module and the parallel-serial conversion module.)

1. A device for generating chirp signals with multiphase DDS, the device comprising, connected in series: a frequency accumulator module, a phase accumulator module, S groups of phase compensation modules and phase/amplitude converter modules which are arranged in series, a parallel-serial conversion module, a digital-to-analog converter module and a low-pass filter module,

wherein: and when S is larger than 2, a plurality of groups of phase compensation modules and phase/amplitude converter modules which are arranged in series are connected in parallel and are respectively connected with the phase accumulator module and the parallel-serial conversion module.

2. The apparatus of claim 1, wherein the frequency accumulator module operates at a clock frequency f_{CLK_L}Accumulating the frequency modulation slope word dFTW with the bit width of N once in each CLK _ L clock period, and then adding the frequency modulation slope word dFTW with the bit width of N to the initial frequency word FTW0 to obtain a frequency control word FTW with the bit width of N;

the phase accumulator moduleHas an operating clock frequency of f_{CLK_L}Accumulating the frequency control word FTW with the bit width N once in each CLK _ L clock period to obtain a phase accumulated word PHA with the bit width N;

the working clock frequency of the phase compensation module is f_{CLK_L}Based on a set calculation formula, calculating a phase compensation value OFF _ x with a bit width N once in each CLK _ L clock period, and adding the phase compensation value OFF _ x with the bit width N to a phase accumulation word PHA with the bit width N to obtain the phase accumulation word PHA _ x with the bit width N after phase compensation;

the working clock frequency of the phase/amplitude converter module is f_{CLK_L}Performing truncation processing on the phase accumulation word PHA _ x with the bit width of N in each CLK _ L clock cycle to obtain the phase accumulation word with the bit width of K, then using the phase accumulation word with the bit width of K as an address of a ROM (read only memory) table for table lookup, completing phase-to-amplitude conversion, and obtaining the phase accumulation word with the bit width of M and the rate of f_{CLK_L}The digital amplitude signal DIG _ x;

the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}High-speed digital amplitude signal H _ DIG;

the frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

and the low-pass filter module is used for carrying out low-pass filtering on the analog signal to obtain a finally required linear frequency modulation signal LFM.

3. The apparatus of claim 2, wherein the phase compensation module calculates a phase difference between a phase accumulation word generated by the multi-phase DDS and a phase accumulation word generated by the single-phase DDS, based on a predetermined calculation formula, and then compensates the phase accumulation word of each phase of the multi-phase DDS, so that the phase accumulation words generated by the multi-phase DDS are equal to the phase accumulation word generated by the single-phase DDS, thereby realizing that the chirp signals generated by the multi-phase DDS are identical to the chirp signals generated by the single-phase DDS.

4. The apparatus of claim 2, wherein the parallel-to-serial conversion module is implemented in an FPGA chip and/or a DAC chip.

5. A method of generating a chirp signal with a multiphase DDS, the method comprising the steps of:

step 1: the frequency of the working clock of the frequency accumulator module, the phase compensation module and the phase/amplitude converter module is f_{CLK_L}And the working clock frequency of the input end of the parallel-serial converter module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial converter module is f_{CLK_H}The frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Wherein S is the number of phases of the multiphase DDS, as shown in the following formula:

f_{CLK_H}＝f_{CLK_L}×S

step 2: according to the initial frequency f of the linear frequency modulation signal₀In Hz, conversion rate f of the digital-to-analog converter_{CLK_H}In Hz, a starting frequency word F0 with a bit width N is calculated as follows:

and step 3: according to the chirp rate beta of the chirp signal, the unit is Hz/s, and a chirp rate word dF with a bit width of N is calculated, as shown in the following formula:

and 4, step 4: according to the phase number S of the multiphase DDS, an initial frequency word FTW0 with a bit width N and a chirp rate word dFTW with a bit width N of the multiphase DDS are calculated as follows:

FTW0＝F0×S

dFTW＝dF×S

and 5: the operating clock frequency of the frequency accumulator module is f_{CLK_L}Accumulating the chirp rate word dFTW with the bit width N once in each CLK _ L clock cycle, and then adding the accumulated chirp rate word dFTW with the start frequency word FTW0 with the bit width N to obtain a frequency control word FTW with the bit width N, as shown in the following formula:

step 6: the operating clock frequency of the phase accumulator module is f_{CLK_L}Once accumulating the frequency control word FTW with the bit width N every CLK _ L clock cycle to obtain a phase accumulated word PHA with the bit width N, as shown in the following equation:

and 7: the phase accumulation words PHA are divided into S paths which enter S phase compensation modules respectively;

and 8: the working clock frequency of the phase compensation module is f_{CLK_L}In each phase compensation module, a phase compensation value OFF _ x with a bit width N is calculated once every CLK _ L clock cycle, and the phase accumulation word PHA is added to the phase compensation word OFF _ x of each phase to obtain a compensated phase compensation word PHA _ x, as shown in the following formula:

PHA _ x [ n ] + PHA _ x [ n ], where x is 1 to S

And step 9: the operating clock frequency of the phase/amplitude converter module is f_{CLK_L}In each phase/amplitude converter block, the phase accumulation word PHA _ x with the bit width N is truncated every CLK _ L clock cycle,obtaining a phase accumulation word with the bit width of K, then using the phase accumulation word with the bit width of K as an address of a ROM table for table lookup, completing the conversion from the phase to the amplitude, and obtaining a phase accumulation word with the bit width of M and the rate of f_{CLK_L}The digital amplitude signal DIG _ x;

step 10: the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}High-speed digital amplitude signal H _ DIG;

step 11: the working clock frequency of the DAC module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

step 12: the analog signal ANA is input to a low-pass filter module to filter the analog signal, so as to obtain a required linear frequency modulation signal LFM.

6. The method of claim 5, wherein the phase compensation module, when calculating the phase compensation word, comprises the steps of:

step A: the working clock frequency of the phase compensation module is f_{CLK_L}Corresponding phase compensation words OFF _1 to OFF _ S are calculated in each CLK _ L clock period, and S phase compensation modules are shared, wherein the specific calculation formula is as follows:

OFF _ x [ n ] - (S-x) × F0, where x is 1 to S

Wherein d _ x [ n ] is used to compensate for the phase difference introduced by dF in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals, (S-x) xf 0 is used to compensate for the phase difference introduced by F0 in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals;

and B: the formula for d _ x [ n ] is shown below:

d _ x [ n ] ═ d _ S [ n-1] + c _ x [ n ], where x is 1 to S

Where d _ S [ n-1] is the previous CLK _ L clock cycle, the S-th phase of the multi-phase DDS is used to compensate for the phase difference dF introduced when the multi-phase DDS generates the chirp signal relative to the single-phase DDS generates the chirp signal, and the initial value of d _ S [ n-1], i.e., the value when n is 1, is as follows:

d_S[0]＝0

and C: the formula for c _ x [ n ] is shown below:

c _ x [ n +1] ═ c _ x [ n ] + (x-1) × sxdf, where x is 1 to S

The initial value of c _ x [ n ], i.e., the value at which n is 1, is represented by the following formula:

wherein x is 1 to S.

Technical Field

The invention relates to the technical field of generating linear frequency modulation signals by a DDS (direct digital synthesizer), in particular to a device and a method for generating linear frequency modulation signals by a multiphase DDS.

Background

With the progress of the technology, the rates of the DDS chip and the DAC chip are faster and faster, the frequency of a signal generated by using the DDS technology is higher and higher, and the bandwidth is larger and larger, and the bottleneck of restriction is often higher than the working frequency of the FPGA and the communication control rate of the FPGA and the DDS chip.

For the FPGA, the working frequency of the logic and related resources of the mainstream FPGA in the market is about 500MHz at the fastest speed, and if the complexity, reliability and the like of the program design are considered, the highest working frequency of the logic and time sequence design in the general program is more suitable between 100MHz and 200 MHz.

For the DDS chip, taking ADI AD9914 as an example, its nominal operating frequency is 3.5GHz, and the part operating at this frequency includes the phase accumulator, the phase/amplitude converter and the digital-to-analog converter, while its frequency accumulator has an operating frequency of 1/24 of 3.5GHz, that is, 145.83 MHz.

Considering the fact that the speed of a DAC chip is higher and higher, but the working frequency of logic design in an FPGA is difficult to improve, a plurality of DDSs can be realized in the FPGA to generate a plurality of paths of low-speed digital signals, then a path of high-speed digital signals is generated through a parallel-serial converter and then sent to a digital-to-analog converter, and finally linear frequency modulation signals with high frequency and large bandwidth are generated.

A plurality of DDSs are realized in an FPGA, each DDS generates S-path low-speed digital signals, the S-path low-speed digital signals are converted into 1-path high-speed digital signals through an S:1 parallel-serial converter, the speed of the digital signals is increased by S times, and then the high-speed digital signals are sent to a digital-to-analog converter to generate required analog signals.

One problem with multi-phase DDS generated chirp signals is how to compensate for the phase difference between the phase accumulated words of the multi-phase DDS generated chirp signal and the phase accumulated words of the single-phase DDS generated chirp signal, which phase difference is relative to the chirp signal start frequency f₀Is related to the chirp rate beta of the chirp signal and varies with the clock period.

The invention provides a device and a method for generating a linear frequency modulation signal by a multiphase DDS (direct digital synthesizer) aiming at the problems, thereby solving the problem that the linear frequency modulation signal generated by the multiphase DDS is inconsistent with the linear frequency modulation signal generated by a single-phase DDS.

Disclosure of Invention

In order to overcome the deficiencies in the prior art, the present application provides a device for generating a chirp signal by a multiphase DDS, the device comprising: a frequency accumulator module, a phase accumulator module, S groups of phase compensation modules and phase/amplitude converter modules which are arranged in series, a parallel-serial conversion module, a digital-to-analog converter module and a low-pass filter module,

wherein: and when S is larger than 2, a plurality of groups of phase compensation modules and phase/amplitude converter modules which are arranged in series are connected in parallel and are respectively connected with the phase accumulator module and the parallel-serial conversion module.

In one possible implementation, the frequency accumulator module has an operating clock frequency f_{CLK_L}Accumulating the frequency modulation slope word dFTW with the bit width of N once in each CLK _ L clock period, and then adding the frequency modulation slope word dFTW with the bit width of N to the initial frequency word FTW0 to obtain a frequency control word FTW with the bit width of N;

the working clock frequency of the phase accumulator module is f_{CLK_L}Accumulating the frequency control word FTW with the bit width N once in each CLK _ L clock period to obtain a phase accumulated word PHA with the bit width N;

the working clock frequency of the phase compensation module is f_{CLK_L}Based on a set calculation formula, calculating a phase compensation value OFF _ x with a bit width N once in each CLK _ L clock period, and adding the phase compensation value OFF _ x with the bit width N to a phase accumulation word PHA with the bit width N to obtain the phase accumulation word PHA _ x with the bit width N after phase compensation;

the working clock frequency of the phase/amplitude converter module is f_{CLK_L}Performing truncation processing on the phase accumulation word PHA _ x with the bit width of N in each CLK _ L clock cycle to obtain the phase accumulation word with the bit width of K, then using the phase accumulation word with the bit width of K as an address of a ROM (read only memory) table for table lookup, completing phase-to-amplitude conversion, and obtaining the phase accumulation word with the bit width of M and the rate of f_{CLK_L}The digital amplitude signal DIG _ x;

the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}High-speed digital amplitude signal H _ DIG;

the frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

and the low-pass filter module is used for carrying out low-pass filtering on the analog signal to obtain a finally required linear frequency modulation signal LFM.

In a possible implementation manner, the phase compensation module calculates, in real time, a phase difference between a phase accumulation word generated by the multi-phase DDS and a phase accumulation word generated by the single-phase DDS, based on a set calculation formula, and then compensates the phase accumulation word of each phase of the multi-phase DDS, so that the phase accumulation words generated by the phase accumulation word generated by the multi-phase DDS and the phase accumulation word generated by the single-phase DDS are equal, thereby realizing that the chirp signal generated by the multi-phase DDS is identical to the chirp signal generated by the single-phase DDS.

In one possible implementation manner, the parallel-to-serial conversion module is implemented in an FPGA chip and/or a DAC chip.

In another aspect, the present application discloses a method for generating a chirp signal by a multiphase DDS, the method comprising the steps of:

step 1: the frequency of the working clock of the frequency accumulator module, the phase compensation module and the phase/amplitude converter module is f_{CLK_L}And the working clock frequency of the input end of the parallel-serial converter module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial converter module is f_{CLK_H}The frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Wherein S is the number of phases of the multiphase DDS, as shown in the following formula:

f_{CLK_H}＝f_{CLK_L}×S

step 2: according to the initial frequency f of the linear frequency modulation signal₀In Hz, conversion rate f of the digital-to-analog converter_{CLK_H}In Hz, a starting frequency word F0 with a bit width N is calculated as follows:

and step 3: according to the chirp rate beta of the chirp signal, the unit is Hz/s, and a chirp rate word dF with a bit width of N is calculated, as shown in the following formula:

and 4, step 4: according to the phase number S of the multiphase DDS, an initial frequency word FTW0 with a bit width N and a chirp rate word dFTW with a bit width N of the multiphase DDS are calculated as follows:

FTW0＝F0×S

dFTW＝dF×S

and 5: the operating clock frequency of the frequency accumulator module is f_{CLK_L}Accumulating the chirp rate word dFTW with the bit width N once in each CLK _ L clock cycle, and then adding the accumulated chirp rate word dFTW with the start frequency word FTW0 with the bit width N to obtain a frequency control word FTW with the bit width N, as shown in the following formula:

step 6: the operating clock frequency of the phase accumulator module is f_{CLK_L}Once accumulating the frequency control word FTW with the bit width N every CLK _ L clock cycle to obtain a phase accumulated word PHA with the bit width N, as shown in the following equation:

and 7: the phase accumulation words PHA are divided into S paths which enter S phase compensation modules respectively;

and 8: the working clock frequency of the phase compensation module is f_{CLK_L}In each phase compensation block, a phase compensation value OFF _ x with a bit width N is calculated once per CLK _ L clock cycle, and a phase accumulation word is added to the phasePHA is added to the phase compensation word OFF _ x for each phase to obtain a compensated phase compensation word PHA _ x, as shown in the following equation:

PHA _ x [ n ] + PHA _ x [ n ], where x is 1 to S

And step 9: the operating clock frequency of the phase/amplitude converter module is f_{CLK_L}In each phase/amplitude converter module, each CLK _ L clock cycle truncates the phase accumulation word PHA _ x with the bit width of N to obtain the phase accumulation word with the bit width of K, and then the phase accumulation word with the bit width of K is used as the address of a ROM table to be subjected to table lookup to complete the phase-to-amplitude conversion to obtain the phase accumulation word with the bit width of M and the rate of f_{CLK_L}The digital amplitude signal DIG _ x;

step 10: the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}High-speed digital amplitude signal H _ DIG;

step 11: the working clock frequency of the DAC module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

step 12: the analog signal ANA is input to a low-pass filter module to filter the analog signal, so as to obtain a required linear frequency modulation signal LFM.

In one possible implementation, the phase compensation module, when calculating the phase compensation word, includes the following steps:

step A: the working clock frequency of the phase compensation module is f_{CLK_L}Corresponding phase compensation words OFF _1 to OFF _ S are calculated in each CLK _ L clock period, and S phase compensation modules are shared, wherein the specific calculation formula is as follows:

OFF _ x [ n ] - (S-x) × F0, where x is 1 to S

Wherein d _ x [ n ] is used to compensate for the phase difference introduced by dF in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals, (S-x) xf 0 is used to compensate for the phase difference introduced by F0 in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals;

and B: the formula for d _ x [ n ] is shown below:

d _ x [ n ] ═ d _ S [ n-1] + c _ x [ n ], where x is 1 to S

Where d _ S [ n-1] is the previous CLK _ L clock cycle, the S-th phase of the multi-phase DDS is used to compensate for the phase difference dF introduced when the multi-phase DDS generates the chirp signal relative to the single-phase DDS generates the chirp signal, and the initial value of d _ S [ n-1], i.e., the value when n is 1, is as follows:

d_S[0]＝0

and C: the formula for c _ x [ n ] is shown below:

c _ x [ n +1] ═ c _ x [ n ] + (x-1) × sxdf, where x is 1 to S

The initial value of c _ x [ n ], i.e., the value at which n is 1, is represented by the following formula:

wherein x is 1 to S. .

By adopting the technical means, compared with the prior art, the method has the following beneficial effects:

1. according to the invention, by adding a phase compensation module and combining a given calculation formula, the phase difference between a phase accumulation word of a multi-phase DDS generated chirp signal and a phase accumulation word of a single-phase DDS generated chirp signal is calculated in real time, and then the phase accumulation word of each phase of the multi-phase DDS is compensated, so that the phase accumulation word generated by the multi-phase DDS is equal to the phase accumulation word generated by the single-phase DDS, and the consistency of the chirp signal generated by the multi-phase DDS and the chirp signal generated by the single-phase DDS is realized;

2. the calculation formula provided by the invention can realize the phase compensation of any multi-phase DDS generated linear frequency modulation signal;

3. the invention introduces the phase compensation module, so that the device can complete the function of generating the linear frequency modulation signal by the multiphase DDS by only using one frequency accumulator and one phase accumulator, and the structure of the device for generating the linear frequency modulation signal by the multiphase DDS is simplified.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic block diagram of an apparatus for generating chirp signals with a multiphase DDS in accordance with the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention is realized by the following technical proposal, a device for generating linear frequency modulation signals by multiphase DDS, the phase difference between a phase accumulation word of a multi-phase DDS generating a linear frequency modulation signal and a phase accumulation word of a single-phase DDS generating the linear frequency modulation signal is calculated in real time by adding a phase compensation module and combining a given calculation formula, then, the phase accumulation words of each phase of the multi-phase DDS are compensated, so that the phase accumulation words generated by the multi-phase DDS and the phase accumulation words generated by the single-phase DDS are equal, thereby realizing that the linear frequency modulation signal generated by the multiphase DDS is consistent with the linear frequency modulation signal generated by the single-phase DDS, the method can realize the phase compensation of any multi-phase DDS generated linear frequency modulation signal, and simultaneously, due to the introduction of the phase compensation module, the device can finish the generation of the linear frequency modulation signal by the multiphase DDS only by using one frequency accumulator and one phase accumulator.The function of (c). The device comprises a frequency accumulator module, a phase compensation module, a phase/amplitude converter module, a parallel-serial conversion module, a digital-to-analog converter module and a low-pass filter module. When generating a linear frequency modulation signal, the frequency accumulator module performs primary accumulation on a frequency modulation slope word dFTW with the bit width of N in each CLK _ L clock period, and then adds the frequency modulation slope word dFTW with the bit width of N to an initial frequency word FTW0 to obtain a frequency control word FTW with the bit width of N; the phase accumulator module accumulates the frequency control word FTW with the bit width of N once in each CLK _ L clock period to obtain a phase accumulated word PHA with the bit width of N; the phase compensation module calculates a phase compensation value OFF _ x with a bit width of N once in each CLK _ L clock period, and adds the phase compensation value OFF _ x with the bit width of N to the phase accumulation word PHA with the bit width of N to obtain the phase accumulation word PHA _ x with the bit width of N after phase compensation; the phase/amplitude converter module performs truncation processing on the phase accumulation word PHA _ x with the bit width of N in each CLK _ L clock period to obtain a phase accumulation word with the bit width of K, and then uses the phase accumulation word with the bit width of K as an address of a ROM (read only memory) table to perform table lookup to complete phase-to-amplitude conversion to obtain a digital amplitude signal DIG _ x with the bit width of M; the parallel-serial conversion module has M bit width and f rate for S path in each CLK _ L clock period_{CLK_L}The digital signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital signal with M bit width and f rate_{CLK_H}High speed digital signal H _ DIG; the digital-to-analog converter module performs digital-to-analog conversion on the input high-speed digital signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA; and the low-pass filter module is used for performing low-pass filtering on the analog signal to obtain a finally required linear frequency modulation signal LFM.

As shown in fig. 1, a schematic block diagram of an apparatus for generating chirp signals by using a multiphase DDS provided in the present invention is a preferred embodiment of the schematic block diagram of the apparatus for generating chirp signals by using a multiphase DDS provided in the present invention, which includes:

frequency accumulator module, phase compensation module, phase/amplitude converter module, parallel-to-serial conversion module, digital-to-analog converter module and low-pass filter module

Wherein:

the working clock frequency of the frequency accumulator module is f_{CLK_L}Accumulating the frequency modulation slope word dFTW with the bit width of N once in each CLK _ L clock period, and then adding the frequency modulation slope word dFTW with the bit width of N to the initial frequency word FTW0 to obtain a frequency control word FTW with the bit width of N;

the working clock frequency of the phase accumulator module is f_{CLK_L}Accumulating the frequency control word FTW with the bit width N once in each CLK _ L clock period to obtain a phase accumulated word PHA with the bit width N;

the working clock frequency of the phase compensation module is f_{CLK_L}Calculating a phase compensation value OFF _ x with the bit width N once in each CLK _ L clock period through a given calculation formula, and adding the phase compensation value OFF _ x with the phase accumulation word PHA with the bit width N to obtain the phase accumulation word PHA _ x with the bit width N after phase compensation;

the working clock frequency of the phase/amplitude converter module is f_{CLK_L}Performing truncation processing on the phase accumulation word PHA _ x with the bit width of N in each CLK _ L clock cycle to obtain the phase accumulation word with the bit width of K, then using the phase accumulation word with the bit width of K as an address of a ROM (read only memory) table for table lookup, completing phase-to-amplitude conversion, and obtaining the phase accumulation word with the bit width of M and the rate of f_{CLK_L}The digital amplitude signal DIG _ x;

the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}The high-speed digital amplitude signal H _ DIG of (1), wherein:

the parallel-serial converter of S:1 can be realized in three ways:

(1) implemented in an FPGA, such as oserds and ODDR in an FPGA, or using high-speed transceivers GTP, GTX or GTZ, etc.;

(2) the method is realized in a DAC chip, for example, a digital signal bus of AD9739 of ADI company is divided into two paths, namely DB0 and DB1, and the parallel-serial conversion of the two paths of digital signals is realized in the DAC chip;

(3) the parallel-serial conversion method is realized in an FPGA and a DAC chip at the same time, the parallel-serial conversion of P:1 is realized in the FPGA, the parallel-serial conversion of Q:1 is realized in the DAC chip, and the total parallel-serial conversion coefficient is (P multiplied by Q ═ S): 1.

The frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

and the low-pass filter module is used for carrying out low-pass filtering on the analog signal to obtain a finally required linear frequency modulation signal LFM.

Based on the device for generating the chirp signal by the multiphase DDS provided by the embodiment, the invention also discloses a method for generating the chirp signal by the multiphase DDS, and when the chirp signal is generated, the method comprises the following steps:

step 1: the frequency of the working clock of the frequency accumulator module, the phase compensation module and the phase/amplitude converter module is f_{CLK_L}And the working clock frequency of the input end of the parallel-serial converter module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial converter module is f_{CLK_H}The frequency of the working clock of the digital-to-analog converter module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Wherein S is the number of phases of the multiphase DDS, as shown in the following formula:

f_{CLK_H}＝f_{CLK_L}×S

step 2: according to the initial frequency f of the linear frequency modulation signal₀In Hz, conversion rate f of the digital-to-analog converter_{CLK_H}In Hz, a starting frequency word F0 with a bit width N is calculated as follows:

and step 3: according to the chirp rate beta of the chirp signal, the unit is Hz/s, and a chirp rate word dF with a bit width of N is calculated, as shown in the following formula:

and 4, step 4: according to the phase number S of the multiphase DDS, an initial frequency word FTW0 with a bit width N and a chirp rate word dFTW with a bit width N of the multiphase DDS are calculated as follows:

FTW0＝F0×S

dFTW＝dF×S

and 5: the operating clock frequency of the frequency accumulator module is f_{CLK_L}Accumulating the chirp rate word dFTW with the bit width N once in each CLK _ L clock cycle, and then adding the accumulated chirp rate word dFTW with the start frequency word FTW0 with the bit width N to obtain a frequency control word FTW with the bit width N, as shown in the following formula:

step 6: the operating clock frequency of the phase accumulator module is f_{CLK_L}Once accumulating the frequency control word FTW with the bit width N every CLK _ L clock cycle to obtain a phase accumulated word PHA with the bit width N, as shown in the following equation:

and 7: the phase accumulation words PHA are divided into S paths which enter S phase compensation modules respectively;

and 8: the working clock frequency of the phase compensation module is f_{CLK_L}In each phase compensation module, a phase compensation value OFF _ x with a bit width N is calculated once every CLK _ L clock cycle, and the phase accumulation word PHA is added to the phase compensation word OFF _ x of each phase to obtain a compensated phase compensation word PHA _ x, as shown in the following formula:

PHA _ x [ n ] + PHA _ x [ n ], where x is 1 to S

And step 9: the operating clock frequency of the phase/amplitude converter module is f_{CLK_L}At each phase/amplitudeIn the converter module, each CLK _ L clock cycle carries out truncation processing on a phase accumulation word PHA _ x with a bit width of N to obtain the phase accumulation word with the bit width of K, then the phase accumulation word with the bit width of K is used as an address of a ROM (read only memory) table to carry out table lookup to complete phase-to-amplitude conversion, and the phase accumulation word with the bit width of M and the rate of f is obtained_{CLK_L}The digital amplitude signal DIG _ x;

step 10: the working clock frequency of the input end of the parallel-serial conversion module is f_{CLK_L}And the working clock frequency at the output end of the parallel-serial conversion module is f_{CLK_H}，f_{CLK_H}Has a frequency of f_{CLK_L}Where S is the number of phases of the multiphase DDS, each CLK _ L clock cycle has a bit width M for the S-way and a rate f_{CLK_L}The digital amplitude signal DIG _ x is subjected to parallel-serial conversion to obtain a path of digital amplitude signal with the bit width of M and the rate of f_{CLK_H}High-speed digital amplitude signal H _ DIG;

step 11: the working clock frequency of the DAC module is f_{CLK_H}Performing digital-to-analog conversion on the input high-speed digital amplitude signal H _ DIG in each CLK _ H clock period to obtain an analog signal ANA;

step 12: the analog signal ANA is input to a low-pass filter module to filter the analog signal, so as to obtain a required linear frequency modulation signal LFM.

In the method provided in the foregoing embodiment, when the phase compensation module calculates the phase compensation word, the steps include:

step A: the working clock frequency of the phase compensation module is f_{CLK_L}Corresponding phase compensation words OFF _1 to OFF _ S are calculated in each CLK _ L clock period, and S phase compensation modules are shared, wherein the specific calculation formula is as follows:

OFF _ x [ n ] - (S-x) × F0, where x is 1 to S

Wherein d _ x [ n ] is used to compensate for the phase difference introduced by dF in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals, (S-x) xf 0 is used to compensate for the phase difference introduced by F0 in multi-phase DDS generating chirp signals versus single-phase DDS generating chirp signals;

and B: the formula for d _ x [ n ] is shown below:

d _ x [ n ] ═ d _ S [ n-1] + c _ x [ n ], where x is 1 to S

Where d _ S [ n-1] is the previous CLK _ L clock cycle, the S-th phase of the multi-phase DDS is used to compensate for the phase difference dF introduced when the multi-phase DDS generates the chirp signal relative to the single-phase DDS generates the chirp signal, and the initial value of d _ S [ n-1], i.e., the value when n is 1, is as follows:

d_S[0]＝0

and C: the formula for c _ x [ n ] is shown below:

c _ x [ n +1] ═ c _ x [ n ] + (x-1) × sxdf, where x is 1 to S

The initial value of c _ x [ n ], i.e., the value at which n is 1, is represented by the following formula:

wherein x is 1 to S.

The inventive concept is explained in detail herein using specific examples, which are given only to aid in understanding the core concepts of the invention. It should be understood that any obvious modifications, equivalents and other improvements made by those skilled in the art without departing from the spirit of the present invention are included in the scope of the present invention.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

It should be understood that reference to "a plurality" herein means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.