阅读说明：本技术 一种恒流脉冲源 (Constant current pulse source ) 是由 冯林润 刘哲 李骏 杜江文 于 2021-06-07 设计创作，主要内容包括：本申请实施例公开了一种恒流脉冲源,包括：第一数字模拟转换器DAC、放大器单元、电阻单元、开关单元和第二DAC；第一DAC的输入端与预设的电压源相连；所述第一DAC的输出端与所述放大器单元的输入端相连；所述放大器单元的输出端通过电阻单元与所述开关单元相连；所述开关单元的输出端在输出电流不为0时接地,在输出电流为0时与第二DAC的输出端相连。通过该实施例方案,实现了输出高电位恒流、低电位正/反向恒压脉冲,为精确调整输出电压电流参数提供了技术基础。(The embodiment of the application discloses a constant current pulse source, includes: the digital-to-analog converter comprises a first digital-to-analog converter DAC, an amplifier unit, a resistance unit, a switch unit and a second DAC; the input end of the first DAC is connected with a preset voltage source; the output end of the first DAC is connected with the input end of the amplifier unit; the output end of the amplifier unit is connected with the switch unit through a resistance unit; and the output end of the switch unit is grounded when the output current is not 0, and is connected with the output end of the second DAC when the output current is 0. Through the scheme of the embodiment, high-potential constant current and low-potential forward/reverse constant voltage pulses are output, and a technical basis is provided for accurately adjusting output voltage and current parameters.)

1. A constant current pulse source, comprising: the digital-to-analog converter comprises a first digital-to-analog converter DAC, an amplifier unit, a resistance unit, a switch unit and a second DAC;

the input end of the first DAC is connected with a preset voltage source; the output end of the first DAC is connected with the input end of the amplifier unit;

the output end of the amplifier unit is connected with the switch unit through a resistance unit;

and the output end of the switch unit is grounded when the output current is not 0, and is connected with the output end of the second DAC when the output current is 0.

2. The constant current pulse source according to claim 1, wherein the amplifier unit comprises: the circuit comprises a first amplifier, a second amplifier, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

the first end of the first resistor is connected with the output end of the first DAC;

a positive input end of the first amplifier is connected with a second end of the first resistor and a first end of the second resistor;

the second end of the second resistor is connected with the output end of the second amplifier, and the positive input end of the second amplifier is connected with the input end of the resistor unit;

the negative input end of the second amplifier is connected with the output end of the second amplifier;

the negative input end of the first amplifier is connected with the first end of the third resistor and the first end of the fourth resistor;

the second end of the third resistor is grounded;

the second end of the fourth resistor is connected with the source electrode of the first triode;

the output end of the first amplifier is connected with the grid electrode of the first triode; the drain electrode of the first triode is connected with a first positive power supply; the first positive power supply is configured to output a first positive voltage;

and a first end of the fifth resistor is connected with the source electrode of the first triode, and a second end of the fifth resistor is connected with the positive input end of the second amplifier and then serves as the output end of the amplifier unit and is connected with the input end of the resistor unit.

3. The constant current pulse source of claim 2,

a first positive power supply input terminal of the first amplifier is connected with the first positive power supply; the first positive power supply is configured to output a first positive voltage;

the first negative power supply input end of the first amplifier is connected with a first negative power supply; the first negative power supply is configured to output a first negative voltage;

a second positive power supply input end of the second amplifier is connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the second negative power supply input end of the second amplifier is connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

4. The constant current pulse source of claim 2,

a first positive power supply input end of the first amplifier and a second positive power supply input end of the second amplifier are both connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the first negative power supply input end of the first amplifier and the second negative power supply input end of the second amplifier are both connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

5. The constant current pulse source according to claim 1, wherein the amplifier unit comprises: the circuit comprises a first amplifier, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor;

the first end of the first resistor is connected with the output end of the first DAC;

a positive input end of the first amplifier is connected with a second end of the first resistor and a first end of the second resistor;

a second end of the second resistor is connected with a first section of the sixth resistor, a second end of the sixth resistor is connected with a first end of the seventh resistor, and a second end of the seventh resistor is connected with a source electrode of the first triode;

the negative input end of the first amplifier is connected with the first end of the third resistor and the first end of the fourth resistor;

the second end of the third resistor is grounded;

a second end of the fourth resistor is connected with a first end of the fifth resistor, and a second end of the fifth resistor is connected with a source electrode of the first triode;

the output end of the first amplifier is connected with the grid electrode and the source electrode of the first triode; the drain electrode of the first triode is connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage.

6. The constant current pulse source of claim 5,

the first positive power supply input end of the first amplifier is connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the first negative power supply input end of the first amplifier is connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

7. The constant current pulse source according to any one of claims 2 to 4, wherein said first amplifier and said second amplifier use LTC 6275.

8. The constant current pulse source according to any one of claims 1 to 6, wherein the first DAC and the second DAC employ AD5443 and/or AD 5445.

9. The constant current pulse source according to any one of claims 1 to 6, wherein the switching unit comprises: a single pole double throw switch;

the single pole double throw switch includes: a first end point, a second end point, a third end point and a movable knife; the first end point is connected with the output end of the resistance unit;

the fixed end of the movable knife is connected with the first end point;

the movable end of the movable knife is alternatively connected between the second endpoint and the third endpoint;

the second end point is connected with the output end of the second DAC; the third terminal is grounded.

10. The constant current pulse source of claim 9, wherein said single pole double throw switch employs ADG 1419.

Technical Field

The present disclosure relates to power supply design, and more particularly to a constant current pulse source.

Background

In a single device photoelectric performance test, a light emitting array performance evaluation, and a lighting drive of a display panel of an Organic Light Emitting Diode (OLED) and a quantum dot light emitting diode (QLED), a signal source is required very much. Generally, signal sources can be generally classified into a constant type current signal source, a pulse type current signal source, a constant type voltage signal source, and a pulse type voltage signal source according to the type of output signal. At present, a constant current signal source, a constant voltage signal source and a pulse voltage signal source are available on the market, and the design is simple, the market demand is large, so that the variety of products is large, and the market is common. The constant current pulse source is more complex in design and generally used in the characterization of the characteristics of the luminescent material, so that the available schemes are few, most of the constant current pulse source is designed by a laboratory, and the stability, the pulse frequency and the output power of the constant current pulse source are poor.

Disclosure of Invention

The embodiment of the application provides a constant current pulse source which can output high-potential constant current and low-potential forward/reverse constant voltage pulses and provides a technical basis for accurately adjusting output voltage and current parameters.

The embodiment of the application provides a constant current pulse source, which can comprise: the digital-to-analog converter comprises a first digital-to-analog converter DAC, an amplifier unit, a resistance unit, a switch unit and a second DAC;

the input end of the first DAC is connected with a preset voltage source; the output end of the first DAC is connected with the input end of the amplifier unit;

the output end of the amplifier unit is connected with the switch unit through a resistance unit;

and the output end of the switch unit is grounded when the output current is not 0, and is connected with the output end of the second DAC when the output current is 0.

In an exemplary embodiment of the present application, the amplifier unit may include: the circuit comprises a first amplifier, a second amplifier, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

the first end of the first resistor is connected with the output end of the first DAC;

a positive input end of the first amplifier is connected with a second end of the first resistor and a first end of the second resistor;

the second end of the second resistor is connected with the output end of the second amplifier, and the positive input end of the second amplifier is connected with the input end of the resistor unit;

the negative input end of the second amplifier is connected with the output end of the second amplifier;

the negative input end of the first amplifier is connected with the first end of the third resistor and the first end of the fourth resistor;

the second end of the third resistor is grounded;

the second end of the fourth resistor is connected with the source electrode of the first triode;

the output end of the first amplifier is connected with the grid electrode of the first triode; the drain electrode of the first triode is connected with a first positive power supply; the first positive power supply is configured to output a first positive voltage;

and a first end of the fifth resistor is connected with the source electrode of the first triode, and a second end of the fifth resistor is connected with the positive input end of the second amplifier and then serves as the output end of the amplifier unit and is connected with the input end of the resistor unit.

In an exemplary embodiment of the present application, the first positive power supply input of the first amplifier is connected to the first positive power supply; the first positive power supply is configured to output a first positive voltage;

the first negative power supply input end of the first amplifier is connected with a first negative power supply; the first negative power supply is configured to output a first negative voltage;

a second positive power supply input end of the second amplifier is connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the second negative power supply input end of the second amplifier is connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

In an exemplary embodiment of the present application, the first positive power supply input of the first amplifier and the second positive power supply input of the second amplifier are both connected to a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the first negative power supply input end of the first amplifier and the second negative power supply input end of the second amplifier are both connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

In an exemplary embodiment of the present application, the amplifier unit may include: the circuit comprises a first amplifier, a first triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor;

the first end of the first resistor is connected with the output end of the first DAC;

a positive input end of the first amplifier is connected with a second end of the first resistor and a first end of the second resistor;

a second end of the second resistor is connected with a first section of the sixth resistor, a second end of the sixth resistor is connected with a first end of the seventh resistor, and a second end of the seventh resistor is connected with a source electrode of the first triode;

the negative input end of the first amplifier is connected with the first end of the third resistor and the first end of the fourth resistor;

the second end of the third resistor is grounded;

a second end of the fourth resistor is connected with a first end of the fifth resistor, and a second end of the fifth resistor is connected with a source electrode of the first triode;

the output end of the first amplifier is connected with the grid electrode and the source electrode of the first triode; the drain electrode of the first triode is connected with a second positive power supply; the second positive power supply is configured to output a second positive voltage.

In an exemplary embodiment of the present application, the first positive power supply input of the first amplifier is connected to a second positive power supply; the second positive power supply is configured to output a second positive voltage;

the first negative power supply input end of the first amplifier is connected with a second negative power supply; the second negative power supply is configured to output a second negative voltage.

In an exemplary embodiment of the present application, the first DAC and the second DAC may employ AD5443 and/or AD 5445.

In an exemplary embodiment of the present application, the first amplifier and the second amplifier may employ LTC 6275.

In an exemplary embodiment of the present application, the switching unit may include: a single pole double throw switch;

the single pole double throw switch may include: a first end point, a second end point, a third end point and a movable knife; the first end point is connected with the output end of the resistance unit;

the fixed end of the movable knife is connected with the first end point;

the movable end of the movable knife is alternatively connected between the second endpoint and the third endpoint;

the second end point is connected with the output end of the second DAC; the third terminal is grounded.

In an exemplary embodiment of the present application, the single pole, double throw switch may employ an ADG 1419.

Compared with the related art, the embodiment of the application can comprise the following steps: the digital-to-analog converter comprises a first digital-to-analog converter DAC, an amplifier unit, a resistance unit, a switch unit and a second DAC; the input end of the first DAC is connected with a preset voltage source; the output end of the first DAC is connected with the input end of the amplifier unit; the output end of the amplifier unit is connected with the switch unit through a resistance unit; and the output end of the switch unit is grounded when the output current is not 0, and is connected with the output end of the second DAC when the output current is 0. Through the scheme of the embodiment, high-potential constant current and low-potential forward/reverse constant voltage pulses are output, and a technical basis is provided for accurately adjusting output voltage and current parameters.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a block diagram of a constant current pulse source according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a constant current pulse source according to an embodiment of the present disclosure;

FIG. 3 is a first circuit diagram of an amplifier unit according to an embodiment of the present application;

FIG. 4 is a second circuit diagram of an amplifier unit according to an embodiment of the present application;

FIG. 5 is a third circuit diagram of an amplifier unit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of current and voltage driving signals of an adjustable pulse width PWM in an OLED and QLED photoelectric performance test according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a linear gradual voltage driving signal in an OLED and QLED photoelectric performance test according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a step-adjustable pulse width PWM voltage driving signal in an OLED and QLED optoelectronic performance test according to an embodiment of the present application.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

The embodiment of the present application provides a constant current pulse source, as shown in fig. 1 and fig. 2, which may include: a first digital-to-analog converter DAC1, an amplifier unit 2, a resistance unit 3, a switching unit 4, and a second DAC 5;

the input end of the first DAC1 is connected with a preset voltage source 6; the output end of the first DAC1 is connected with the input end of the amplifier unit 2;

the output end of the amplifier unit 2 is connected with the switch unit 4 through a resistance unit 3;

the output terminal of the switching unit 4 is grounded when the output current is not 0, and is connected to the output terminal of the second DAC 5 when the output current is 0.

At present, in a single device photoelectric performance test, a light emitting array performance evaluation and a lighting drive of a display panel of an Organic Light Emitting Diode (OLED) and a quantum dot light emitting diode (QLED), a signal source driving scheme is generally an analog scheme and a digital scheme. Currently, analog pixel circuits still dominate, and in the analog scheme, unit pixel circuits can be divided into a voltage control type and a current control type according to the type of input data signals. Since the OLED and the QLED are current mode devices, the stability of the devices under current mode driving is more guaranteed. When a Thin Film Transistor (TFT) in a driving pixel is used as a driving tube of an OLED and a QLED, the linear region of a voltage-current output characteristic curve is narrow, so that the voltage range for adjusting the display gray scale is limited, and although a voltage control type circuit has the characteristic of high response speed, the regulation and control requirement for displaying high gray scale is difficult to meet. The current-controlled (unit) pixel circuit has a current as an input data signal. In general, a current control type unit (pixel) circuit needs to satisfy the following requirements: 1) effectively compensating for drift in threshold voltage; 2) the current following characteristic and the linearity are good; 3) the response speed is as fast as possible; 4) the driving power supply voltage is as low as possible under allowable conditions to reduce power consumption. Most current-controlled pixel circuits receive an input current signal, map the current signal to an output terminal, and store the current signal in a storage capacitor in a pixel, so as to ensure stable output in the whole frame. This puts high demands on the output accuracy and output stability of the current source in the drive design.

In addition, the most direct method of Organic Light Emitting Diode (OLED) and quantum dot light emitting diode (QLED) in the gray scale control is to adjust the amplitude of the LED input current, which seemingly seems to be a simple matter on the surface by amplitude adjustment of gray scale, and actually, it is necessary to consider the precise output of the current source amplitude particularly for good and smooth gray scale adjustment, and since the operating current of the low-power OLED or QLED device is 10mA or less, the range of current adjustment is also limited. The simplest and most preferred application solution is to properly select a driving current (voltage) source with an output adjustable Pulse Width (PWM) function to fulfill the OLED or QLED gray scale control requirements. The important parameter of the driving power supply is the frequency of the output pulse width modulation PWM, and the resolution of the lowest frequency adjustment is lower than 0.1% of the adjustable frequency range so as to achieve the gray resolution of an OLED or QLED device with 8 bits. The output PWM frequency should be increased as much as possible in practical products, for example, the related art research literature suggests that at least 1.25kHz is increased to reduce ghost flicker visible to human eyes. At present, few pulse constant current sources with frequency characteristics, current stability and regulation and control precision which uniformly meet the photoelectric performance test requirements of OLED or QLED devices exist.

In an exemplary embodiment of the present application, a pulsed current source design is provided, including at least the following features:

1) high-potential constant-current and low-potential positive/negative constant-voltage pulses are output, and the amplitude, frequency and duty ratio of current and voltage can be accurately adjusted;

2) outputting time sequence data to an external storage device in real time, wherein the time sequence data comprises forward current, forward voltage, amplitude, frequency and duty ratio data of reverse voltage;

3) the upper computer sends the regulating command and the lower computer throws the parameter record data up, and the communication is realized in a Bluetooth mode. The display of the software and the parameters of the control end is realized in a mobile phone application program (APP) mode, so that the human-computer interaction experience is good;

4) outputting and recording data for a long time continuous signal;

5) the method has a pause restart function.

In the exemplary embodiment of the present application, the most core part of the scheme of the present application is a first DAC and a first DAC, and the second DAC and the first DAC may both adopt AD5443 or AD 5445.

In the exemplary embodiment of the present application, the rise time of the current source (i.e. the constant current pulse source) is 100ns, the voltage formed on the load is also 100ns, if the load is 10mA corresponding to 20V at the maximum, the above-mentioned requirement of the corresponding DAC needs 100ns to be completed from 0000 to FFFF, and the operational amplifier (amplifier unit 2) needs 100ns to be completed from 0V to 20V. The maximum current source and voltage source can be 20V/0.1-200 adjustable steps, and 8bit theory is enough. Here, a DAC with 12 bits is selected to meet the requirement, so the model of the DAC (including the first DAC and the second DAC) can be AD5443 or AD5445, and the setting time (typical value) can be less than 100 ns.

In an exemplary embodiment of the present application, adding the amplifier unit 2 can increase the driving capability and adjust the amplification factor to achieve the amplitude requirement, for example ± 10V.

In the exemplary embodiment of the present application, the parasitic capacitance such as an operational amplifier (amplifier unit) connected to the DAC is ensured to be small in the circuit design.

In the exemplary embodiment of the present application, the amplifier unit 2 may be implemented by selecting an existing op-amp chip. In order to achieve a current source or a voltage source of 20V/100nS, the slew rate of the amplifier unit 2 needs to be more than 200V/uS, according to the requirement, the type of the operational amplifier chip can be selected from LTC6275, the slew rate of the operational amplifier chip is 2200V/uS, any capacitive load can be driven, the voltage range is more than 30V, the maximum bias current of 500nA can be achieved, and the requirements of pulse source amplitude output capacity and stability can be met.

In an exemplary embodiment of the present application, the amplifier unit 2 may also be implemented by a self-designed operational amplification circuit, several specific embodiments of which may be given below.

In an exemplary embodiment of the present application, as shown in fig. 3, a first circuit embodiment of the amplifier unit 2 is given: the amplifier unit 2 may include: the circuit comprises a first amplifier 21, a second amplifier 22, a first triode Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

a first end of the first resistor R1 is connected with an output end of the first DAC 1;

a positive input terminal of the first amplifier 21 is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2;

a second end of the second resistor R2 is connected to the output end of the second amplifier 22, and a positive input end of the second amplifier 22 is connected to the input end of the resistance unit 3;

the negative input end of the second amplifier 22 is connected with the output end of the second amplifier 22;

a negative input terminal of the first amplifier 22 is connected to a first terminal of the third resistor R3 and a first terminal of the fourth resistor R4;

a second end of the third resistor R3 is grounded;

a second end of the fourth resistor R4 is connected to the source of the first transistor Q1;

the output end of the first amplifier 21 is connected with the grid electrode of the first triode Q1; the drain electrode of the first triode Q1 is connected with a first positive power supply U11; the first positive power supply U11 is configured to output a first positive voltage;

a first end of the fifth resistor R5 is connected to the source of the first transistor Q1, and a second end of the fifth resistor R5 is connected to the positive input end of the second amplifier 22 and then serves as the output end of the amplifier unit 2, and is connected to the input end of the resistor unit 3.

In an exemplary embodiment of the present application, the first positive power supply input of the first amplifier 21 is connected to the first positive power supply U11; the first positive power supply U11 is configured to output a first positive voltage (which may be 1.5V);

the first negative power supply input end of the first amplifier 21 is connected with a first negative power supply U12; the first negative power supply U12 is set to output a first negative voltage (which may be-1.5V);

a second positive power supply input of the second amplifier 22 is connected to a second positive power supply U21; the second positive power supply U21 is set to output a second positive voltage (which may be 3.0V);

the second negative power supply input end of the second amplifier 22 is connected with a second negative power supply U22; the second negative power supply U22 is set to output a second negative voltage (which may be-2.5V).

In the exemplary embodiment of the present application, with the above-described amplifier unit 2, it can be ensured that the power supply is constant under a constant current condition; and the larger the load, the smaller the inputtable voltage, and the smaller the load, the larger the inputtable voltage. For example, when the load is 1k Ω, the input voltage is 0-10V; when the load is 100 omega, the input voltage is 0-50V.

In the exemplary embodiment of the present application, when the load decreases, the second resistor R2 may decrease (coarse adjustment); the fourth resistor R4 can be reduced (fine-tuned) according to the output, the resistance is increased, and the output is larger; the resistance becomes small and the output becomes small. When the load increases, the second resistor R2 increases, and the fourth resistor R4 can be adjusted according to the output.

In the exemplary embodiment of the present application, the resistance values of the first resistor R1 and the third resistor R3 are suggested to be consistent.

In the exemplary embodiment of the present application, based on the first circuit embodiment described above, the following settings may also be made for the power supply sources of the first amplifier 21 and the second amplifier 22: as shown in fig. 4, the first positive power supply input terminal of the first amplifier 21 and the second positive power supply input terminal of the second amplifier 22 are both connected to a second positive power supply U21; the second positive power supply U21 may be configured to output a second positive voltage;

the first negative power supply input end of the first amplifier 21 and the second negative power supply input end of the second amplifier 22 are both connected with a second negative power supply U22; the second negative power supply U22 is configured to output a second negative voltage.

In the exemplary embodiment of the present application, the first amplifier 21 and the second amplifier 22 are based on the above-described power supply source, and the input voltage of the amplifier unit 2 may be 0 to 25V, which is lower than 5V of the operational amplifier (LT 6274); the output current may be 0-25 mA. In the state of ensuring the constant current, if the load increases, the resistance value of the first resistor R1 may be decreased; if the load decreases, the resistance of the first resistor R1 may be increased.

In the exemplary embodiment of the application, when the input voltage is constant, the larger the ratio R4/R3 is, the larger the output is, and the smaller the ratio R4/R3 is, the smaller the output is; input and output relationships can be fine-tuned based on this principle.

In the exemplary embodiment of the present application, the R3 and R1 resistance values are suggested to be consistent.

In an exemplary embodiment of the present application, a second circuit embodiment of the amplifier unit 2 is given, as shown in fig. 5: the amplifier unit 2 may include: the circuit comprises a first amplifier 21, a first triode Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;

in an exemplary embodiment of the present application, a first terminal of the first resistor R1 is connected to an output terminal of the first DAC 1;

a positive input terminal of the first amplifier 21 is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2;

a second end of the second resistor R2 is connected to a first segment of the sixth resistor R6, a second end of the sixth resistor R6 is connected to a first end of the seventh resistor R7, and a second end of the seventh resistor R7 is connected to a source of the first transistor Q1;

a negative input terminal of the first amplifier 21 is connected to a first terminal of the third resistor R3 and a first terminal of the fourth resistor R4;

a second end of the third resistor R3 is grounded;

a second end of the fourth resistor R4 is connected to a first end of the fifth resistor R5, and a second end of the fifth resistor R5 is connected to a source of the first transistor Q1;

the output end of the first amplifier 21 is connected with the grid electrode and the source electrode of the first triode Q1; the drain electrode of the first triode Q1 is connected with a second positive power supply U21; the second positive power supply U21 is configured to output a second positive voltage.

In an exemplary embodiment of the present application, the first positive power supply input of the first amplifier 21 is connected to a second positive power supply U21; the second positive power supply U21 is set to output a second positive voltage (which may be 3.0V);

the first negative power supply input end of the first amplifier 21 is connected with a second negative power supply U22; the second negative power supply U22 is set to output a second negative voltage (which may be-2.5V).

In the exemplary embodiment of the present application, LT6274 may be selected for the first amplifier 21 and the second amplifier 22.

In an exemplary embodiment of the present application, the supply voltage of the operational amplifier (LT6274) determines the circuit input voltage of the amplifier unit 2 to be 0-30V and the current output range to be 0-30 mA. Based on this amplifier unit 2, when the state of constant current is ensured, if the load increases, the resistance value of the seventh resistor R7 may be decreased; if the load decreases, the resistance of the seventh resistor R7 may be increased. When the input voltage of the amplifier unit 2 is constant, the larger the ratio R4/R3 is, the larger the output is, and the smaller the ratio R4/R3 is, the smaller the output is; (input to output relationships can be fine tuned).

In the exemplary embodiment of the present application, the resistance values of the first resistor R1 and the third resistor R3 are suggested to be consistent.

In an exemplary embodiment of the present application, the eighth resistor R8 in fig. 3-5 may be used as a load, and the eighth resistor R8 may be connected in parallel with the first capacitor C1.

A first end of the eighth resistor R8 is connected to an output terminal (current output terminal) of the amplifier unit; a second terminal of the eighth resistor R8 is connected to ground.

In an exemplary embodiment of the present application, as shown in fig. 2, the switching unit 4 may include: single pole double throw switch SPDT.

The single pole double throw switch may include: a first end point O, a second end point A, a third end point B and a movable knife; the first end point O is connected with the output end of the resistance unit 2;

the fixed end of the movable knife is connected with the first end point O;

the movable end of the movable knife is selectively connected between the second end point A and the third end point B;

the second end point A is connected with the output end of the second DAC; the third terminal B is grounded.

In an exemplary embodiment of the present application, in order to output the required PWM square wave, the voltage current source output (DUT), i.e., the output of the constant current pulse source, needs to be applied with an adjustable reverse bias voltage at an output current of 0. Here, an analog switch, such as the single pole double throw switch described above, is selected as the switch. When normal current is output, the switch of the single-pole double-throw Switch (SPDT) is switched off, and the movable knife of the single-pole double-throw Switch (SPDT) is switched to the third end point, namely the grounding end; when the current source has no current, namely the output current is 0, a single-pole double-throw Switch (SPDT) is closed, namely the movable knife is switched to the second DAC end, and the voltage of the constant current pulse source can be set by the second DAC and can be adjusted through the software of the mobile phone application program end. In addition, time series data can be recorded in real time and output to an upper computer (for example, a mobile phone application program), and the time series data can comprise the amplitude of forward current, the amplitude of forward voltage, the amplitude of reverse voltage, frequency, duty ratio data and the like.

In the exemplary embodiment of the application, the upper computer regulates and controls sending of commands such as the amplitude of current, the amplitude of voltage, frequency and duty ratio, and upward throwing of parameter recording data such as the amplitude of forward current, the amplitude of forward voltage and the amplitude of reverse voltage, frequency and duty ratio data of the lower computer can be realized through a Bluetooth mode. The control function and parameter display of the control command can be realized in a mobile phone application program (APP) mode, and the human-computer interaction experience is good.

In an exemplary embodiment of the present application, the constant current pulse source of the embodiment of the present application can continuously output high-potential constant current and low-potential positive/negative constant voltage pulses as a driving signal source for a device long-time stability test for a long time, and can also continuously record data for a long time. And the constant current pulse source has a pause restart function, after the restart, the high potential constant current is realized, the output of the low potential positive/negative constant voltage pulse can be normally recovered, and the recording of parameters such as the amplitude, the frequency, the duty ratio and the like of the forward current, the forward voltage and the reverse voltage can be continuously carried out.

In the exemplary embodiment of the present application, the selection of the switch unit 3 is also one of the keys of the function implementation, in the embodiment of the present application, the model of the analog switch (the single-pole double-throw switch) may be selected as ADG1419, there is a delay of about 100ns from enable to output, in addition, this switch has an internal resistance of about 2.1 ohms, and under normal 10mA, there is a voltage drop of 0.02V across the switch, which satisfies the requirements of the pulse source for response speed and load capacity.

In an exemplary embodiment of the application, the constant-current pulse source driving design disclosed by the embodiment of the application can realize voltage PWM square wave output (as shown in 'output 1' in FIG. 6), the amplitude is adjustable from-10V to +10V, and the output voltage is adjustable with the accuracy of 0.1V. The frequency is 50 Hz-100 kHz adjustable, and the rising and falling edge time of the pulse is less than 100 ns. The pulse width is 1 mus-20 ms. The duty ratio is adjustable from 0% to 100%, and the duty ratio adjustable precision is 1%.

In an exemplary embodiment of the present application, the constant current pulse source driving design disclosed in the embodiment of the present application can realize current PWM square wave output (as shown in "output 2" in fig. 6), the amplitude is adjustable from 0 to +10mA, the output current is adjustable with accuracy of 0.1mA, and the output current accuracy is 1 μ a. The frequency is 50 Hz-100 kHz adjustable, the pulse width is 1 mu s-20 ms, and the rising and falling edge time of the pulse is less than 100 ns. The duty ratio is adjustable from 0% to 100%, and the duty ratio adjustable precision is 1%. When the current amplitude is 0mA, a negative voltage signal (blue part) is loaded, the amplitude is-10-0V adjustable, and the current amplitude is equivalent to a negative weak current.

In an exemplary embodiment of the present application, the constant current pulse source driving design disclosed in the embodiment of the present application can achieve a linearly tapered adjustable voltage output (as shown as "output 3" in fig. 7), the adjustable voltage output has an amplitude of-10V to +10V positive/negative scan, and the voltage is stepped by ± 0.1V.

In an exemplary embodiment of the present application, the constant current pulse source driving design disclosed in the embodiment of the present application can realize step voltage PWM square wave output (as shown in "output 4" in fig. 8), the amplitude is adjustable from-10V to +10V, and the voltage is stepped by ± 0.1V. The pulse width is adjustable within 50-500 ms, and the rising and falling edge time of the pulse is less than 100 ns.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.